KR20090121290A - 인장성 및 압축성 디바이스 영역을 갖는 응력을 받은 ｓｏｉ ｆｅｔ - Google Patents

인장성 및 압축성 디바이스 영역을 갖는 응력을 받은 ｓｏｉ ｆｅｔ Download PDF

Info

Publication number
KR20090121290A
KR20090121290A KR1020097017539A KR20097017539A KR20090121290A KR 20090121290 A KR20090121290 A KR 20090121290A KR 1020097017539 A KR1020097017539 A KR 1020097017539A KR 20097017539 A KR20097017539 A KR 20097017539A KR 20090121290 A KR20090121290 A KR 20090121290A
Authority
KR
South Korea
Prior art keywords
layer
stressed
stress
soi
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1020097017539A
Other languages
English (en)
Korean (ko)
Inventor
두레세티 치담바라오
윌리암 헨손
야오쳉 리우
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인터내셔널 비지네스 머신즈 코포레이션 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR20090121290A publication Critical patent/KR20090121290A/ko
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020097017539A 2007-02-12 2008-02-06 인장성 및 압축성 디바이스 영역을 갖는 응력을 받은 ｓｏｉ ｆｅｔ Abandoned KR20090121290A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/673,716 2007-02-12
US11/673,716 US7632724B2 (en) 2007-02-12 2007-02-12 Stressed SOI FET having tensile and compressive device regions

Publications (1)

Publication Number Publication Date
KR20090121290A true KR20090121290A (ko) 2009-11-25

Family

ID=39685098

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020097017539A Abandoned KR20090121290A (ko) 2007-02-12 2008-02-06 인장성 및 압축성 디바이스 영역을 갖는 응력을 받은 ｓｏｉ ｆｅｔ

Country Status (6)

Country Link
US (1) US7632724B2 (https=)
JP (1) JP5244128B2 (https=)
KR (1) KR20090121290A (https=)
BR (1) BRPI0807243A2 (https=)
TW (1) TW200901367A (https=)
WO (1) WO2008100751A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
JP5299268B2 (ja) * 2007-03-30 2013-09-25 富士通セミコンダクター株式会社 半導体集積回路装置およびその製造方法
US8169025B2 (en) * 2010-01-19 2012-05-01 International Business Machines Corporation Strained CMOS device, circuit and method of fabrication
US9406798B2 (en) 2010-08-27 2016-08-02 Acorn Technologies, Inc. Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
US8642430B2 (en) * 2012-04-09 2014-02-04 GlobalFoundries, Inc. Processes for preparing stressed semiconductor wafers and for preparing devices including the stressed semiconductor wafers
US9406508B2 (en) 2013-10-31 2016-08-02 Samsung Electronics Co., Ltd. Methods of forming a semiconductor layer including germanium with low defectivity
US9209301B1 (en) * 2014-09-18 2015-12-08 Soitec Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers
FR3029011B1 (fr) * 2014-11-25 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede ameliore de mise en contrainte d'une zone de canal de transistor
US9768254B2 (en) 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors
US9685510B2 (en) * 2015-09-10 2017-06-20 International Business Machines Corporation SiGe CMOS with tensely strained NFET and compressively strained PFET
WO2018125120A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Techniques for forming dual-strain fins for co-integrated n-mos and p-mos devices
US10263107B2 (en) * 2017-05-01 2019-04-16 The Regents Of The University Of California Strain gated transistors and method
US10770586B2 (en) * 2018-02-04 2020-09-08 Tower Semiconductor Ltd. Stressing structure with low hydrogen content layer over NiSi salicide
CN115376606B (zh) * 2022-08-11 2024-09-17 深圳市晶存科技股份有限公司 动态随机存储器通道测试方法、系统、装置及存储介质

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3951134B2 (ja) * 2003-07-24 2007-08-01 セイコーエプソン株式会社 半導体装置およびその製造方法
US20070126034A1 (en) * 2003-10-10 2007-06-07 Tokyo Institute Of Technology Semiconductor substrate, semiconductor device and process for producing semiconductor substrate
WO2005112129A1 (ja) * 2004-05-13 2005-11-24 Fujitsu Limited 半導体装置およびその製造方法、半導体基板の製造方法
US7227205B2 (en) 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
JP2006040958A (ja) * 2004-07-22 2006-02-09 Sumco Corp 歪みｓｏｉ基板
US7064045B2 (en) * 2004-08-30 2006-06-20 Miradia Inc. Laser based method and device for forming spacer structures for packaging optical reflection devices
KR100585157B1 (ko) 2004-09-07 2006-05-30 삼성전자주식회사 다수의 와이어 브릿지 채널을 구비한 모스 트랜지스터 및그 제조방법
US7125759B2 (en) * 2005-03-23 2006-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor-on-insulator (SOI) strained active areas
US7432149B2 (en) * 2005-06-23 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS on SOI substrates with hybrid crystal orientations
US7381649B2 (en) 2005-07-29 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for a multiple-gate FET device and a method for its fabrication
US20080191285A1 (en) * 2007-02-09 2008-08-14 Chih-Hsin Ko CMOS devices with schottky source and drain regions

Also Published As

Publication number Publication date
JP2010527140A (ja) 2010-08-05
WO2008100751A1 (en) 2008-08-21
BRPI0807243A2 (pt) 2014-06-17
US20080191281A1 (en) 2008-08-14
US7632724B2 (en) 2009-12-15
TW200901367A (en) 2009-01-01
JP5244128B2 (ja) 2013-07-24

Similar Documents

Publication Publication Date Title
KR20090121290A (ko) 인장성 및 압축성 디바이스 영역을 갖는 응력을 받은 ｓｏｉ ｆｅｔ
US7888197B2 (en) Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
JP4814304B2 (ja) 集積回路およびその製造方法
US7410859B1 (en) Stressed MOS device and method for its fabrication
US8557666B2 (en) Methods for fabricating integrated circuits
US8299453B2 (en) CMOS transistors with silicon germanium channel and dual embedded stressors
US7678634B2 (en) Local stress engineering for CMOS devices
US20070020861A1 (en) Method to engineer etch profiles in Si substrate for advanced semiconductor devices
US7485519B2 (en) After gate fabrication of field effect transistor having tensile and compressive regions
US20130277746A1 (en) Integrated circuits having protruding source and drain regions and methods for forming integrated circuits
KR20070024581A (ko) 다수 반도체 층들을 갖는 반도체 디바이스
US8710549B2 (en) MOS device for eliminating floating body effects and self-heating effects
KR20070086303A (ko) 다수의 스택화된 하이브리드 배향 층들을 포함하는 반도체디바이스를 만드는 방법 및 반도체 디바이스
US20070181880A1 (en) Semiconductor device and method for forming the same
US10199392B2 (en) FinFET device having a partially dielectric isolated fin structure
CN101233605A (zh) 用于制造受应力的mos器件的方法
CN110246752A (zh) 集成电路和制造集成电路的方法
KR100618827B1 (ko) ＦｉｎＦＥＴ을 포함하는 반도체 소자 및 그 제조방법
US20050023608A1 (en) Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
KR20030050995A (ko) 고집적 트랜지스터의 제조 방법
JP2007318125A (ja) Ｓｏｉおよびｈｏｔ半導体装置上のｌｏｃｏｓおよびその製造方法
US12211934B2 (en) Semiconductor structure and method for manufacturing the same

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

NORF Unpaid initial registration fee
PC1904 Unpaid initial registration fee

St.27 status event code: A-2-2-U10-U14-oth-PC1904

St.27 status event code: N-2-6-B10-B12-nap-PC1904

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000