JP5234756B2 - パイプライン型ａ／ｄコンバータ - Google Patents

パイプライン型ａ／ｄコンバータ Download PDF

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Publication number
JP5234756B2
JP5234756B2 JP2008182437A JP2008182437A JP5234756B2 JP 5234756 B2 JP5234756 B2 JP 5234756B2 JP 2008182437 A JP2008182437 A JP 2008182437A JP 2008182437 A JP2008182437 A JP 2008182437A JP 5234756 B2 JP5234756 B2 JP 5234756B2
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JP
Japan
Prior art keywords
circuit
sub
converter
pipeline type
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008182437A
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English (en)
Japanese (ja)
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JP2010021918A5 (https=
JP2010021918A (ja
Inventor
康夫 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2008182437A priority Critical patent/JP5234756B2/ja
Priority to US12/463,833 priority patent/US7907077B2/en
Publication of JP2010021918A publication Critical patent/JP2010021918A/ja
Publication of JP2010021918A5 publication Critical patent/JP2010021918A5/ja
Application granted granted Critical
Publication of JP5234756B2 publication Critical patent/JP5234756B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
    • H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
    • H03M1/168—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters and delivering the same number of bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution
    • H03M1/806—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution with equally weighted capacitors which are switched by unary decoded digital signals

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
JP2008182437A 2008-07-14 2008-07-14 パイプライン型ａ／ｄコンバータ Expired - Fee Related JP5234756B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008182437A JP5234756B2 (ja) 2008-07-14 2008-07-14 パイプライン型ａ／ｄコンバータ
US12/463,833 US7907077B2 (en) 2008-07-14 2009-05-11 Pipelined A/D converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008182437A JP5234756B2 (ja) 2008-07-14 2008-07-14 パイプライン型ａ／ｄコンバータ

Publications (3)

Publication Number Publication Date
JP2010021918A JP2010021918A (ja) 2010-01-28
JP2010021918A5 JP2010021918A5 (https=) 2011-05-19
JP5234756B2 true JP5234756B2 (ja) 2013-07-10

Family

ID=41504685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008182437A Expired - Fee Related JP5234756B2 (ja) 2008-07-14 2008-07-14 パイプライン型ａ／ｄコンバータ

Country Status (2)

Country Link
US (1) US7907077B2 (https=)
JP (1) JP5234756B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5671123B2 (ja) * 2010-03-31 2015-02-18 旭化成エレクトロニクス株式会社 パイプライン型ａ／ｄコンバータ
JP5904022B2 (ja) 2012-06-08 2016-04-13 富士通株式会社 Ａｄ変換装置及びａｄ変換方法
JP7563675B2 (ja) * 2020-04-09 2024-10-08 ミネベアミツミ株式会社 信号処理回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404364B1 (en) * 2000-08-24 2002-06-11 Agere Systems Guardian Corp. Multistage converter employing digital dither
JP3968382B2 (ja) * 2001-11-26 2007-08-29 旭化成エレクトロニクス株式会社 パイプライン型ａ／ｄコンバータの試験方法
US6839009B1 (en) * 2003-07-18 2005-01-04 Analog Devices, Inc. Analog-to-digital converter methods and structures for interleavably processing data signals and calibration signals
JP2006086981A (ja) 2004-09-17 2006-03-30 Fujitsu Ltd スイッチトキャパシタ回路およびパイプラインａ／ｄ変換回路
US6987477B1 (en) * 2004-10-04 2006-01-17 National Semiconductor Corporation Pipelined analog-to-digital converter (ADC) with 3-bit ADC and endpoint correction
US7595744B2 (en) * 2007-11-27 2009-09-29 Texas Instruments Incorporated Correcting offset errors associated with a sub-ADC in pipeline analog to digital converters

Also Published As

Publication number Publication date
US20100007542A1 (en) 2010-01-14
US7907077B2 (en) 2011-03-15
JP2010021918A (ja) 2010-01-28

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