JP5227071B2 - 半導体素子の実装方法 - Google Patents
半導体素子の実装方法 Download PDFInfo
- Publication number
- JP5227071B2 JP5227071B2 JP2008114622A JP2008114622A JP5227071B2 JP 5227071 B2 JP5227071 B2 JP 5227071B2 JP 2008114622 A JP2008114622 A JP 2008114622A JP 2008114622 A JP2008114622 A JP 2008114622A JP 5227071 B2 JP5227071 B2 JP 5227071B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- bump
- mounting
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- Wire Bonding (AREA)
Description
本実施形態では、図1に示すように、半導体素子1をセラミックスなどで形成された基板2に実装する例を説明する。また、半導体素子1としては加速度センサを例示する。
実施形態1では半導体素子1に設けたすべてのスタッドバンプ41を同サイズとしたが、本実施形態は実装時に生じる応力をさらに低減することができる実装構造について説明する。本実施形態では、半導体素子3の一面の周部において、サイズの異なる第1バンプ44と第2バンプ45とを配列してある(図7参照)。第2バンプ45は、第1バンプ44よりも半導体素子3からの突出寸法が小さく形成される。本実施形態で示す半導体素子3は、図6に示すように、平面視において外周縁が正方形であって、例えば1〜10mm角程度に形成されている。
2 基板
3 半導体素子
11 素子電極
21 基板電極
41 スタッドバンプ
41a 基部
41b 変形可能部
42 接着部材
42′ 接着剤
43 充填部材
44 第1バンプ
45 第2バンプ
Claims (1)
- 一表面側に金からなる複数個のバンプが突設された半導体素子を各バンプにそれぞれ対応する複数個の基板電極を備える基板に実装するにあたり、少なくとも一部のバンプにはバンプの突出方向において所定の変形限度位置まで塑性変形可能である変形可能部をそれぞれ設けておき、弾性および導電性を有する合成樹脂材料からなり各バンプにそれぞれ密着する接着部材により各バンプをそれぞれ囲繞し、かつ各基板電極に対応する各部位において基板電極と半導体素子の前記一表面との間を接着部材により接着する実装方法であって、
硬化後に接着部材を形成する接着剤を基板に設けた各基板電極にそれぞれ塗布する第1工程と、変形可能部を備える各バンプを対応する各基板電極に位置合わせし半導体素子と基板とが相対的に近付くように加圧する第2工程と、接着剤を硬化させる第3工程とを有し、
第2工程では、加圧時に印加する荷重を調節することにより、変形可能部が変形限度位置までの余裕寸法である変形許容量を残して塑性変形するように、半導体素子と基板との間の隙間寸法を調節することを特徴とする半導体素子の実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008114622A JP5227071B2 (ja) | 2008-04-24 | 2008-04-24 | 半導体素子の実装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008114622A JP5227071B2 (ja) | 2008-04-24 | 2008-04-24 | 半導体素子の実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009267067A JP2009267067A (ja) | 2009-11-12 |
JP5227071B2 true JP5227071B2 (ja) | 2013-07-03 |
Family
ID=41392539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008114622A Expired - Fee Related JP5227071B2 (ja) | 2008-04-24 | 2008-04-24 | 半導体素子の実装方法 |
Country Status (1)
Country | Link |
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JP (1) | JP5227071B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102018104279A1 (de) | 2018-02-26 | 2019-08-29 | Tdk Electronics Ag | Elektronische Vorrichtung |
DE102019130209A1 (de) | 2019-11-08 | 2021-05-12 | Tdk Corporation | Elektronische Vorrichtung und Verfahren zur Herstellung einer elektronischen Vorrichtung |
CN112419892B (zh) * | 2020-11-16 | 2023-01-17 | 武汉天马微电子有限公司 | 一种显示面板和显示装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10256304A (ja) * | 1997-03-07 | 1998-09-25 | Citizen Watch Co Ltd | 半導体装置の製造方法 |
JPH10294330A (ja) * | 1997-04-18 | 1998-11-04 | Matsushita Electric Works Ltd | フリップチップ接合方法 |
JP4030220B2 (ja) * | 1998-04-07 | 2008-01-09 | 新光電気工業株式会社 | 半導体チップの実装構造 |
JP2002299380A (ja) * | 2001-03-30 | 2002-10-11 | Matsushita Electric Works Ltd | 半導体チップ実装構造及び半導体チップ実装方法 |
JP2005303176A (ja) * | 2004-04-15 | 2005-10-27 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
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2008
- 2008-04-24 JP JP2008114622A patent/JP5227071B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2009267067A (ja) | 2009-11-12 |
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