JP5197512B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP5197512B2 JP5197512B2 JP2009157504A JP2009157504A JP5197512B2 JP 5197512 B2 JP5197512 B2 JP 5197512B2 JP 2009157504 A JP2009157504 A JP 2009157504A JP 2009157504 A JP2009157504 A JP 2009157504A JP 5197512 B2 JP5197512 B2 JP 5197512B2
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- voltage
- resistance
- line
- memory cell
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- 239000004065 semiconductor Substances 0.000 title claims description 50
- 230000015654 memory Effects 0.000 claims description 129
- 230000008859 change Effects 0.000 claims description 21
- 238000007667 floating Methods 0.000 claims description 5
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- 230000000052 comparative effect Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 6
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- 229910010413 TiO 2 Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
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- 230000007704 transition Effects 0.000 description 2
- 206010021143 Hypoxia Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
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- 230000008878 coupling Effects 0.000 description 1
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- 230000001419 dependent effect Effects 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
Description
[実施の形態に係る半導体記憶装置の構成]
図1は、本発明の実施の形態に係る半導体記憶装置のブロック図である。この半導体記憶装置は、複数本の行線と、これら行線と交差する複数本の列線とを有し、それらの各交差部にメモリセルが配置されたメモリセル配列41を有する。また、行線を選択する行デコーダ42、列線を選択する列デコーダ43を備える。また、行デコーダ42、列デコーダ43にそれぞれ行アドレス、列アドレスを与え、メモリセル配列41中の読み書きを行うメモリセルを選択する読み出し制御手段である上位ブロック44を備える。電源45は、読み出し、書き込み、消去の、それぞれの動作に対応した、所定の電圧の組み合わせを生成し、行デコーダ42、列デコーダ43に供給する。以下の説明では、通常の半導体記憶装置にならい、行線をワード線、列線をビット線と呼ぶ。
Claims (6)
- 平行に配置された複数の行線と、
前記行線に交差するように配置された複数の列線と、
前記行線と前記列線との各交差部に配置され、抵抗変化素子及び前記抵抗変化素子に直列接続された選択素子を含む複数の記憶素子と、
前記行線を選択する行選択部と、
前記列線を選択する列選択部と、
前記行選択部により選択された選択行線と前記列選択部により選択された選択列線とにそれぞれ所定の選択線電圧を印加するとともに、前記行選択部により選択された選択行線以外の非選択行線と、前記列選択部により選択された選択列線以外の非選択列線に、それぞれ所定の非選択線電圧を印加する電源部と
を備え、
前記電源部と前記非選択行線及び前記非選択列線との間に、所定の抵抗値を有する抵抗素子を有する
ことを特徴とする半導体記憶装置。 - 前記抵抗素子は、複数の第1の抵抗素子及び複数の第2の抵抗素子からなり
前記第1の抵抗素子は、前記非選択行線及び前記非選択列線にそれぞれ設けられている
ことを特徴とする請求項1記載の半導体記憶装置。 - 前記第2の抵抗素子は、前記行選択部と前記電源部との間に設けられるとともに、前記列選択部と前記電源部との間に設けられる
ことを特徴とする請求項2記載の半導体記憶装置。 - 前記第1の抵抗素子の抵抗値は、前記抵抗変化素子と前記選択素子との合成抵抗値の取りうる範囲に含まれている
ことを特徴とする請求項2又は3のいずれか一項に記載の半導体記憶装置。 - 前記行選択部と前記電源部との間に設けられた前記第2の抵抗素子の抵抗値は、直列接続された前記記憶素子及び前記第1の抵抗素子が前記非選択行線の数だけ並列接続された場合の合成抵抗値よりも大きく、
前記列選択部と前記電源部との間に設けられた前記第2の抵抗素子の抵抗値は、直列接続された前記記憶素子及び前記第1の抵抗素子が前記非選択列線の数だけ並列接続された場合の合成抵抗値よりも大きい
ことを特徴とする請求項3又は4のいずれか一項に記載の半導体記憶装置。 - 前記電源部は、前記選択行線及び前記選択列線に前記選択線電圧を印加した場合において、前記非選択線をフローティング状態にしたときの電圧の値と略同一の値を前記非選択行線及び前記非選択列線に印加する
ことを特徴とする、請求項1乃至5のいずれか一項に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009157504A JP5197512B2 (ja) | 2009-07-02 | 2009-07-02 | 半導体記憶装置 |
US12/695,512 US8320156B2 (en) | 2009-07-02 | 2010-01-28 | Semiconductor memory device |
KR1020100020721A KR20110002778A (ko) | 2009-07-02 | 2010-03-09 | 반도체 기억 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009157504A JP5197512B2 (ja) | 2009-07-02 | 2009-07-02 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011014194A JP2011014194A (ja) | 2011-01-20 |
JP5197512B2 true JP5197512B2 (ja) | 2013-05-15 |
Family
ID=43412569
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009157504A Expired - Fee Related JP5197512B2 (ja) | 2009-07-02 | 2009-07-02 | 半導体記憶装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8320156B2 (ja) |
JP (1) | JP5197512B2 (ja) |
KR (1) | KR20110002778A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9349446B2 (en) | 2014-09-04 | 2016-05-24 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of controlling the same |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011192333A (ja) * | 2010-03-12 | 2011-09-29 | Elpida Memory Inc | 半導体装置 |
DE102011085555A1 (de) * | 2011-11-02 | 2013-05-02 | Robert Bosch Gmbh | Variable Widerstandsanordnung, Messbrückenschaltung und Verfahren zum Kalibrieren einer Messbrückenschaltung |
US9466362B2 (en) * | 2014-08-12 | 2016-10-11 | Arizona Board Of Regents On Behalf Of Arizona State University | Resistive cross-point architecture for robust data representation with arbitrary precision |
KR20160137148A (ko) | 2015-05-22 | 2016-11-30 | 에스케이하이닉스 주식회사 | 전자 장치 |
WO2019116932A1 (ja) * | 2017-12-11 | 2019-06-20 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
US10896726B2 (en) * | 2019-04-02 | 2021-01-19 | Junsung KIM | Method for reading a cross-point type memory array comprising a two-terminal switching material |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3532742B2 (ja) | 1997-08-29 | 2004-05-31 | 株式会社東芝 | X線リソグラフィ装置およびx線露光方法 |
US6504753B1 (en) | 2001-03-21 | 2003-01-07 | Matrix Semiconductor, Inc. | Method and apparatus for discharging memory array lines |
KR100744114B1 (ko) * | 2005-05-12 | 2007-08-01 | 삼성전자주식회사 | 상 변화 메모리 장치 및 그 워드라인 구동방법 |
JP4231502B2 (ja) * | 2005-11-02 | 2009-03-04 | シャープ株式会社 | クロスポイント構造の半導体記憶装置 |
JP4203506B2 (ja) * | 2006-01-13 | 2009-01-07 | シャープ株式会社 | 不揮発性半導体記憶装置及びその書き換え方法 |
JP5100292B2 (ja) * | 2007-10-05 | 2012-12-19 | 株式会社東芝 | 抵抗変化メモリ装置 |
US7813157B2 (en) | 2007-10-29 | 2010-10-12 | Contour Semiconductor, Inc. | Non-linear conductor memory |
-
2009
- 2009-07-02 JP JP2009157504A patent/JP5197512B2/ja not_active Expired - Fee Related
-
2010
- 2010-01-28 US US12/695,512 patent/US8320156B2/en active Active
- 2010-03-09 KR KR1020100020721A patent/KR20110002778A/ko not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9349446B2 (en) | 2014-09-04 | 2016-05-24 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of controlling the same |
Also Published As
Publication number | Publication date |
---|---|
KR20110002778A (ko) | 2011-01-10 |
JP2011014194A (ja) | 2011-01-20 |
US8320156B2 (en) | 2012-11-27 |
US20110002156A1 (en) | 2011-01-06 |
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