JP5180137B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5180137B2
JP5180137B2 JP2009095790A JP2009095790A JP5180137B2 JP 5180137 B2 JP5180137 B2 JP 5180137B2 JP 2009095790 A JP2009095790 A JP 2009095790A JP 2009095790 A JP2009095790 A JP 2009095790A JP 5180137 B2 JP5180137 B2 JP 5180137B2
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JP
Japan
Prior art keywords
sealing resin
chip mounting
semiconductor device
wiring board
chip
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
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JP2009095790A
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English (en)
Japanese (ja)
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JP2010251346A5 (https=
JP2010251346A (ja
Inventor
淳 大井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009095790A priority Critical patent/JP5180137B2/ja
Publication of JP2010251346A publication Critical patent/JP2010251346A/ja
Publication of JP2010251346A5 publication Critical patent/JP2010251346A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
JP2009095790A 2009-04-10 2009-04-10 半導体装置の製造方法 Active JP5180137B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009095790A JP5180137B2 (ja) 2009-04-10 2009-04-10 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009095790A JP5180137B2 (ja) 2009-04-10 2009-04-10 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010251346A JP2010251346A (ja) 2010-11-04
JP2010251346A5 JP2010251346A5 (https=) 2012-04-05
JP5180137B2 true JP5180137B2 (ja) 2013-04-10

Family

ID=43313408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009095790A Active JP5180137B2 (ja) 2009-04-10 2009-04-10 半導体装置の製造方法

Country Status (1)

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JP (1) JP5180137B2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8993358B2 (en) * 2011-12-28 2015-03-31 Ledengin, Inc. Deposition of phosphor on die top by stencil printing
JP2014042748A (ja) * 2012-08-28 2014-03-13 Glory Ltd 各台装置、遊技システム及び遊技媒体管理方法
JP6196893B2 (ja) * 2012-12-18 2017-09-13 新光電気工業株式会社 半導体装置の製造方法
JP6232633B1 (ja) * 2017-03-03 2017-11-22 山栄化学株式会社 部品の実装方法
JP6351004B1 (ja) * 2017-09-29 2018-07-04 山栄化学株式会社 活性樹脂組成物及びクリーム半田、並びにプリント配線板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022040A (ja) * 1998-07-07 2000-01-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3350454B2 (ja) * 1998-09-24 2002-11-25 三菱電機株式会社 半導体集積回路装置およびその製造方法並びに製造装置
JP4973837B2 (ja) * 2006-03-13 2012-07-11 セイコーエプソン株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2010251346A (ja) 2010-11-04

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