JP5174518B2 - 積層型半導体装置、及びその製造方法 - Google Patents
積層型半導体装置、及びその製造方法 Download PDFInfo
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- JP5174518B2 JP5174518B2 JP2008107790A JP2008107790A JP5174518B2 JP 5174518 B2 JP5174518 B2 JP 5174518B2 JP 2008107790 A JP2008107790 A JP 2008107790A JP 2008107790 A JP2008107790 A JP 2008107790A JP 5174518 B2 JP5174518 B2 JP 5174518B2
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- wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
Description
パッド 6
絶縁膜 8
半導体チップ 9
半導体装置 10
切断線 11、25
配線 12
ブレード 14、22
金属膜 16
側壁配線 18
配線連結部 20、20a
積層型半導体装置 100、110、120、130
Claims (9)
- 複数の半導体チップの各々の上に、複数の配線を設ける工程と、
前記複数の半導体チップのうち、隣接する半導体チップの間に配置された絶縁体の上に、前記複数の配線と電気的に接続されるように、前記配線の幅よりも大きな幅を有する配線連結部を設ける工程と、
前記複数の半導体チップの各々の側面に前記配線連結部の側面が露出するように前記複数の半導体チップを個片化し、半導体装置を形成する工程と、
複数の前記半導体装置を積層する工程と、
前記配線連結部同士が接続されるように、前記積層された複数の半導体装置の側面に延在する側壁配線を設ける工程と、
を含み、
前記側壁配線を設ける工程は、
前記積層された複数の半導体装置の各々の側面に露出した前記配線連結部の各々と接続されるように、前記積層された複数の半導体装置の側面に金属膜を設ける工程と、
前記積層された複数の半導体装置の各々に設けられた前記複数の配線のうち、隣接する配線の間に切断線が位置するように、前記金属膜を積層方向に切断する第1切断工程と、を含む、
ことを特徴とする積層型半導体装置の製造方法。 - 前記配線連結部を設ける工程は、前記配線の前記配線連結部と接触する領域の幅よりも大きな幅を有する前記配線連結部を設ける工程であることを特徴とする請求項1記載の積層型半導体装置の製造方法。
- 前記配線連結部を設ける工程は、前記複数の半導体チップの各々に設けられた全ての前記複数の配線が互いに接続されるように、帯状の前記配線連結部を設ける工程であることを特徴とする請求項1又は2記載の積層型半導体装置の製造方法。
- 前記配線連結部を設ける工程は、前記隣接する半導体チップに設けられた互いに対向する配線が接続された、互いに隣接する配線連結部が離間するように、前記配線連結部を設ける工程であることを特徴とする請求項1又は2記載の積層型半導体装置の製造方法。
- 前記第1切断工程は前記金属膜と前記配線連結部とを切断する工程であることを特徴とする請求項1から4いずれか一項記載の積層型半導体装置の製造方法。
- 前記複数の半導体装置を積層する工程の後であって、前記金属膜を設ける工程の前に、前記第1切断工程の切断線と重なる切断線で前記配線連結部を積層方向に切断する、第2切断工程を有することを特徴とする請求項1から4いずれか一項記載の積層型半導体装置の製造方法。
- 前記複数の配線を設ける工程は、前記複数の配線の一部をテスト用パッドと接続する工程を含むことを特徴とする請求項1から6いずれか一項記載の積層型半導体装置の製造方法。
- 前記側壁配線を設ける工程の後に、半田を用いて前記側壁配線と基板とを接続することにより、前記積層された複数の半導体装置を前記基板上に実装する工程を有することを特徴とする請求項1から7いずれか一項記載の積層型半導体装置の製造方法。
- 各々が複数の配線を有し、かつ積層された複数の半導体装置と、
前記複数の配線の各々と接続され、前記配線の幅よりも大きな幅を有し、前記積層された複数の半導体装置の各々の側面に設けられた複数の配線連結部と、
前記配線連結部同士が接続されるように、前記積層された複数の半導体装置の側面に延在する側壁配線と、
を具備し、
前記側壁配線は、前記積層された複数の半導体装置の各々の側面に露出した前記配線連結部の各々と接続されるように、前記積層された複数の半導体装置の側面にある金属膜を備え、該金属膜は、前記積層された複数の半導体装置の各々に設けられた前記複数の配線のうち、隣接する配線の間に切断線が位置するように、積層方向に切断される、
ことを特徴とする積層型半導体装置。
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JP5174518B2 true JP5174518B2 (ja) | 2013-04-03 |
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TW201214656A (en) * | 2010-09-27 | 2012-04-01 | Universal Scient Ind Shanghai | Chip stacked structure and method of fabricating the same |
US9190390B2 (en) * | 2012-08-22 | 2015-11-17 | Freescale Semiconductor Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
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JP3509239B2 (ja) * | 1994-11-04 | 2004-03-22 | イビデン株式会社 | リードレスチップキャリア及びその製造方法 |
JP2944449B2 (ja) * | 1995-02-24 | 1999-09-06 | 日本電気株式会社 | 半導体パッケージとその製造方法 |
JP2004221372A (ja) * | 2003-01-16 | 2004-08-05 | Seiko Epson Corp | 半導体装置、半導体モジュール、電子機器、半導体装置の製造方法および半導体モジュールの製造方法 |
JP4934053B2 (ja) * | 2005-12-09 | 2012-05-16 | スパンション エルエルシー | 半導体装置およびその製造方法 |
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