JP5172275B2 - Component built-in printed wiring board and method for manufacturing component built-in printed wiring board - Google Patents

Component built-in printed wiring board and method for manufacturing component built-in printed wiring board Download PDF

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Publication number
JP5172275B2
JP5172275B2 JP2007278557A JP2007278557A JP5172275B2 JP 5172275 B2 JP5172275 B2 JP 5172275B2 JP 2007278557 A JP2007278557 A JP 2007278557A JP 2007278557 A JP2007278557 A JP 2007278557A JP 5172275 B2 JP5172275 B2 JP 5172275B2
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core layer
layer
wiring
component
solder
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JP2009110992A (en
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義之 和田
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2007278557A priority Critical patent/JP5172275B2/en
Priority to PCT/JP2008/002892 priority patent/WO2009054105A1/en
Priority to TW097140626A priority patent/TW200920197A/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、複数の配線層を積層して構成されコア層に電子部品が実装された部品内蔵プリント配線基板および部品内蔵プリント配線基板の製造方法に関するものである。   The present invention relates to a component built-in printed wiring board configured by laminating a plurality of wiring layers and having electronic components mounted on a core layer, and a method of manufacturing the component built-in printed wiring board.

近年電子機器の高機能化・小型化の進展に伴い、電子部品が実装された実装基板において実装密度の更なる高度化が求められる傾向にある。このため、電子部品の実装に用いられるプリント配線基板として、複数積層された配線層の内層に電子部品を実装したいわゆる部品内蔵型のものが用いられるようになっている（例えば特許文献１参照）。この特許文献例においては、プリント配線基板に複数層設けられた配線層のうち、内層にチップコンデンサ等のチップ部品を実装する例が示されている。これにより、プリント配線基板の外層に実装される電子部品の一部を内層に取り込むことができ、高密度の実装が実現されるという利点がある。
特開２００７−２１４２３０号公報 In recent years, with the advancement of high functionality and miniaturization of electronic devices, there is a tendency for further enhancement of mounting density in a mounting substrate on which electronic components are mounted. For this reason, as a printed wiring board used for mounting an electronic component, a so-called component built-in type in which an electronic component is mounted on an inner layer of a plurality of stacked wiring layers is used (for example, see Patent Document 1). . In this patent document example, an example in which a chip component such as a chip capacitor is mounted on an inner layer among wiring layers provided on a printed wiring board in a plurality of layers is shown. Thereby, a part of electronic components mounted on the outer layer of the printed wiring board can be taken into the inner layer, and there is an advantage that high-density mounting is realized.
JP 2007-214230 A

しかしながら上述の特許文献例を含め、実装密度の高密度化を促進する目的で採用されるプリント配線基板の内層への部品内蔵においては、従来より次のような問題点がある。まず従来は、内蔵の対象となる部品の種類は主にコンデンサや抵抗などの受動部品に限定される場合が多く、半導体部品などを含めた基板全体の実装密度の高度化には限界があった。また半導体部品を内層へ実装しようとすれば、基板製造工程においてこれら部品を収容するためのキャビティの加工や部品を封止するための工程など、複雑な工程を経る必要があった。このように、従来技術においては、簡便な工程で効率よく部品内蔵プリント配線基板を製造するための技術が確立されておらず、新しい構成の部品内蔵プリント配線基板およびその製造方法が望まれていた。   However, including the above-mentioned patent literature examples, the following problems have been encountered in the past in the incorporation of components in the inner layer of a printed wiring board that is employed for the purpose of accelerating the mounting density. First, in the past, the types of components that were built-in were mostly limited to passive components such as capacitors and resistors, and there was a limit to increasing the mounting density of the entire board including semiconductor components. . In addition, if semiconductor components are to be mounted on the inner layer, it has been necessary to go through complicated steps such as processing a cavity for housing these components and sealing a component in the substrate manufacturing process. Thus, in the prior art, a technique for efficiently producing a component-embedded printed wiring board in a simple process has not been established, and a component-embedded printed wiring board having a new configuration and a method for producing the same have been desired. .

そこで本発明は、簡便な工程で効率よく製造可能な部品内蔵プリント配線基板および部品内蔵プリント配線基板の製造方法を提供することを目的とする。   Then, an object of this invention is to provide the manufacturing method of the component built-in printed wiring board which can be efficiently manufactured in a simple process, and a component built-in printed wiring board.

請求項１記載の本発明の部品内蔵プリント配線基板は、コア層を含む複数の配線層を積層して構成され前記コア層に電子部品が実装された部品内蔵プリント配線基板であって、前記電子部品は前記コア層の少なくとも一方の面に形成された配線回路を構成する接続用の電極に半田接合されており、前記コア層を除く前記配線層はプリプレグが固化した絶縁層に配線回路を形成して構成されており、前記コア層において前記電子部品と前記電極との半田接合部を樹脂によって覆って形成された樹脂コート部と、前記コア層の前記一方の面に積層されたプリプレグを固化させることにより形成され前記電子部品および前記樹脂コート部を周囲から固定する部品固定層と、前記複数の配線層の１つであって前記部品固定層の表面に形成された表面層と、前記コア層の配線回路と前記表面層を含む他の配線層の配線回路とを接続する層間配線部とを備え、前記電子部品と前記接続用の電極は半田の酸化膜を除去する活性作用を有する熱硬化性樹脂に半田粒子を５０ｗｔ％〜８８ｗｔ％の含有率で含有させた半田接合材によって半田接合されており、前記樹脂コート部は前記熱硬化性樹脂が硬化した樹脂によって形成されている。
また請求項２記載の本発明の部品内蔵プリント配線基板の製造方法は、コア層を含む複数の配線層を積層して構成され前記コア層に電子部品が実装された部品内蔵プリント配線基板を製造する部品内蔵プリント配線基板の製造方法であって、前記コア層の少なくとも一方の面に形成された配線回路を構成する接続用の電極に、半田の酸化膜を除去する活性作用を有する熱硬化性樹脂に半田粒子を５０ｗｔ％〜８８ｗｔ％の含有率で含有させた半田接合材を供給する半田供給工程と、前記半田供給工程後のコア層に前記電子部品を搭載する部品搭載工程と、前記部品搭載工程後のコア層を加熱することにより前記電極と前記電子部品とを半田接合するとともに、前記電極と前記電子部品との半田接合部を前記熱硬化性樹脂が硬化した樹脂で覆って樹脂コート部を形成する半田接合工程と、前記半田接合工程後のコア層を黒化処理することにより、前記配線回路の表面を粗化する黒化処理工程と、前記黒化処理工程後のコア層において、前記電子部品を周囲から囲んで固定する部品固定層を形成するためのプリプレグおよび前記部品固定層の表面に形成される表面層を少なくとも含む複数の配線層を前記コア層と貼り合わせて積層する積層工程と、前記積層工程において形成された積層体を加熱加圧することにより、前記電子部品を周囲から囲んで固定する部品固定層を形成するとともに、前記コア層と前記複数の配線層とを固着させるプレス工程と、前記コア層の配線回路と前記配線層とを接続する層間配線部を形成する層間配線工程と、前記配線層に配線回路を形成する回路形成工程とを含む。 The component-embedded printed wiring board according to claim 1 is a component-embedded printed wiring board in which a plurality of wiring layers including a core layer are stacked and an electronic component is mounted on the core layer. The component is soldered to a connection electrode constituting a wiring circuit formed on at least one surface of the core layer, and the wiring layer excluding the core layer forms a wiring circuit in an insulating layer in which a prepreg is solidified. A resin coat portion formed by covering the solder joint between the electronic component and the electrode with a resin in the core layer, and a prepreg laminated on the one surface of the core layer. A component fixing layer that is formed by fixing the electronic component and the resin coating portion from the periphery, and a surface layer that is one of the plurality of wiring layers and is formed on a surface of the component fixing layer An interlayer wiring portion for connecting the wiring circuit of the core layer and the wiring circuit of another wiring layer including the surface layer, and the electronic component and the connection electrode have an active action of removing a solder oxide film The thermosetting resin is soldered with a solder bonding material containing solder particles at a content of 50 wt% to 88 wt% , and the resin coat portion is formed of a resin obtained by curing the thermosetting resin. Yes.
According to a second aspect of the present invention, there is provided a method of manufacturing a component built-in printed wiring board according to the present invention, wherein a plurality of wiring layers including a core layer are stacked and an electronic component is mounted on the core layer. A method of manufacturing a component-embedded printed wiring board, the thermosetting having an active action of removing a solder oxide film on a connection electrode constituting a wiring circuit formed on at least one surface of the core layer A solder supplying step of supplying a solder bonding material in which solder particles are contained in a resin at a content of 50 wt% to 88 wt%, a component mounting step of mounting the electronic component on the core layer after the solder supplying step, and the component By heating the core layer after the mounting process, the electrode and the electronic component are soldered together, and the soldered joint between the electrode and the electronic component is covered with a resin cured by the thermosetting resin. A solder bonding step for forming a resin coat portion; a blackening treatment step for roughening a surface of the wiring circuit by blackening a core layer after the solder bonding step; and a core after the blackening treatment step. A plurality of wiring layers including at least a prepreg for forming a component fixing layer that surrounds and fixes the electronic component from the periphery and a surface layer formed on a surface of the component fixing layer; A stacking step for stacking, and heating and pressurizing the stack formed in the stacking step to form a component fixing layer that surrounds and fixes the electronic component from the periphery, and the core layer and the plurality of wiring layers A pressing step for fixing the wiring layer, an interlayer wiring step for forming an interlayer wiring portion for connecting the wiring circuit of the core layer and the wiring layer, and a circuit forming process for forming the wiring circuit in the wiring layer Including the door.

本発明の部品内蔵プリント配線基板の製造方法は、コア層を含む複数の配線層を積層して構成され前記コア層に電子部品が実装された部品内蔵プリント配線基板を製造する部品内蔵プリント配線基板の製造方法であって、前記コア層の少なくとも一方の面に形成された配線回路を構成する接続用の電極に、半田の酸化膜を除去する活性作用を有する熱硬化性樹脂に半田粒子を含有させた半田接合材を供給する半田供給工程と、前記半田供給工程後のコア層に前記電子部品を搭載する部品搭載工程と、前記部品搭載工程後のコア層を加熱することにより前記電極と前記電子部品とを半田接合するとともに、前記電極と前記電子部品との半田接合部を前記熱硬化性樹脂が硬化した樹脂で覆って樹脂コート部を形成する半田接合工程と、前記半田接合工程後のコア層を黒化処理することにより、前記配線回路の表面を粗化する黒化処理工程と、前記黒化処理工程後のコア層において、前記電子部品を周囲から囲んで固定する部品固定層を形成するためのプリプレグおよび前記部品固定層の表面に形成される表面層を少なくとも含む複数の配線層を前記コア層と貼り合わせて積層する積層工程と、前記積層工程において形成された積層体を加熱加圧することにより、前記電子部品を周囲から囲んで固定する部品固定層を形成するとともに、前記コア層と前記複数の配線層とを固着させるプレス工程と、前記コア層の配線回路と前記配線層とを接続する層間配線部を形成する層間配線工程と、前記配線層に配線回路を形成する回路形成工程とを含む。   The method for manufacturing a component built-in printed wiring board according to the present invention includes a component built-in printed wiring board that is formed by laminating a plurality of wiring layers including a core layer, and in which an electronic component is mounted on the core layer. A solder electrode in a thermosetting resin having an active action of removing an oxide film of solder on a connection electrode constituting a wiring circuit formed on at least one surface of the core layer A solder supplying step for supplying the solder bonding material, a component mounting step for mounting the electronic component on the core layer after the solder supplying step, and heating the core layer after the component mounting step, A solder joining step of soldering an electronic component and covering a solder joint portion between the electrode and the electronic component with a resin cured by the thermosetting resin to form a resin coat portion; A blackening treatment step for roughening the surface of the wiring circuit by blackening the core layer after the step, and a component that surrounds and fixes the electronic component from the periphery in the core layer after the blackening treatment step A lamination step of laminating a plurality of wiring layers including at least a prepreg for forming a fixing layer and a surface layer formed on a surface of the component fixing layer with the core layer; and a lamination formed in the lamination step Forming a component fixing layer that surrounds and fixes the electronic component from around by heating and pressurizing a body, and fixing the core layer and the plurality of wiring layers; a wiring circuit of the core layer; An interlayer wiring step for forming an interlayer wiring portion connecting the wiring layer; and a circuit forming step for forming a wiring circuit in the wiring layer.

本発明によれば、電子部品が実装されたコア層において電子部品と電極との半田接合部を樹脂によって覆って樹脂コート部を形成することにより、複数の配線層を積層する際のプリプレグの密着性を確保するために行われる黒化処理において半田接合部を保護することができ、コア層への部品実装とプリプレグを用いた配線層の積層という簡便な工程で効率よく部品内蔵プリント配線基板を製造することができる。   According to the present invention, in the core layer on which the electronic component is mounted, the solder joint portion between the electronic component and the electrode is covered with the resin to form the resin coat portion, thereby adhering the prepreg when stacking the plurality of wiring layers. The solder joints can be protected during the blackening process performed to ensure safety, and the printed wiring board with built-in components can be efficiently manufactured by a simple process of mounting the component on the core layer and laminating the wiring layer using the prepreg. Can be manufactured.

（実施の形態１）
図１、図２は本発明の実施の形態１の部品内蔵プリント配線基板の製造方法を示す工程説明図である。
まず部品内蔵プリント配線基板の製造方法について説明する。図１，図２はコア層を含む複数の配線層を積層して構成されコア層に電子部品が実装された部品内蔵プリント配線基板を製造する方法を工程順に示すものである。図１（ａ）において、コア層１は絶縁性の樹脂基板２の上面２ａ、下面２ｂにそれぞれ配線回路３および配線回路５を形成した構成となっている。配線回路３の内側の端部は電子部品の端子を接続するための電極３ａとなっている。すなわち電極３ａは、コア層１の少なくとも一方の面（上面２ａ）に形成された配線回路３を構成する形態となっている。電極３ａには、電子部品の端子との半田接合部の形成範囲を囲む配置・形状で予めソルダレジスト４が形成されている。 (Embodiment 1)
1 and 2 are process explanatory views showing a method of manufacturing a component built-in printed wiring board according to the first embodiment of the present invention.
First, a method for manufacturing a component built-in printed wiring board will be described. 1 and 2 show a method of manufacturing a component built-in printed wiring board in which a plurality of wiring layers including a core layer are stacked and an electronic component is mounted on the core layer in order of steps. In FIG. 1A, the core layer 1 has a configuration in which a wiring circuit 3 and a wiring circuit 5 are formed on an upper surface 2a and a lower surface 2b of an insulating resin substrate 2, respectively. The inner end of the wiring circuit 3 serves as an electrode 3a for connecting a terminal of an electronic component. That is, the electrode 3 a is configured to constitute the wiring circuit 3 formed on at least one surface (upper surface 2 a) of the core layer 1. The solder resist 4 is formed in advance on the electrode 3a in an arrangement / shape surrounding the formation range of the solder joint with the terminal of the electronic component.

次いで、図１（ｂ）に示すように、コア層１の少なくとも一方の面（上面２ａ）に形成された配線回路３を構成する接続用の電極３ａ上に、クリーム半田６がスクリーン印刷やディスペンサによる塗布などの方法によって供給される（半田供給工程）。ここでは、電極３ａにおいてソルダレジスト４が形成されていない露呈範囲にクリーム半田６が供給される。クリーム半田６は、半田粒子６ａを粘性体であるフラックス６ｂ中に含有させた構成となっており、フラックス６ｂ中の活性剤成分によって半田粒子６ａの表面や、電極３ａ、端子７ａの表面の酸化膜が除去される。   Next, as shown in FIG. 1B, cream solder 6 is applied to the connection electrodes 3a constituting the wiring circuit 3 formed on at least one surface (upper surface 2a) of the core layer 1 by screen printing or dispenser. It is supplied by a method such as coating by (solder supply step). Here, the cream solder 6 is supplied to the exposed range where the solder resist 4 is not formed on the electrode 3a. The cream solder 6 has a configuration in which solder particles 6a are contained in a flux 6b which is a viscous body, and the surface of the solder particles 6a, the surfaces of the electrodes 3a and the terminals 7a are oxidized by the activator component in the flux 6b. The film is removed.

この後、図１（ｃ）に示すように、クリーム半田６が電極３ａに供給された半田供給工程後のコア層１に対して、両端部に端子７ａを有するチップ型の電子部品７が搭載される（部品搭載工程）。次いで、電子部品７が搭載されたコア層１はリフロー装置に送られ、図１（ｄ）に示すように、部品搭載工程後のコア層を加熱することにより、電極３ａと電子部品７の端子７ａとを半田接合する（半田接合工程）。この半田接合工程においては、クリーム半田６中の半田粒子６ａが溶融固化することにより、電極３ａと端子７ａとを接合して電気的に導通させる半田接合部６ａ＊が形成される。このとき、溶融状態の半田が過度に濡れ拡がることによる流動が、電極３ａに形成されたソルダレジスト４によって規制され、適正な形状の半田接合部６ａ＊が形成される。なお、ソルダレジスト４は必ずしも必須ではなく、半田の流動に起因する不具合のおそれがない場合には、ソルダレジスト４を形成しなくてもよい。このことは、実施の形態２においても同様である。   Thereafter, as shown in FIG. 1C, chip-type electronic components 7 having terminals 7a at both ends are mounted on the core layer 1 after the solder supplying process in which the cream solder 6 is supplied to the electrodes 3a. (Component mounting process). Next, the core layer 1 on which the electronic component 7 is mounted is sent to a reflow apparatus, and the core layer after the component mounting step is heated as shown in FIG. 7a is soldered (solder joining step). In this solder bonding step, the solder particles 6a in the cream solder 6 are melted and solidified, thereby forming a solder bonding portion 6a * for bonding the electrode 3a and the terminal 7a and making them electrically conductive. At this time, the flow caused by excessively wet spreading of the molten solder is restricted by the solder resist 4 formed on the electrode 3a, and the solder joint portion 6a * having an appropriate shape is formed. Note that the solder resist 4 is not always essential, and the solder resist 4 does not have to be formed if there is no risk of trouble due to solder flow. The same applies to the second embodiment.

この後、半田接合工程後のコア層１は洗浄装置に送られる。すなわち図１（ｅ）に示すように、コア層１を洗浄槽の洗浄剤８内に浸漬した状態で超音波振動を作用させることにより、電極３ａと電子部品７との半田接合部６ａ＊を洗浄して半田接合部６ａ＊の周囲に残留したフラックス成分などの半田接合残渣を除去する（洗浄工程）。   Thereafter, the core layer 1 after the solder bonding step is sent to a cleaning device. That is, as shown in FIG. 1E, by applying ultrasonic vibration in a state where the core layer 1 is immersed in the cleaning agent 8 of the cleaning tank, the solder joint portion 6a * between the electrode 3a and the electronic component 7 is formed. Washing and removing solder joint residues such as flux components remaining around the solder joint portion 6a * (cleaning step).

これにより、後工程において部品内蔵プリント配線基板にさらに電子部品を実装する際に実行されるリフローでの加熱によって半田接合部６ａ＊が再溶融した場合にあっても、半田接合残渣が除去されていることから、フラックス成分が残留することによる不具合を防止することができる。すなわち、残留したフラックス成分によって溶融半田が流動して、半田接合部６ａ＊の形状が崩れることによる不具合を防止することができる。なお洗浄方法としては、洗浄剤８内にコア層１を浸漬する洗浄方法以外にも、洗浄剤を洗浄対象部位に噴射するシャワー洗浄など、各種の方法を用いることができる。   As a result, the solder joint residue is removed even when the solder joint 6a * is remelted by reflow heating performed when electronic components are further mounted on the component-embedded printed wiring board in a later process. Therefore, it is possible to prevent problems caused by the flux component remaining. That is, it is possible to prevent problems caused by the molten solder flowing due to the remaining flux component and the shape of the solder joint 6a * being broken. In addition to the cleaning method in which the core layer 1 is immersed in the cleaning agent 8, various methods such as shower cleaning in which the cleaning agent is sprayed onto the site to be cleaned can be used as the cleaning method.

次いで洗浄工程後のコア層１に対して樹脂塗布が行われる。すなわち図２（ａ）に示すように、コア層１において電子部品７の周囲にディスペンサなどによってエポキシ樹脂などの樹脂を塗布することにより、電子部品７の下面側の隙間を充填するとともに、半田接合部６ａ＊を樹脂で覆って樹脂コート部９を形成する（樹脂コート工程）。   Next, resin coating is performed on the core layer 1 after the cleaning process. That is, as shown in FIG. 2A, by applying a resin such as epoxy resin around the electronic component 7 in the core layer 1 with a dispenser or the like, the gap on the lower surface side of the electronic component 7 is filled and soldered. The resin coat part 9 is formed by covering the part 6a * with resin (resin coating process).

この後、樹脂コート工程後のコア層１を黒化処理することにより、配線回路の表面を粗化する（黒化処理工程）。すなわち、図２（ｂ）に示すように、コア層１を強酸溶液などの処理液に浸漬することにより、配線回路３の表面３ｂや配線回路５の表面５ａが酸化により粗化されて、これらの表面には微細な凹凸よりなるアンカーパターンが形成される。このとき、半田接合部６ａ＊は樹脂コート部９によって覆われて保護されていることから、黒化処理の作用が半田接合部６ａ＊に及ぶことはなく、半田接合部６ａ＊は健全な状態に保たれる。   Thereafter, the surface of the wiring circuit is roughened by blackening the core layer 1 after the resin coating step (blackening treatment step). That is, as shown in FIG. 2B, by immersing the core layer 1 in a treatment solution such as a strong acid solution, the surface 3b of the wiring circuit 3 and the surface 5a of the wiring circuit 5 are roughened by oxidation. An anchor pattern made of fine irregularities is formed on the surface of the substrate. At this time, since the solder joint portion 6a * is covered and protected by the resin coat portion 9, the effect of the blackening treatment does not reach the solder joint portion 6a *, and the solder joint portion 6a * is in a healthy state. To be kept.

この後、コア層１には電子部品７を固定するための部品固定層および複数の配線層が積層される。すなわち、図２（ｃ）に示すように、電子部品７の位置に対応して開口部１１ａが設けられたプリプレグ１１およびプリプレグ１３の上面側に銅箔１４を貼着した構成
の配線層１２を、コア層１の上面側（電子部品７側）に順次重ね合わせるとともに、プリプレグ１６の下面側に銅箔１７を貼着した構成の配線層１５をコア層１の下面側に重ね合わせる。すなわちこの工程においては、黒化処理工程後のコア層１において、電子部品７を周囲から囲んで固定する部品固定層を形成するためのプリプレグ１１および部品固定層の表面に形成される表面層１２を少なくとも含む複数の配線層１２，１５をコア層１と貼り合わせて積層し、積層体１８を形成する（積層工程）。 Thereafter, a component fixing layer and a plurality of wiring layers for fixing the electronic component 7 are laminated on the core layer 1. That is, as shown in FIG. 2C, the wiring layer 12 having a configuration in which the copper foil 14 is attached to the upper surface side of the prepreg 11 and the prepreg 13 provided with the opening 11 a corresponding to the position of the electronic component 7. The wiring layer 15 having a configuration in which the copper foil 17 is adhered to the lower surface side of the prepreg 16 is superimposed on the lower surface side of the core layer 1 while being sequentially superimposed on the upper surface side (electronic component 7 side) of the core layer 1. That is, in this step, in the core layer 1 after the blackening treatment step, a prepreg 11 for forming a component fixing layer that surrounds and fixes the electronic component 7 from the periphery and a surface layer 12 formed on the surface of the component fixing layer. A plurality of wiring layers 12 and 15 including at least one are bonded and laminated to the core layer 1 to form a laminated body 18 (lamination process).

次いで、図２（ｄ）に示すように、配線層１５、コア層１、プリプレグ１１および配線層１２より成る積層体１８をプレス装置によって３０ｋｇ／ｃｍ２程度の圧力で加圧しながら、１５０℃〜２００℃程度の温度で加熱する。これにより、プリプレグ１３、１１、１６の各層に含浸された樹脂が軟化して相接する界面が相互に融着するとともに、表面３ｂおよび表面５ａの表面にプリプレグ１１、プリプレグ１６がそれぞれ密着する。このとき、黒化処理工程において表面３ｂおよび表面５ａの表面には微細なアンカーパターンが形成されていることから、良好な密着性が確保される。   Next, as shown in FIG. 2 (d), the laminated body 18 composed of the wiring layer 15, the core layer 1, the prepreg 11 and the wiring layer 12 is pressed at a pressure of about 30 kg / cm 2 by a press device at 150 ° C. to 200 ° C. Heat at a temperature of about ℃. As a result, the resin impregnated in each layer of the prepregs 13, 11, 16 is softened and the contacting interfaces are fused together, and the prepreg 11 and the prepreg 16 are in close contact with the surfaces 3 b and 5 a, respectively. At this time, since a fine anchor pattern is formed on the surface 3b and the surface 5a in the blackening process, good adhesion is ensured.

さらにプリプレグ１３、１１中に含浸された樹脂が、加圧・加熱により開口部１１ａ内において電子部品７との隙間部分を充填し、電子部品７や樹脂コート部９を周囲から固定する部品固定層１１＊を形成する。すなわちここでは、積層工程において形成された積層体１８を加熱・加圧することにより、電子部品７を周囲から囲んで固定する部品固定層１１＊を形成するとともに、コア層１と複数の配線層１２，１５とを固着させる（プレス工程）。この加熱・加圧により、プリプレグ１３、１６は融着状態で熱硬化して、配線層１２，１５における絶縁層を形成する。   Furthermore, the resin impregnated in the prepregs 13 and 11 fills the gaps with the electronic component 7 in the opening 11a by pressing and heating, and fixes the electronic component 7 and the resin coating portion 9 from the periphery. 11 * is formed. That is, here, the laminated body 18 formed in the laminating process is heated and pressurized to form the component fixing layer 11 * that surrounds and fixes the electronic component 7 from the periphery, and the core layer 1 and the plurality of wiring layers 12 are formed. , 15 are fixed (pressing process). By this heating and pressurization, the prepregs 13 and 16 are thermally cured in a fused state to form insulating layers in the wiring layers 12 and 15.

次いで図２（ｅ）に示すように、積層体１８を貫通するスルーホールの内面にメッキ層を形成することにより、コア層１の配線回路３と配線層１２，１５の銅箔１４、１７とを接続する層間配線部１９を形成し（層間配線工程）、さらに配線層１２，１５の銅箔１４、銅箔１７にパターニングを施すことにより、配線回路１４ａ、１７ａを形成する（回路形成工程）。   Next, as shown in FIG. 2 (e), by forming a plating layer on the inner surface of the through hole that penetrates the laminated body 18, the wiring circuit 3 of the core layer 1 and the copper foils 14, 17 of the wiring layers 12, 15 are formed. Is formed (interlayer wiring process), and the copper foils 14 and 17 of the wiring layers 12 and 15 are patterned to form wiring circuits 14a and 17a (circuit forming process). .

これにより、図２（ｅ）に示すように、コア層１を含む複数の配線層（コア層１，配線層１２，１５）を積層して構成され、コア層１に電子部品７が実装された部品内蔵プリント配線基板２０が完成する。この部品内蔵プリント配線基板２０においては、電子部品７はコア層１の少なくとも一方の面に形成された配線回路３を構成する接続用の電極３ａに半田接合されており、また配線層１２，１５はプリプレグ１３，１６が固化した絶縁層に配線回路１４ａ、１７ａを形成して構成された形態となっている。   As a result, as shown in FIG. 2 (e), a plurality of wiring layers (core layer 1, wiring layers 12, 15) including the core layer 1 are stacked, and the electronic component 7 is mounted on the core layer 1. The component built-in printed wiring board 20 is completed. In this component built-in printed wiring board 20, the electronic component 7 is soldered to the connection electrode 3 a constituting the wiring circuit 3 formed on at least one surface of the core layer 1, and the wiring layers 12, 15 are connected. Has a configuration in which wiring circuits 14a and 17a are formed on an insulating layer in which the prepregs 13 and 16 are solidified.

さらに部品内蔵プリント配線基板２０は、コア層１において電子部品７の端子７ａと電極３ａとの半田接合部６ａ＊を樹脂によって覆って形成された樹脂コート部９と、コア層１の上面２ａ（一方の面）に積層されたプリプレグ１１を固化させることにより形成され、電子部品７および樹脂コート部９を周囲から固定する部品固定層１１＊と、複数の配線層の１つであって部品固定層１１＊の表面に形成された表面層としての配線層１２と、コア層１の配線回路３と表面層を含む他の配線層１２，１５の配線回路１４ａ、１７ａとを接続する層間配線部１９とを備えた構成となっている。   Furthermore, the component built-in printed wiring board 20 includes a resin coat portion 9 formed by covering the solder joint portion 6a * between the terminal 7a and the electrode 3a of the electronic component 7 in the core layer 1 with a resin, and an upper surface 2a ( The prepreg 11 laminated on one surface) is solidified, and a component fixing layer 11 * for fixing the electronic component 7 and the resin coating portion 9 from the periphery, and one of a plurality of wiring layers and fixing the component Interlayer wiring section connecting wiring layer 12 as a surface layer formed on the surface of layer 11 *, wiring circuit 3 of core layer 1 and wiring circuits 14a and 17a of other wiring layers 12 and 15 including the surface layer 19.

このようにして製造された部品内蔵プリント配線基板２０はさらに部品実装の対象となり、表面層の配線層１２、さらに必要に応じて下面層の配線層１５に電子部品が実装され実装基板が完成する。実装基板の製造過程において本実施の形態に示すように多層配線基板のコア層に電子部品を実装することにより、実装密度を高度化して基板面積を減少させ、基板の製造コストを大幅に低減することが可能となっている。   The component built-in printed wiring board 20 manufactured in this way is further subjected to component mounting, and electronic components are mounted on the wiring layer 12 on the surface layer and, if necessary, the wiring layer 15 on the lower surface layer, thereby completing the mounting substrate. . By mounting electronic components on the core layer of the multilayer wiring board as shown in this embodiment in the manufacturing process of the mounting board, the mounting density is increased, the board area is reduced, and the board manufacturing cost is greatly reduced. It is possible.

（実施の形態２）
図３は本発明の実施の形態２の部品内蔵プリント配線基板の製造方法を示す工程説明図である。本実施の形態２は、実施の形態１において半田接合材料として用いられたクリーム半田６を、半田の酸化膜を除去する活性作用を有する熱硬化性樹脂に半田粒子を含有させた半田接合材６Ａに置き換えた形態となっている。 (Embodiment 2)
FIG. 3 is a process explanatory view showing the method of manufacturing the component built-in printed wiring board according to the second embodiment of the present invention. In this second embodiment, the cream solder 6 used as the solder bonding material in the first embodiment is a solder bonding material 6A in which solder particles are contained in a thermosetting resin having an active action of removing the oxide film of the solder. It has become a form replaced.

図３（ａ）において、コア層１は図１（ａ）に示すコア層１と同様であり、図３（ｂ）に示すように、コア層１の上面２ａに形成された接続用の電極３ａに、半田接合材６Ａを供給する（半田供給工程）。電極３ａは、実施の形態１と同様に配線回路３の一部を構成する。半田接合材６Ａは、半田の酸化膜を除去する活性作用を有する熱硬化性樹脂６ｃに半田粒子６ａを含有させた組成となっており、エポキシ樹脂などの熱硬化性樹脂に有機酸などの活性剤を配合することにより活性作用を付与している。ここでは、半田接合材６Ａとして、半田粒子６ａの含有率が５０ｗｔ％〜８８ｗｔ％程度の低半田含有タイプのものを使用するようにしている。   3A, the core layer 1 is the same as the core layer 1 shown in FIG. 1A, and as shown in FIG. 3B, the connection electrode formed on the upper surface 2a of the core layer 1 is used. The solder bonding material 6A is supplied to 3a (solder supply process). The electrode 3a constitutes a part of the wiring circuit 3 as in the first embodiment. The solder bonding material 6A has a composition in which solder particles 6a are contained in a thermosetting resin 6c having an active action of removing an oxide film of solder, and an activity such as an organic acid is added to a thermosetting resin such as an epoxy resin. The active action is given by mix | blending an agent. Here, as the solder bonding material 6A, a low solder content type in which the content of the solder particles 6a is about 50 wt% to 88 wt% is used.

次いで図３（ｃ）に示すように、半田供給工程後のコア層１には電子部品７が搭載される（部品搭載工程）。この後、コア層１はリフロー装置に送られ、図３（ｄ）に示すように、部品搭載後のコア層１を加熱することにより、電極３ａと電子部品７の端子７ａとを半田接合するとともに、電極３ａと端子７ａとの半田接合部６ａ＊を熱硬化性樹脂６ｃが硬化した樹脂で覆って樹脂コート部６ｃ＊を形成する（半田接合工程）。このとき樹脂コート部６ｃ＊は電子部品７の下面側の隙間内にも侵入して隙間を封止する。   Next, as shown in FIG. 3C, the electronic component 7 is mounted on the core layer 1 after the solder supplying process (component mounting process). Thereafter, the core layer 1 is sent to a reflow apparatus, and as shown in FIG. 3 (d), the core layer 1 after component mounting is heated to solder the electrode 3a and the terminal 7a of the electronic component 7 together. At the same time, the solder joint portion 6a * between the electrode 3a and the terminal 7a is covered with a resin obtained by curing the thermosetting resin 6c to form a resin coat portion 6c * (solder joining step). At this time, the resin coat portion 6c * also enters the gap on the lower surface side of the electronic component 7 to seal the gap.

この半田接合工程においては、半田接合材６Ａとして低半田含有タイプのものを用いていることから、電極３ａと端子７ａとを接合する半田接合部６ａ＊は固化した半田の体積が小さく、樹脂コート部６ｃ＊によって完全に覆われ易い形態となっている。このように半田接合部の半田体積が小さいことは通常の半田接合による電子部品７の実装の場合には電子部品を固着する実装強度の面で望ましくないが、本実施の形態のように電子部品を多層基板中に内蔵する構成においては、電子部品７は樹脂コート部６ｃ＊によってコア層１に固着され、さらに内蔵状態において電子部品７は部品固定層１１＊（図２（ｄ）（ｅ）参照）によって周囲から固定されることから、半田接合部６ａ＊のサイズが小さい場合にあっても、必要十分な実装強度が確保される。   In this solder bonding process, since a low solder content type material is used as the solder bonding material 6A, the solder bonding portion 6a * for bonding the electrode 3a and the terminal 7a has a small volume of solidified solder, and the resin coat It is in a form that is easily covered by the portion 6c *. Such a small solder volume of the solder joint is not desirable in terms of mounting strength for fixing the electronic component in the case of mounting the electronic component 7 by normal solder joint, but the electronic component as in the present embodiment. In the configuration in which the electronic component 7 is built in the multilayer substrate, the electronic component 7 is fixed to the core layer 1 by the resin coat portion 6c *, and further, in the built-in state, the electronic component 7 is the component fixing layer 11 * (FIGS. 2D and 2E). Therefore, even when the size of the solder joint portion 6a * is small, necessary and sufficient mounting strength is ensured.

また熱硬化性樹脂６ｃ中に含有されている活性剤成分は、半田接合後においては熱硬化性樹脂が硬化した樹脂コート部６ｃ＊内に固溶した状態で存在していることから、活性剤成分が半田接合部に接触した状態で残留することによる悪影響が無い。したがって実施の形態１において必須とされた半田接合後の洗浄工程が不要となり、工程負荷の高い洗浄工程を排して工程簡略化を図ることが可能となっている。   Further, since the activator component contained in the thermosetting resin 6c is present in a solid solution state in the resin coat portion 6c * where the thermosetting resin is cured after the solder bonding, the activator is present. There is no adverse effect due to the component remaining in contact with the solder joint. Therefore, the cleaning process after solder bonding, which is essential in the first embodiment, is unnecessary, and it is possible to simplify the process by eliminating the cleaning process with a high process load.

この半田接合工程の後は、実施の形態１と同様の工程を経る。すなわち、半田接合工程後のコア層１を黒化処理することにより、配線回路３，５の表面３ｂ、５ａを粗化する黒化処理工程（図２（ｂ））と、黒化処理工程後のコア層１において、電子部品７を周囲から囲んで固定する部品固定層を形成するためのプリプレグ１１および部品固定層の表面に形成される表面層を少なくとも含む複数の配線層１２，１５をコア層１と貼り合わせて積層する積層工程（図２（ｃ））と、積層工程において形成された積層体１８を加熱加圧することにより、電子部品７を周囲から囲んで固定する部品固定層１１＊を形成するとともに、コア層１と複数の配線層１２，１５とを固着させるプレス工程（図２（ｄ））と、コア層１の配線回路３と配線層１２，１５とを接続する層間配線部１９を形成する層間配線工程と、配線層１２，１５に配線回路１４ａ、１７ａを形成する回路形成工程が順次実行される。   After this solder bonding process, the same process as in the first embodiment is performed. That is, by blackening the core layer 1 after the solder joining process, the blackening process (FIG. 2B) for roughening the surfaces 3b and 5a of the wiring circuits 3 and 5, and after the blackening process The core layer 1 includes a plurality of wiring layers 12 and 15 including at least a prepreg 11 for forming a component fixing layer for surrounding and fixing the electronic component 7 and a surface layer formed on a surface of the component fixing layer. A laminating step (FIG. 2C) for laminating and laminating with the layer 1, and a component fixing layer 11 * that surrounds and fixes the electronic component 7 from the periphery by heating and pressurizing the laminate 18 formed in the laminating step. And a pressing step for fixing the core layer 1 and the plurality of wiring layers 12 and 15 (FIG. 2D), and an interlayer wiring for connecting the wiring circuit 3 of the core layer 1 and the wiring layers 12 and 15 Interlayer wiring process for forming portion 19 , Circuit formation step of forming a wiring circuit 14a, a 17a to the wiring layer 12 and 15 are sequentially executed.

そしてこれにより、図２（ｅ）に示す部品内蔵プリント配線基板２０と同様構成の部品内蔵プリント配線基板２０が完成する。但し本実施の形態２においては、半田接合部を覆う樹脂コート部として、実施の形態１に示す塗布された樹脂による樹脂コート部９の替わりに、半田接合材６Ａ中の熱硬化性樹脂６ｃが熱硬化した樹脂コート部６ｃ＊が形成された構成となっている。   Thereby, the component built-in printed wiring board 20 having the same configuration as the component built-in printed wiring board 20 shown in FIG. However, in the second embodiment, the thermosetting resin 6c in the solder bonding material 6A is used as the resin coating portion covering the solder bonding portion, instead of the resin coating portion 9 by the applied resin shown in the first embodiment. The heat-cured resin coat portion 6c * is formed.

上記説明したように実施の形態１，２においては、コア層を含む複数の配線層を積層して構成されコア層に電子部品が実装された部品内蔵プリント配線基板の製造に際し、電子部品７が実装されたコア層１において電子部品７と電極３ａとの半田接合部を樹脂によって覆って樹脂コート部を形成するようにしている。これにより、複数の配線層を積層する際のプリプレグの密着性を確保するために行われる黒化処理において半田接合部が樹脂コート部によって保護されることから、コア層１への部品実装に半田接合を採用することが可能となる。したがって、コア層１への半田接合による部品実装とプリプレグを用いた配線層の積層という簡便な工程で、効率よく部品内蔵プリント配線基板を製造することができる。   As described above, in the first and second embodiments, in manufacturing a printed wiring board with a built-in component in which a plurality of wiring layers including a core layer are stacked and an electronic component is mounted on the core layer, the electronic component 7 is In the mounted core layer 1, the solder joint between the electronic component 7 and the electrode 3a is covered with resin to form a resin coat portion. As a result, the solder joint portion is protected by the resin coating portion in the blackening process performed to ensure the adhesion of the prepreg when laminating a plurality of wiring layers. Bonding can be employed. Therefore, the component built-in printed wiring board can be efficiently manufactured by a simple process of mounting the component by solder bonding to the core layer 1 and laminating the wiring layer using the prepreg.

本発明の部品内蔵プリント配線基板および部品内蔵プリント配線基板の製造方法は、簡便な工程で効率よく部品内蔵プリント配線基板を製造することができるという利点を有し、複数の配線層を積層して構成された部品内蔵プリント配線基板の製造分野に有用である。   The component-embedded printed wiring board and the method for manufacturing a component-embedded printed wiring board according to the present invention have the advantage that the component-embedded printed wiring board can be efficiently manufactured by a simple process, and a plurality of wiring layers are laminated. This is useful in the field of manufacturing a printed wiring board with built-in components.

本発明の実施の形態１の部品内蔵プリント配線基板の製造方法を示す工程説明図Process explanatory drawing which shows the manufacturing method of the component built-in printed wiring board of Embodiment 1 of this invention 本発明の実施の形態１の部品内蔵プリント配線基板の製造方法を示す工程説明図Process explanatory drawing which shows the manufacturing method of the component built-in printed wiring board of Embodiment 1 of this invention 本発明の実施の形態２の部品内蔵プリント配線基板の製造方法を示す工程説明図Process explanatory drawing which shows the manufacturing method of the component built-in printed wiring board of Embodiment 2 of this invention

符号の説明Explanation of symbols

１ コア層
２ 樹脂基板
３、１４ａ、１７ａ 配線回路
３ａ 電極
４ ソルダレジスト
６ クリーム半田
６ａ 半田粒子
６ａ＊ 半田接合部
７ 電子部品
７ａ 端子
８ 洗浄剤
９ 樹脂コート部
１１、１３、１６ プリプレグ
１２、１５ 配線層
１４，１７ 銅箔
１８ 積層体
１９ 層間配線部
２０ 部品内蔵プリント配線基板 DESCRIPTION OF SYMBOLS 1 Core layer 2 Resin substrate 3, 14a, 17a Wiring circuit 3a Electrode 4 Solder resist 6 Cream solder 6a Solder particle 6a * Solder joint part 7 Electronic component 7a Terminal 8 Cleaning agent 9 Resin coating part 11, 13, 16 Prepreg 12, 15 Wiring layers 14, 17 Copper foil 18 Laminate body 19 Interlayer wiring portion 20 Printed wiring board with built-in components

Claims (2)

コア層を含む複数の配線層を積層して構成され前記コア層に電子部品が実装された部品内蔵プリント配線基板であって、
前記電子部品は前記コア層の少なくとも一方の面に形成された配線回路を構成する接続用の電極に半田接合されており、
前記コア層を除く前記配線層はプリプレグが固化した絶縁層に配線回路を形成して構成されており、
前記コア層において前記電子部品と前記電極との半田接合部を樹脂によって覆って形成された樹脂コート部と、
前記コア層の前記一方の面に積層されたプリプレグを固化させることにより形成され前記電子部品および前記樹脂コート部を周囲から固定する部品固定層と、
前記複数の配線層の１つであって前記部品固定層の表面に形成された表面層と、
前記コア層の配線回路と前記表面層を含む他の配線層の配線回路とを接続する層間配線部とを備え、前記電子部品と前記接続用の電極は半田の酸化膜を除去する活性作用を有する熱硬化性樹脂に半田粒子を５０ｗｔ％〜８８ｗｔ％の含有率で含有させた半田接合材によって半田接合されており、前記樹脂コート部は前記熱硬化性樹脂が硬化した樹脂によって形成されていることを特徴とする部品内蔵プリント配線基板。 A printed wiring board with a built-in component in which a plurality of wiring layers including a core layer are stacked and an electronic component is mounted on the core layer,
The electronic component is soldered to a connection electrode constituting a wiring circuit formed on at least one surface of the core layer,
The wiring layer excluding the core layer is formed by forming a wiring circuit in an insulating layer in which a prepreg is solidified,
A resin coat part formed by covering a solder joint between the electronic component and the electrode with a resin in the core layer;
A component fixing layer formed by solidifying a prepreg laminated on the one surface of the core layer, and fixing the electronic component and the resin coat portion from the surroundings;
A surface layer that is one of the plurality of wiring layers and is formed on the surface of the component fixing layer;
An interlayer wiring portion for connecting the wiring circuit of the core layer and the wiring circuit of another wiring layer including the surface layer, and the electronic component and the connection electrode have an active action of removing a solder oxide film The thermosetting resin is solder-bonded by a solder bonding material containing solder particles at a content of 50 wt% to 88 wt% , and the resin coat portion is formed of a resin obtained by curing the thermosetting resin. A printed wiring board with built-in components. コア層を含む複数の配線層を積層して構成され前記コア層に電子部品が実装された部品内蔵プリント配線基板を製造する部品内蔵プリント配線基板の製造方法であって、
前記コア層の少なくとも一方の面に形成された配線回路を構成する接続用の電極に、半田の酸化膜を除去する活性作用を有する熱硬化性樹脂に半田粒子を５０ｗｔ％〜８８ｗｔ％の含有率で含有させた半田接合材を供給する半田供給工程と、
前記半田供給工程後のコア層に前記電子部品を搭載する部品搭載工程と、
前記部品搭載工程後のコア層を加熱することにより前記電極と前記電子部品とを半田接合するとともに、前記電極と前記電子部品との半田接合部を前記熱硬化性樹脂が硬化した樹脂で覆って樹脂コート部を形成する半田接合工程と、
前記半田接合工程後のコア層を黒化処理することにより、前記配線回路の表面を粗化する黒化処理工程と、
前記黒化処理工程後のコア層において、前記電子部品を周囲から囲んで固定する部品固定層を形成するためのプリプレグおよび前記部品固定層の表面に形成される表面層を少なくとも含む複数の配線層を前記コア層と貼り合わせて積層する積層工程と、
前記積層工程において形成された積層体を加熱加圧することにより、前記電子部品を周囲から囲んで固定する部品固定層を形成するとともに、前記コア層と前記複数の配線層とを固着させるプレス工程と、
前記コア層の配線回路と前記配線層とを接続する層間配線部を形成する層間配線工程と、
前記配線層に配線回路を形成する回路形成工程とを含むことを特徴とする部品内蔵プリント配線基板の製造方法。 A method of manufacturing a component built-in printed wiring board for manufacturing a component built-in printed wiring board configured by laminating a plurality of wiring layers including a core layer and mounting electronic components on the core layer,
Content of solder particles in a thermosetting resin having an activity of removing an oxide film of solder on a connection electrode constituting a wiring circuit formed on at least one surface of the core layer in a range of 50 wt% to 88 wt% a solder supply step of supplying a solder bonding material which contains in,
A component mounting step of mounting the electronic component on the core layer after the solder supply step;
By heating the core layer after the component mounting step, the electrode and the electronic component are soldered together, and the solder joint portion between the electrode and the electronic component is covered with a resin cured by the thermosetting resin. A solder bonding step for forming a resin coat portion;
A blackening treatment step of roughening the surface of the wiring circuit by blackening the core layer after the solder bonding step;
In the core layer after the blackening treatment step, a plurality of wiring layers including at least a prepreg for forming a component fixing layer for surrounding and fixing the electronic component and a surface layer formed on the surface of the component fixing layer Laminating step of laminating and laminating the core layer;
A pressing step for fixing the core layer and the plurality of wiring layers while forming a component fixing layer for surrounding and fixing the electronic component by heating and pressing the laminate formed in the stacking step; ,
An interlayer wiring process for forming an interlayer wiring portion connecting the wiring circuit of the core layer and the wiring layer;
And a circuit forming step for forming a wiring circuit in the wiring layer.
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