JP5161503B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5161503B2 JP5161503B2 JP2007179753A JP2007179753A JP5161503B2 JP 5161503 B2 JP5161503 B2 JP 5161503B2 JP 2007179753 A JP2007179753 A JP 2007179753A JP 2007179753 A JP2007179753 A JP 2007179753A JP 5161503 B2 JP5161503 B2 JP 5161503B2
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- forming
- via hole
- etching
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- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000005530 etching Methods 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 33
- 239000011229 interlayer Substances 0.000 claims description 25
- 230000009977 dual effect Effects 0.000 claims description 14
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 8
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000007789 gas Substances 0.000 description 52
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000007795 chemical reaction product Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
Si、O、およびCを含む材料からなる層間絶縁膜105としては、低誘電率材料が用いられ、例えば炭素含有シリコン酸化膜(SiOC膜)である。このような低誘電率材料は、寄生容量の低減に効果的である。また、本実施の形態では、このような低誘電率材料からなる層間絶縁膜に良好なボーイング形状のビアホールを安定的に形成できる。
さらに、本実施の形態では、ビアホールをボーイング形状に制御するとともに、深さ方向においてもビア径を制御できる。
さらに、ビアの深さ方向におけるボーイングが入る位置は、ステージ温度で調整することが可能である。好ましい温度範囲は、特に限定されないが、例えば、0℃以上40℃以下である。
上記実施の形態と同様の方法により、ボーイング形状のビアホールを形成した。本実施例において、180sccmのN2ガス流量条件を用いてビアホールを形成した。なお、層間絶縁膜の構成およびエッチング条件等は以下のとおりであった。
(層間絶縁膜)
・ストッパ膜:SiCN(厚さ50nm)
・層間絶縁膜:SiOC(厚さ400nm)
・シリコン酸化防止膜(厚さ180nm)
(エッチング条件)
二周波数RIE装置を用い、以下の条件を用いて、ボーイング形状を得た。
・ターゲットホールサイズ:170nm
・エッチングガス:CF4 30sccm、CHF3 30sccm、Ar 1000sccm、N2 180sccm
・条件:上部投入電力2000W、下部投入電力、Bias2000W、ステージ温度20℃
N2ガス流量条件を60sccmとした以外は、実施例1と同様の条件を用いてビアホールを形成した。
N2ガス流量条件を120sccmとした以外は、実施例1と同様の条件を用いてビアホールを形成した。
N2ガス流量180sccmを用い、種々のホールサイズを用いた以外は、実施例1
と同様の条件を用いてボーイング形状のビアホールを形成した。本実施例では、120nm、140nm、160nm、180nm、および190nmのホールサイズを用いた。
2 ビア部
3 層間絶縁膜
101 下層導電膜
103 ストッパ膜
105 層間絶縁膜
107 シリコン酸化膜
109 反射防止膜
111 レジスト膜
112 ビアホール
113 下層レジスト膜
115 低温酸化膜
117 反射防止膜
119 レジスト膜
121 配線溝
301 下層配線
303 ストッパ膜
305 低誘電率膜
307 シリコン酸化膜
309 反射防止膜
311 レジスト膜
312 ビアホール
313 下層レジスト膜
315 低温酸化膜
317 反射防止膜
319 レジスト膜
321 配線溝
Claims (6)
- 半導体基板上に形成された下層導電膜上に、Si、O、およびCを含む材料からなる層間絶縁膜を形成する工程と、
前記層間絶縁膜に、フルオロカーボン系ガスおよびN2ガスを含むエッチングガスを用いたドライエッチングによりビアホールを形成する工程と、
つづいて前記層間絶縁膜に、前記ビアホールに接続する配線溝を形成し、当該層間絶縁膜に前記下層導電膜に接続するデュアルダマシン配線を形成するためのデュアルダマシン配線溝を形成する工程と、
を含み、
前記ビアホールを形成する工程において、ビアホールをボーイング形状に形成し、および前記配線溝を形成する工程において、前記ビアホールが最大径となる近傍領域の位置までエッチングして、前記配線溝を形成するとともに、前記配線溝の下部に順テーパー形状のビアを形成する、
半導体装置の製造方法。 - 前記配線溝形成前の前記ビアホールの開口径dとビアホールの最大径c部分との比が1.03≦c/d≦1.1の範囲である、請求項1に記載の半導体装置の製造方法。
- 前記N2ガスの流量が170sccm以上350sccm以下である、請求項1または2に記載の半導体装置の製造方法。
- エッチングガスの総流量に対する前記N2ガスの流量の比率が15%以上25%以下である、請求項1乃至3のいずれかに記載の半導体装置の製造方法。
- 前記配線溝形成前の前記ビアホールの開口径dが、110nm以上190nm以下の範囲である、請求項1乃至4のいずれかに記載の半導体装置の製造方法。
- ビアホールを形成する前記工程において、ステージ温度が、0℃以上40℃以下である、請求項1乃至5のいずれかに記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007179753A JP5161503B2 (ja) | 2007-07-09 | 2007-07-09 | 半導体装置の製造方法 |
US12/216,610 US20090017620A1 (en) | 2007-07-09 | 2008-07-08 | Method of manufacturing semiconductor device for dual damascene wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007179753A JP5161503B2 (ja) | 2007-07-09 | 2007-07-09 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009016737A JP2009016737A (ja) | 2009-01-22 |
JP5161503B2 true JP5161503B2 (ja) | 2013-03-13 |
Family
ID=40253506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007179753A Expired - Fee Related JP5161503B2 (ja) | 2007-07-09 | 2007-07-09 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
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US (1) | US20090017620A1 (ja) |
JP (1) | JP5161503B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5357710B2 (ja) * | 2009-11-16 | 2013-12-04 | 東京エレクトロン株式会社 | 基板処理方法,基板処理装置,プログラムを記録した記録媒体 |
JP2013021001A (ja) * | 2011-07-07 | 2013-01-31 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US9564359B2 (en) * | 2014-07-17 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive structure and method of forming the same |
US9613861B2 (en) | 2015-08-05 | 2017-04-04 | Globalfoundries Inc. | Damascene wires with top via structures |
US9679850B2 (en) * | 2015-10-30 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating semiconductor structure |
WO2017190117A1 (en) * | 2016-04-30 | 2017-11-02 | BioLegend, Inc. | Compositions and methods for performing magnetibuoyant separations |
US10964648B2 (en) * | 2017-04-24 | 2021-03-30 | International Business Machines Corporation | Chip security fingerprint |
US10752496B2 (en) * | 2017-09-22 | 2020-08-25 | Applied Materials, Inc. | Pore formation in a substrate |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001135724A (ja) * | 1999-11-10 | 2001-05-18 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US7502936B2 (en) * | 2001-02-14 | 2009-03-10 | Jsm Technologies, L.L.C. | System and method providing secure access to a computer system |
KR100454128B1 (ko) * | 2002-04-02 | 2004-10-26 | 삼성전자주식회사 | 금속간 절연막 패턴 및 그 형성 방법 |
JP2004031759A (ja) * | 2002-06-27 | 2004-01-29 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US7115517B2 (en) * | 2003-04-07 | 2006-10-03 | Applied Materials, Inc. | Method of fabricating a dual damascene interconnect structure |
JP3976703B2 (ja) * | 2003-04-30 | 2007-09-19 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
-
2007
- 2007-07-09 JP JP2007179753A patent/JP5161503B2/ja not_active Expired - Fee Related
-
2008
- 2008-07-08 US US12/216,610 patent/US20090017620A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20090017620A1 (en) | 2009-01-15 |
JP2009016737A (ja) | 2009-01-22 |
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