JP5159744B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5159744B2 JP5159744B2 JP2009246054A JP2009246054A JP5159744B2 JP 5159744 B2 JP5159744 B2 JP 5159744B2 JP 2009246054 A JP2009246054 A JP 2009246054A JP 2009246054 A JP2009246054 A JP 2009246054A JP 5159744 B2 JP5159744 B2 JP 5159744B2
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- 239000004065 semiconductor Substances 0.000 title claims description 27
- 239000000463 material Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 12
- 229910010271 silicon carbide Inorganic materials 0.000 description 12
- 230000000694 effects Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
- H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は、本発明の実施形態による半導体装置の平面図であり、図2は、図1に示す半導体装置の側面透視図である。図1,2に示すように、本実施形態による半導体装置は、スイッチング動作を行うパワーチップ1(パワーチップ部)と、パワーチップ1を制御するIC(Integrated Circuit)2(IC部)と、パワーチップ1とIC2とをモールド樹脂で封止したパッケージ3とを備えており、パッケージ3のパワーチップ1とIC2との間には貫通穴4(第1の貫通穴)が形成されている。パワーチップ1およびIC2の各々には、パッケージ3の外部に延設された端子が接続されており、パワーチップ1とIC2とはワイヤによって電気的に接続されている。
本発明の実施形態2では、貫通穴4の開口端の形状が、テーパ形状またはR形状であることを特徴としている。その他の構成は実施形態1と同様であるため、ここでは説明を省略する。
本発明の実施形態3では、各々のパワーチップ1の間に貫通穴5(第2の貫通穴)が形成されることを特徴としている。その他の構成は実施形態1と同様であるため、ここでは説明を省略する。
本発明の実施形態4では、パワーチップ1がSiCを材料として構成されることを特徴としている。その他の構成は実施形態1〜3と同様であるため、ここでは説明を省略する。
本発明の実施形態5では、実施形態4と同様に、パワーチップ1がSiCを材料として構成されることを特徴としている。その他の構成は実施形態1〜3と同様であるため、ここでは説明を省略する。
Claims (5)
- スイッチング動作を行うパワーチップ部と、
前記パワーチップ部を制御するIC部と、
前記パワーチップ部と前記IC部とをモールド樹脂で封止したパッケージと、
前記パッケージの前記パワーチップ部と前記IC部との間に形成された第1の貫通穴と、
を備え、
前記パワーチップ部は、複数個離間して並設され、各々の前記パワーチップ部の間には第2の貫通穴が形成され、
前記パワーチップ部は、SiCを材料として構成されることを特徴とする、半導体装置。 - 前記第1の貫通穴は、前記パワーチップ部と前記IC部との間隔方向を短手方向とし、前記短手方向に対して垂直方向を長手方向とした長穴であることを特徴とする、請求項1に記載の半導体装置。
- 前記長穴は、前記長手方向に沿って複数個設けられることを特徴とする、請求項2に記載の半導体装置。
- 前記第2の貫通穴は、前記離間方向を短手方向とし、前記短手方向に対して垂直方向を長手方向とした長穴であることを特徴とする、請求項1に記載の半導体装置。
- 前記第1の貫通穴および前記第2の貫通穴の開口端の形状は、テーパ形状またはR形状であることを特徴とする、請求項1ないし4のいずれかに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2009246054A JP5159744B2 (ja) | 2009-10-27 | 2009-10-27 | 半導体装置 |
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JP2009246054A JP5159744B2 (ja) | 2009-10-27 | 2009-10-27 | 半導体装置 |
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JP2011096696A JP2011096696A (ja) | 2011-05-12 |
JP5159744B2 true JP5159744B2 (ja) | 2013-03-13 |
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JP2009246054A Active JP5159744B2 (ja) | 2009-10-27 | 2009-10-27 | 半導体装置 |
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Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6255118B2 (ja) * | 2011-10-31 | 2017-12-27 | ローム株式会社 | 半導体装置 |
JP5921491B2 (ja) | 2013-06-13 | 2016-05-24 | 三菱電機株式会社 | 電力用半導体装置 |
JP6365322B2 (ja) * | 2015-01-23 | 2018-08-01 | 三菱電機株式会社 | 半導体装置 |
US11398818B2 (en) | 2018-06-04 | 2022-07-26 | Rohm Co., Ltd. | Semiconductor device |
WO2020194431A1 (ja) * | 2019-03-25 | 2020-10-01 | 三菱電機株式会社 | 回路基板および空気調和機 |
JP2023013254A (ja) | 2021-07-15 | 2023-01-26 | 三菱電機株式会社 | 半導体装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH024248U (ja) * | 1988-06-20 | 1990-01-11 | ||
JPH09232473A (ja) * | 1996-02-21 | 1997-09-05 | Toshiba Corp | 半導体パッケージとその製造方法およびプリント基板 |
JP4533152B2 (ja) * | 2005-01-06 | 2010-09-01 | 三菱電機株式会社 | 半導体装置 |
JP2007096035A (ja) * | 2005-09-29 | 2007-04-12 | Sanyo Electric Co Ltd | 回路装置および回路実装体 |
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