JP5133963B2 - セラミック基板 - Google Patents

セラミック基板 Download PDF

Info

Publication number
JP5133963B2
JP5133963B2 JP2009252854A JP2009252854A JP5133963B2 JP 5133963 B2 JP5133963 B2 JP 5133963B2 JP 2009252854 A JP2009252854 A JP 2009252854A JP 2009252854 A JP2009252854 A JP 2009252854A JP 5133963 B2 JP5133963 B2 JP 5133963B2
Authority
JP
Japan
Prior art keywords
layer
silver
nickel
metal
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009252854A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010028146A5 (enExample
JP2010028146A (ja
Inventor
久 若子
誠 永井
敦士 内田
雅仁 森田
賀津雄 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2009252854A priority Critical patent/JP5133963B2/ja
Publication of JP2010028146A publication Critical patent/JP2010028146A/ja
Publication of JP2010028146A5 publication Critical patent/JP2010028146A5/ja
Application granted granted Critical
Publication of JP5133963B2 publication Critical patent/JP5133963B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Landscapes

  • Led Device Packages (AREA)
  • Semiconductor Lasers (AREA)
JP2009252854A 2004-12-03 2009-11-04 セラミック基板 Expired - Fee Related JP5133963B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009252854A JP5133963B2 (ja) 2004-12-03 2009-11-04 セラミック基板

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2004350927 2004-12-03
JP2004350927 2004-12-03
JP2005084449 2005-03-23
JP2005084449 2005-03-23
JP2009252854A JP5133963B2 (ja) 2004-12-03 2009-11-04 セラミック基板

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2005343890A Division JP2006303419A (ja) 2004-12-03 2005-11-29 セラミック基板

Publications (3)

Publication Number Publication Date
JP2010028146A JP2010028146A (ja) 2010-02-04
JP2010028146A5 JP2010028146A5 (enExample) 2011-03-31
JP5133963B2 true JP5133963B2 (ja) 2013-01-30

Family

ID=41733609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009252854A Expired - Fee Related JP5133963B2 (ja) 2004-12-03 2009-11-04 セラミック基板

Country Status (1)

Country Link
JP (1) JP5133963B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170011735A (ko) * 2015-07-24 2017-02-02 엘지이노텍 주식회사 발광소자 패키지

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5958342B2 (ja) * 2010-10-27 2016-07-27 旭硝子株式会社 発光素子用基板および発光装置
DE102015208704A1 (de) * 2015-05-11 2016-11-17 Osram Opto Semiconductors Gmbh Optoelektronisches Bauteil
CN112159253A (zh) * 2020-09-26 2021-01-01 深圳市海里表面技术处理有限公司 5g通讯用电阻陶瓷镀银工艺及陶瓷片

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04152661A (ja) * 1990-10-17 1992-05-26 Hitachi Cable Ltd Ｉｃ用リードフレーム
JPH06334087A (ja) * 1993-05-21 1994-12-02 Hitachi Cable Ltd 半導体装置用リードフレームの製造方法
JP2003347600A (ja) * 2002-05-28 2003-12-05 Matsushita Electric Works Ltd Ｌｅｄ実装基板
JP2004228549A (ja) * 2002-11-25 2004-08-12 Kyocera Corp 発光素子収納用パッケージおよび発光装置
JP3940124B2 (ja) * 2003-01-16 2007-07-04 松下電器産業株式会社 装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170011735A (ko) * 2015-07-24 2017-02-02 엘지이노텍 주식회사 발광소자 패키지
KR102413301B1 (ko) * 2015-07-24 2022-06-27 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광소자 패키지

Also Published As

Publication number Publication date
JP2010028146A (ja) 2010-02-04

Similar Documents

Publication Publication Date Title
KR101154801B1 (ko) 세라믹 기판 및 발광 소자 수납용 세라믹 패키지
JP5967836B2 (ja) セラミック基板およびその製造方法
JP5093840B2 (ja) 発光素子実装用多層配線基板とその製造方法
JP6298163B2 (ja) 配線基板、電子装置および電子モジュール
JP6483800B2 (ja) 発光素子搭載用パッケージ、発光装置および発光モジュール
JP2015185820A (ja) 配線基板および電子装置
JP5133963B2 (ja) セラミック基板
JP5977180B2 (ja) 配線基板
JP2006303419A (ja) セラミック基板
JP2005019688A (ja) 発光素子収納用パッケージおよび発光装置
JP2009135536A (ja) 発光素子収納用パッケージおよび発光装置
JP4998183B2 (ja) 電子装置
JP4336137B2 (ja) 発光素子収納用パッケージおよび発光装置
JP6306474B2 (ja) 配線基板、電子装置および電子モジュール
JP6123215B2 (ja) 発光装置
JP4070195B2 (ja) 発光素子収納用パッケージ
JP6166194B2 (ja) 配線基板、電子装置および電子モジュール
JP5787808B2 (ja) プローブカード用配線基板およびそれを用いたプローブカード
JP2004221520A (ja) 発光素子収納用パッケージおよび発光装置
JP6267068B2 (ja) 配線基板、電子装置および電子モジュール
JP4548262B2 (ja) 下部電極構造
JP5631268B2 (ja) 配線基板
CN111490018A (zh) 具有金属导热凸块接垫的陶瓷基板元件、组件及制法
JP2008159969A (ja) 回路基板、電子装置および回路基板の製造方法
EP4113590A1 (en) Electronic component mounting package and electronic device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091204

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20091204

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110209

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120821

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120828

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120919

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121016

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121108

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151116

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5133963

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees