JP5113089B2 - 選択可能な副精度に対して、低減された電力要求を有する浮動小数点プロセッサ - Google Patents
選択可能な副精度に対して、低減された電力要求を有する浮動小数点プロセッサ Download PDFInfo
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Description
Claims (23)
- 第1の精度を有し、浮動小数点演算を実行するように動作可能な浮動小数点プロセッサにより、浮動小数点演算を実行する方法において、
前記方法は、
1つ以上の浮動小数点数に関する前記浮動小数点演算に対して、アプリケーションを実行するための精度に基づいて、前記第1の精度よりも小さい副精度を選択し、前記副精度の選択は、1つ以上の過剰ビットをもたらすことと、
前記1つ以上の過剰ビットを処理するために使用される、ロジック回路の一部から電力を取り除くことと、
前記過剰ビットに対応する、レジスタファイル内のレジスタの一部から電力を取り除くことと、
前記電力が取り除かれたレジスタを使用して、前記選択した副精度で、前記電力が取り除かれたロジック回路により前記浮動小数点演算を実行して、結果として生じる出力を発生させることとを含む方法。 - 前記ロジック回路の一部のステージからの桁上がり値を強制的にゼロにすることをさらに含む請求項1記載の方法。
- 前記副精度は、浮動小数点制御装置を使用して選択される請求項1記載の方法。
- 前記浮動小数点制御装置は、ユーザにより制御される請求項3記載の方法。
- 一連のスイッチが、前記レジスタファイル内のレジスタの一部から電力を取り除くために使用される請求項1記載の方法。
- 前記スイッチは、電界効果トランジスタである請求項5記載の方法。
- 前記スイッチは、前記レジスタファイル内のレジスタの一部に対して内部にある請求項5記載の方法。
- 前記スイッチは、前記レジスタファイル内のレジスタの一部に対して外部にある請求項5記載の方法。
- 前記浮動小数点演算を実行することからの中間結果と、前記結果として生じる出力とが、前記レジスタファイル中に記憶される請求項1記載の方法。
- 第1の精度を有する浮動小数点プロセッサにおいて、
浮動小数点演算に対して、アプリケーションを実行するための精度に基づいて、前記第1の精度よりも小さい副精度を選択するように構成された浮動小数点制御装置であって、前記副精度の選択は、1つ以上の過剰ビットをもたらし、前記浮動小数点制御装置は、前記過剰ビットに対応する、前記浮動小数点プロセッサ中のレジスタファイル内のレジスタの一部から電力を取り除き、前記1つ以上の過剰ビットを処理するために使用される、ロジック回路の一部から電力を取り除くようにさらに構成されている浮動小数点制御装置と、
前記電力が取り除かれたレジスタを使用して、前記選択した副精度で、前記電力が取り除かれたロジック回路により前記浮動小数点演算を実行して、結果として生じる出力を発生させるように構成された浮動小数点演算器とを具備する浮動小数点プロセッサ。 - 前記浮動小数点演算器は、浮動小数点加算器を含み、前記浮動小数点演算を実行することからの中間結果と、前記結果として生じる出力とが、前記レジスタファイル中に記憶される請求項10記載の浮動小数点プロセッサ。
- 前記電力が取り除かれるとき、前記浮動小数点演算器は、前記ロジック回路の第2の部分からの桁上がりを強制的にゼロにするようにさらに構成されている請求項11記載の浮動小数点プロセッサ。
- 前記浮動小数点演算器は、浮動小数点乗算器を含む請求項10記載の浮動小数点プロセッサ。
- 第1の精度を有する浮動小数点プロセッサにおいて、
1つ以上の浮動小数点数を記憶するように構成された、複数の記憶素子を有する浮動小数点レジスタと、
前記浮動小数点レジスタ中に記憶された前記1つ以上の浮動小数点数に関して、浮動小数点演算を実行するように構成された浮動小数点演算器と、
前記1つ以上の浮動小数点数に関する浮動小数点演算に対して、アプリケーションを実行するための精度に基づいて、前記第1の精度よりも小さい副精度を選択するように構成された浮動小数点制御装置とを具備し、
前記副精度の選択は、1つ以上の過剰ビットをもたらし、
前記浮動小数点制御装置は、前記過剰ビットに対応する、前記記憶素子の一部から電力を取り除き、前記浮動小数点演算により前記1つ以上の過剰ビットを処理するために使用される、ロジック回路の一部から電力を取り除くようにさらに構成されている浮動小数点プロセッサ。 - 一連のスイッチが、前記記憶素子の一部から電力を取り除くために使用される請求項14記載の浮動小数点プロセッサ。
- 前記スイッチは、前記記憶素子に対して内部にある請求項15記載の浮動小数点プロセッサ。
- 前記スイッチは、前記記憶素子に対して外部にある請求項15記載の浮動小数点プロセッサ。
- 前記浮動小数点演算は、前記記憶素子の一部から電力が取り除かれた状態で実行される請求項14記載の浮動小数点プロセッサ。
- 前記浮動小数点演算は、複数ステージのビット加算を含み、前記複数ステージのビット加算の1つ以上のステージは、前記副精度にしたがって電源が切られ、最後に電源が切られたステージからの桁上がり値は、強制的に論理ゼロ値にされる請求項14記載の浮動小数点プロセッサ。
- 最大精度を有する浮動小数点プロセッサにおいて、
1つ以上の浮動小数点数を記憶するように構成された浮動小数点レジスタと、
浮動小数点演算を実行するように構成されたロジックを有する浮動小数点演算器と、
前記1つ以上の浮動小数点数に関する浮動小数点演算に対して、アプリケーションを実行するための精度に基づいて、前記最大精度よりも小さい副精度を選択するように構成された浮動小数点制御装置とを具備し、
前記副精度の選択は、前記1つ以上の浮動小数点数のそれぞれに対して、1つ以上の過剰ビットをもたらし、
前記浮動小数点制御装置は、さもなければ前記1つ以上の過剰ビットを処理するために使用される、前記ロジックの一部から電力を取り除き、前記過剰ビットに対応する、前記浮動小数点レジスタ内のレジスタの一部から電力を取り除くようにさらに構成されている浮動小数点プロセッサ。 - 前記浮動小数点演算器は、浮動小数点加算器を含む請求項20記載の浮動小数点プロセッサ。
- 前記電力が取り除かれるとき、前記浮動小数点演算器は、前記ロジックの一部のステージからの桁上がりを強制的にゼロにするようにさらに構成されている請求項21記載の浮動小数点プロセッサ。
- 前記浮動小数点演算器は、浮動小数点乗算器を含む請求項20記載の浮動小数点プロセッサ。
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US11/363,118 US8595279B2 (en) | 2006-02-27 | 2006-02-27 | Floating-point processor with reduced power requirements for selectable subprecision |
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PCT/US2007/062908 WO2007101216A2 (en) | 2006-02-27 | 2007-02-27 | Floating-point processor with reduced power requirements for selectable subprecision |
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JP2016206781A Active JP6495220B2 (ja) | 2006-02-27 | 2016-10-21 | 選択可能な副精度に対して、低減された電力要求を有する浮動小数点プロセッサ |
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JP2014258023A Withdrawn JP2015133111A (ja) | 2006-02-27 | 2014-12-19 | 選択可能な副精度に対して、低減された電力要求を有する浮動小数点プロセッサ |
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KR (1) | KR100994862B1 (ja) |
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JP2012230684A (ja) | 2012-11-22 |
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CN101390045A (zh) | 2009-03-18 |
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WO2007101216A3 (en) | 2008-01-03 |
BRPI0708284A2 (pt) | 2011-05-24 |
KR20080098440A (ko) | 2008-11-07 |
MX2008010873A (es) | 2008-09-04 |
JP6495220B2 (ja) | 2019-04-03 |
CA2641334C (en) | 2015-07-21 |
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