JP5067151B2 - モールドパッケージの製造方法 - Google Patents
モールドパッケージの製造方法 Download PDFInfo
- Publication number
- JP5067151B2 JP5067151B2 JP2007327095A JP2007327095A JP5067151B2 JP 5067151 B2 JP5067151 B2 JP 5067151B2 JP 2007327095 A JP2007327095 A JP 2007327095A JP 2007327095 A JP2007327095 A JP 2007327095A JP 5067151 B2 JP5067151 B2 JP 5067151B2
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- Prior art keywords
- heat sink
- island
- mold
- resin
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
なお、上記実施形態においては、制御素子用のアイランド11の直下に金型のゲートが位置するものであったが、金型のゲートは、パワー素子用のアイランド11の直下に位置するヒートシンク20の貫通穴21の直下に位置してもよい。この場合、上記したゲート206と貫通穴21とを連通する溝22は、ヒートシンク20の下面20bに設けなくてもよい。
11 アイランド
11a アイランドの上面
11b アイランドの下面
12 リード
20 ヒートシンク
20a ヒートシンクの上面
20b ヒートシンクの下面
21 貫通穴
22 溝
30 パワー素子
40 制御素子
60 配線基板
80 モールド樹脂
100 ワーク
200 金型
204 キャビティ
205 支持部材
206 ゲート
Claims (4)
- リードフレーム(10)のアイランド(11)の一面(11b)とヒートシンク(20)の一面(20a)とを対向して配置してなるワーク(100)を、金型(200)のキャビティ(204)内に設置し、
前記キャビティ(204)内に樹脂(80)を注入して前記ワーク(100)を封止するモールドパッケージの製造方法において、
前記ワーク(100)における前記ヒートシンク(20)に対して、前記ヒートシンク(20)の前記一面(20a)と当該一面(20a)とは反対の他面(20b)との間で貫通する貫通穴(21)を設けておき、
前記ワーク(100)の前記キャビティ(204)への設置工程では、前記キャビティ(204)内に設けられた支持部材(205)によって前記アイランド(11)および前記ヒートシンク(20)を支持固定することにより、前記ヒートシンク(20)の前記一面(20a)と前記アイランド(11)の前記一面(11b)との隙間寸法を固定した状態とし、
前記樹脂(80)の注入工程では、前記ワーク(100)を前記樹脂(80)で封止するとともに、前記ヒートシンク(20)の前記他面(20b)側から前記貫通穴(21)を介して、前記ヒートシンク(20)の前記一面(20a)と前記アイランド(11)の前記一面(11b)との隙間に、前記樹脂(80)を注入し、
前記隙間に注入された前記樹脂(80)により、前記ヒートシンク(20)と前記アイランド(11)とを接合するようにしたことを特徴とするモールドパッケージの製造方法。 - 前記金型(200)における前記キャビティ(204)のうち前記ヒートシンク(20)の前記他面(20b)に対向する部位に、前記樹脂(80)を注入するゲート(206)が設けられており、
前記ヒートシンク(20)の前記他面(20b)には、前記ゲート(206)と前記貫通穴(21)とを連通する溝(22)が設けられていることを特徴とする請求項1に記載のモールドパッケージの製造方法。 - 前記アイランド(11)を支持する前記支持部材(205)は、前記キャビティ(204)の内面から突出する突出部材であり、その先端部にて前記アイランド(11)を支持するものであることを特徴とする請求項1または2に記載のモールドパッケージの製造方法。
- 前記アイランド(11)は、前記ヒートシンク(20)からはみ出しており、このアイランド(11)におけるはみ出している部位にて、前記支持部材(205)の先端部が接触して支持を行うようにしたことを特徴とする請求項3に記載のモールドパッケージの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007327095A JP5067151B2 (ja) | 2007-12-19 | 2007-12-19 | モールドパッケージの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007327095A JP5067151B2 (ja) | 2007-12-19 | 2007-12-19 | モールドパッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009152280A JP2009152280A (ja) | 2009-07-09 |
JP5067151B2 true JP5067151B2 (ja) | 2012-11-07 |
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ID=40921108
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Application Number | Title | Priority Date | Filing Date |
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JP2007327095A Expired - Fee Related JP5067151B2 (ja) | 2007-12-19 | 2007-12-19 | モールドパッケージの製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP5067151B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2023148836A1 (ja) * | 2022-02-02 | 2023-08-10 | 日立Astemo株式会社 | 半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2836219B2 (ja) * | 1990-08-10 | 1998-12-14 | 株式会社デンソー | 樹脂封止型半導体パッケージ |
JPH04306865A (ja) * | 1991-04-03 | 1992-10-29 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP3123482B2 (ja) * | 1997-10-08 | 2001-01-09 | 日本電気株式会社 | 低熱抵抗型半導体パッケージ、および低熱抵抗型半導体パッケージの製造方法 |
JP4366700B2 (ja) * | 1998-10-05 | 2009-11-18 | 富士電機デバイステクノロジー株式会社 | 半導体素子のパッケージの製造方法 |
JP3737673B2 (ja) * | 2000-05-23 | 2006-01-18 | 株式会社ルネサステクノロジ | 半導体装置 |
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- 2007-12-19 JP JP2007327095A patent/JP5067151B2/ja not_active Expired - Fee Related
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JP2009152280A (ja) | 2009-07-09 |
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