JP5063430B2 - 光伝送機構を備えたモジュール基板およびその製造方法 - Google Patents

光伝送機構を備えたモジュール基板およびその製造方法 Download PDF

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Publication number
JP5063430B2
JP5063430B2 JP2008077274A JP2008077274A JP5063430B2 JP 5063430 B2 JP5063430 B2 JP 5063430B2 JP 2008077274 A JP2008077274 A JP 2008077274A JP 2008077274 A JP2008077274 A JP 2008077274A JP 5063430 B2 JP5063430 B2 JP 5063430B2
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Japan
Prior art keywords
optical transmission
component
transmission mechanism
module substrate
optical
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JP2008077274A
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English (en)
Japanese (ja)
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JP2009229962A (ja
JP2009229962A5 (enExample
Inventor
直幸 小泉
淳 大井
昭彦 立岩
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008077274A priority Critical patent/JP5063430B2/ja
Priority to US12/408,820 priority patent/US8111954B2/en
Publication of JP2009229962A publication Critical patent/JP2009229962A/ja
Publication of JP2009229962A5 publication Critical patent/JP2009229962A5/ja
Application granted granted Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Integrated Circuits (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Structure Of Printed Boards (AREA)
JP2008077274A 2008-03-25 2008-03-25 光伝送機構を備えたモジュール基板およびその製造方法 Active JP5063430B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008077274A JP5063430B2 (ja) 2008-03-25 2008-03-25 光伝送機構を備えたモジュール基板およびその製造方法
US12/408,820 US8111954B2 (en) 2008-03-25 2009-03-23 Module substrate including optical transmission mechanism and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008077274A JP5063430B2 (ja) 2008-03-25 2008-03-25 光伝送機構を備えたモジュール基板およびその製造方法

Publications (3)

Publication Number Publication Date
JP2009229962A JP2009229962A (ja) 2009-10-08
JP2009229962A5 JP2009229962A5 (enExample) 2011-02-03
JP5063430B2 true JP5063430B2 (ja) 2012-10-31

Family

ID=41117358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008077274A Active JP5063430B2 (ja) 2008-03-25 2008-03-25 光伝送機構を備えたモジュール基板およびその製造方法

Country Status (2)

Country Link
US (1) US8111954B2 (enExample)
JP (1) JP5063430B2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9299661B2 (en) * 2009-03-24 2016-03-29 General Electric Company Integrated circuit package and method of making same
US20110156261A1 (en) * 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
US8866301B2 (en) 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
JP2015213124A (ja) * 2014-05-02 2015-11-26 イビデン株式会社 パッケージ基板
US9721812B2 (en) * 2015-11-20 2017-08-01 International Business Machines Corporation Optical device with precoated underfill
US10141623B2 (en) 2016-10-17 2018-11-27 International Business Machines Corporation Multi-layer printed circuit board having first and second coaxial vias coupled to a core of a dielectric waveguide disposed in the circuit board
JP6810346B2 (ja) * 2016-12-07 2021-01-06 富士通株式会社 発光素子接合基板
US10914895B2 (en) * 2018-09-18 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
JP7176401B2 (ja) * 2018-12-25 2022-11-22 富士通株式会社 光デバイス及び光モジュール
US11635566B2 (en) 2019-11-27 2023-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of forming same
DE102020115377B4 (de) 2019-11-27 2026-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Package und verfahren zu dessen herstellung
US20220404568A1 (en) * 2021-06-17 2022-12-22 Intel Corporation Package with optical waveguide in a glass core

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4227471B2 (ja) 2002-06-28 2009-02-18 パナソニック株式会社 受発光素子内蔵光電気混載配線モジュールの製造方法
TWI294262B (en) * 2002-06-28 2008-03-01 Matsushita Electric Industrial Co Ltd A light reception/emission device built-in module with optical and electrical wiring combined therein and method of making the same
JP2004069798A (ja) * 2002-08-02 2004-03-04 Canon Inc 光電融合ビアをもつ光電融合配線基板
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
JP2005005505A (ja) * 2003-06-12 2005-01-06 Denso Corp 多層配線基板及びその製造方法
AT413891B (de) * 2003-12-29 2006-07-15 Austria Tech & System Tech Leiterplattenelement mit wenigstens einem licht-wellenleiter sowie verfahren zur herstellung eines solchen leiterplattenelements
JP4276143B2 (ja) 2004-07-23 2009-06-10 新光電気工業株式会社 光モジュールの製造方法
JP4760128B2 (ja) * 2005-05-20 2011-08-31 住友ベークライト株式会社 光導波路構造体および光導波路基板
KR100770853B1 (ko) * 2006-02-09 2007-10-26 삼성전자주식회사 광 모듈
US8014638B2 (en) * 2006-04-03 2011-09-06 The University Of Tokyo Signal transmission device
AT505834B1 (de) * 2007-09-21 2009-09-15 Austria Tech & System Tech Leiterplattenelement

Also Published As

Publication number Publication date
US20090245724A1 (en) 2009-10-01
US8111954B2 (en) 2012-02-07
JP2009229962A (ja) 2009-10-08

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