JP5063430B2 - 光伝送機構を備えたモジュール基板およびその製造方法 - Google Patents

光伝送機構を備えたモジュール基板およびその製造方法 Download PDF

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Publication number
JP5063430B2
JP5063430B2 JP2008077274A JP2008077274A JP5063430B2 JP 5063430 B2 JP5063430 B2 JP 5063430B2 JP 2008077274 A JP2008077274 A JP 2008077274A JP 2008077274 A JP2008077274 A JP 2008077274A JP 5063430 B2 JP5063430 B2 JP 5063430B2
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Japan
Prior art keywords
optical transmission
component
transmission mechanism
module substrate
optical
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JP2008077274A
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English (en)
Japanese (ja)
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JP2009229962A (ja
JP2009229962A5 (enExample
Inventor
直幸 小泉
淳 大井
昭彦 立岩
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2008077274A priority Critical patent/JP5063430B2/ja
Priority to US12/408,820 priority patent/US8111954B2/en
Publication of JP2009229962A publication Critical patent/JP2009229962A/ja
Publication of JP2009229962A5 publication Critical patent/JP2009229962A5/ja
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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Optical Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
JP2008077274A 2008-03-25 2008-03-25 光伝送機構を備えたモジュール基板およびその製造方法 Active JP5063430B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008077274A JP5063430B2 (ja) 2008-03-25 2008-03-25 光伝送機構を備えたモジュール基板およびその製造方法
US12/408,820 US8111954B2 (en) 2008-03-25 2009-03-23 Module substrate including optical transmission mechanism and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008077274A JP5063430B2 (ja) 2008-03-25 2008-03-25 光伝送機構を備えたモジュール基板およびその製造方法

Publications (3)

Publication Number Publication Date
JP2009229962A JP2009229962A (ja) 2009-10-08
JP2009229962A5 JP2009229962A5 (enExample) 2011-02-03
JP5063430B2 true JP5063430B2 (ja) 2012-10-31

Family

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Family Applications (1)

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JP2008077274A Active JP5063430B2 (ja) 2008-03-25 2008-03-25 光伝送機構を備えたモジュール基板およびその製造方法

Country Status (2)

Country Link
US (1) US8111954B2 (enExample)
JP (1) JP5063430B2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9299661B2 (en) * 2009-03-24 2016-03-29 General Electric Company Integrated circuit package and method of making same
US20110156261A1 (en) * 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
US8866301B2 (en) 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
JP2015213124A (ja) * 2014-05-02 2015-11-26 イビデン株式会社 パッケージ基板
US9721812B2 (en) * 2015-11-20 2017-08-01 International Business Machines Corporation Optical device with precoated underfill
US10141623B2 (en) 2016-10-17 2018-11-27 International Business Machines Corporation Multi-layer printed circuit board having first and second coaxial vias coupled to a core of a dielectric waveguide disposed in the circuit board
JP6810346B2 (ja) * 2016-12-07 2021-01-06 富士通株式会社 発光素子接合基板
US10914895B2 (en) * 2018-09-18 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
JP7176401B2 (ja) * 2018-12-25 2022-11-22 富士通株式会社 光デバイス及び光モジュール
US11635566B2 (en) * 2019-11-27 2023-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of forming same
DE102020115377A1 (de) 2019-11-27 2021-05-27 Taiwan Semiconductor Manufacturing Co., Ltd. Package und verfahren zu dessen herstellung
US20220404568A1 (en) * 2021-06-17 2022-12-22 Intel Corporation Package with optical waveguide in a glass core

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI294262B (en) * 2002-06-28 2008-03-01 Matsushita Electric Industrial Co Ltd A light reception/emission device built-in module with optical and electrical wiring combined therein and method of making the same
JP4227471B2 (ja) 2002-06-28 2009-02-18 パナソニック株式会社 受発光素子内蔵光電気混載配線モジュールの製造方法
JP2004069798A (ja) * 2002-08-02 2004-03-04 Canon Inc 光電融合ビアをもつ光電融合配線基板
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
JP2005005505A (ja) * 2003-06-12 2005-01-06 Denso Corp 多層配線基板及びその製造方法
AT413891B (de) * 2003-12-29 2006-07-15 Austria Tech & System Tech Leiterplattenelement mit wenigstens einem licht-wellenleiter sowie verfahren zur herstellung eines solchen leiterplattenelements
JP4276143B2 (ja) 2004-07-23 2009-06-10 新光電気工業株式会社 光モジュールの製造方法
JP4760128B2 (ja) * 2005-05-20 2011-08-31 住友ベークライト株式会社 光導波路構造体および光導波路基板
KR100770853B1 (ko) * 2006-02-09 2007-10-26 삼성전자주식회사 광 모듈
JP4876263B2 (ja) * 2006-04-03 2012-02-15 国立大学法人 東京大学 信号伝送機器
AT505834B1 (de) * 2007-09-21 2009-09-15 Austria Tech & System Tech Leiterplattenelement

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Publication number Publication date
JP2009229962A (ja) 2009-10-08
US8111954B2 (en) 2012-02-07
US20090245724A1 (en) 2009-10-01

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