JP5050069B2 - 再構成可能なプログラマブルロジックデバイスコンピュータシステム - Google Patents
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- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Description
Claims (8)
- 複数の機能を有する所与のアプリケーションを実行させるためにコンピュータの能力を向上させるように、前記所与のアプリケーションの前記複数の機能に配分されるように動作可能な複数のプログラマブルロジックリソースを含む前記コンピュータ内のリソースを管理する方法であって、
前記所与のアプリケーションの前記複数の機能のうちの所与の機能を実行するために配分されるように利用可能なプログラマブルロジックリソースが充分に在るかどうかを判定するために仮想コンピュータオペレーティングシステムを使用することと、
ランタイム中における前記所与のアプリケーションの性能を計測するとともに計測された性能を規定の性能要件と比較するために前記仮想コンピュータオペレーティングシステムを使用することと、
前記計測された性能と前記規定の性能要件との比較に基づいて前記所与のアプリケーションの前記複数の機能に前記複数のプログラマブルロジックリソースを配分するために前記仮想コンピュータオペレーティングシステムを使用することと、
前記計測された性能と前記規定の性能要件との比較に基づいて前記所与のアプリケーションの前記複数の機能のうちの前記所与の機能に対してハードウェア手段を使用するかまたはソフトウェア手段を使用するかを決定するために前記仮想コンピュータオペレーティングシステムを使用することと
を含む、方法。 - 前記コンピュータは、少なくとも1つのプログラマブルロジックデバイス上で実行される中央プロセッシングユニットと前記中央プロセッシングユニットに結合されたプログラマブルロジックとを備え、プログラマブルロジックは、前記所与のアプリケーションを処理するために前記コンピュータの能力を向上させるように、前記所与のアプリケーションの前記複数の機能に配分されるように動作可能である、請求項1に記載の方法。
- 前記コンピュータは、マイクロプロセッサ上で実行される中央プロセッシングユニットと前記中央プロセッシングユニットに結合されたプログラマブルロジックとを備え、プログラマブルロジックは、前記所与のアプリケーションを処理するために前記コンピュータの能力を向上させるように、前記所与のアプリケーションの前記複数の機能に配分されるように動作可能である、請求項1に記載の方法。
- 前記コンピュータは、部分的にマイクロプロセッサ上で実行されるとともに部分的にプログラマブルロジックデバイス上で実行される中央プロセッシングユニットと前記中央プロセッシングユニットに結合されたプログラマブルロジックとを備え、プログラマブルロジックは、前記所与のアプリケーションを処理するために前記コンピュータの能力を向上させるように、前記所与のアプリケーションの前記複数の機能に配分されるように動作可能である、請求項1に記載の方法。
- 前記所与のアプリケーションが前記複数の機能を含み、前記方法は、前記複数のプログラマブルロジックリソースのうちの単一のプログラマブルロジックリソースを前記所与のアプリケーションの前記複数の機能のうちの前記所与の機能を構成する複数のブロックの構成データに配分することをさらに含む、請求項1に記載の方法。
- 前記所与のアプリケーションが前記複数の機能を含み、前記方法は、前記複数のプログラマブルロジックリソースのうちの単一のプログラマブルロジックリソースを前記所与のアプリケーションの前記複数の機能のうちの前記所与の機能を構成する単一のブロックの構成データに配分することをさらに含む、請求項1に記載の方法。
- 複数の機能を有する所与のアプリケーションを実行させるためにコンピュータの能力を向上させるように、前記所与のアプリケーションの前記複数の機能に配分されるように動作可能な複数のプログラマブルロジックリソースを含む前記コンピュータ内のリソースを管理する方法であって、
前記所与のアプリケーションの前記複数の機能のうちの所与の機能を実行するために配分されるように利用可能なプログラマブルロジックリソースが充分に在るかどうかを判定するために仮想コンピュータオペレーティングシステムを使用することと、
ランタイム中における前記所与のアプリケーションの性能を計測するとともに計測された性能を規定の性能要件と比較するために前記仮想コンピュータオペレーティングシステムを使用することと、
ランタイム中に、前記計測された性能と前記規定の性能要件との比較に基づいて、前記所与のアプリケーションの前記複数の機能のうちの前記所与の機能に対してハードウェア手段を使用するかまたはソフトウェア手段を使用するかを決定するために前記仮想コンピュータオペレーティングシステムを使用することと
を含む、方法。 - 前記所与のアプリケーションの前記複数の機能の中の、前記プログラマブルロジックリソースをタイムマルチプレクシングすることをさらに含む、請求項7に記載の方法。
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JP2010059968A Expired - Fee Related JP5050069B2 (ja) | 1998-11-20 | 2010-03-16 | 再構成可能なプログラマブルロジックデバイスコンピュータシステム |
JP2011003508A Expired - Fee Related JP5509107B2 (ja) | 1998-11-20 | 2011-01-11 | 再構成可能なプログラマブルロジックデバイスコンピュータシステム |
JP2012163797A Pending JP2012252712A (ja) | 1998-11-20 | 2012-07-24 | 再構成可能なプログラマブルロジックデバイスコンピュータシステム |
JP2013246866A Pending JP2014059905A (ja) | 1998-11-20 | 2013-11-29 | 再構成可能なプログラマブルロジックデバイスコンピュータシステム |
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JP2012163797A Pending JP2012252712A (ja) | 1998-11-20 | 2012-07-24 | 再構成可能なプログラマブルロジックデバイスコンピュータシステム |
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EP (3) | EP1138001B1 (ja) |
JP (5) | JP2002530780A (ja) |
DE (1) | DE69910826T2 (ja) |
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DE69910826T2 (de) | 2004-06-17 |
DE69910826D1 (de) | 2003-10-02 |
JP2014059905A (ja) | 2014-04-03 |
US7171548B2 (en) | 2007-01-30 |
WO2000031652A3 (en) | 2000-12-28 |
EP1351154A2 (en) | 2003-10-08 |
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