JP5048972B2 - プログラマブル・デバイスの構成エラー検出の偽陽性の低減 - Google Patents

プログラマブル・デバイスの構成エラー検出の偽陽性の低減 Download PDF

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Publication number
JP5048972B2
JP5048972B2 JP2006159772A JP2006159772A JP5048972B2 JP 5048972 B2 JP5048972 B2 JP 5048972B2 JP 2006159772 A JP2006159772 A JP 2006159772A JP 2006159772 A JP2006159772 A JP 2006159772A JP 5048972 B2 JP5048972 B2 JP 5048972B2
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Japan
Prior art keywords
data
mask
error detection
memory
bits
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JP2006159772A
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Japanese (ja)
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JP2006344223A5 (enExample
JP2006344223A (ja
Inventor
デイビッド・ルイス
ロバート・ブレーク
リチャード・ジイ・クリフ
スリニバス・ティ・レディ
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Altera Corp
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Altera Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
JP2006159772A 2005-06-08 2006-06-08 プログラマブル・デバイスの構成エラー検出の偽陽性の低減 Expired - Fee Related JP5048972B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US68898005P 2005-06-08 2005-06-08
US60/688,980 2005-06-08
US11/407,519 2006-04-19
US11/407,519 US7620876B2 (en) 2005-06-08 2006-04-19 Reducing false positives in configuration error detection for programmable devices

Publications (3)

Publication Number Publication Date
JP2006344223A JP2006344223A (ja) 2006-12-21
JP2006344223A5 JP2006344223A5 (enExample) 2009-07-16
JP5048972B2 true JP5048972B2 (ja) 2012-10-17

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JP2006159772A Expired - Fee Related JP5048972B2 (ja) 2005-06-08 2006-06-08 プログラマブル・デバイスの構成エラー検出の偽陽性の低減

Country Status (4)

Country Link
US (1) US7620876B2 (enExample)
EP (1) EP1732083A1 (enExample)
JP (1) JP5048972B2 (enExample)
CN (1) CN1892611B (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8566616B1 (en) * 2004-09-10 2013-10-22 Altera Corporation Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like
US8612772B1 (en) 2004-09-10 2013-12-17 Altera Corporation Security core using soft key
US7596744B1 (en) * 2006-02-24 2009-09-29 Lattice Semiconductor Corporation Auto recovery from volatile soft error upsets (SEUs)
US7702978B2 (en) * 2006-04-21 2010-04-20 Altera Corporation Soft error location and sensitivity detection for programmable devices
US7844886B1 (en) * 2006-05-16 2010-11-30 Altera Corporation Parallel processing error detection and location circuitry for configuration random-access memory
US20080172659A1 (en) * 2007-01-17 2008-07-17 Microsoft Corporation Harmonizing a test file and test configuration in a revision control system
US8065574B1 (en) 2007-06-08 2011-11-22 Lattice Semiconductor Corporation Soft error detection logic testing systems and methods
JP5014899B2 (ja) * 2007-07-02 2012-08-29 ルネサスエレクトロニクス株式会社 再構成可能デバイス
US7865788B2 (en) * 2007-11-15 2011-01-04 Verigy (Singapore) Pte. Ltd. Dynamic mask memory for serial scan testing
US8656082B2 (en) * 2008-08-05 2014-02-18 Micron Technology, Inc. Flexible and expandable memory architectures
CN102169711A (zh) * 2010-02-25 2011-08-31 复旦大学 带电阻随机存储器模块的单芯片结构可编程逻辑器
US8522126B1 (en) 2010-12-22 2013-08-27 Lattice Semiconductor Corporation Blocking memory readback in a programmable logic device
US9230683B2 (en) 2012-04-25 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
KR20140120100A (ko) * 2013-04-02 2014-10-13 에스케이하이닉스 주식회사 수신회로를 포함하는 데이터전송시스템 및 데이터전송방법
US9658920B1 (en) * 2013-06-21 2017-05-23 Altera Corporation Method for reconfiguring an erroneous memory frame in an integrated circuit
US9529673B2 (en) * 2013-07-30 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device having adjustable refresh period and method of operating the same
JP2015201813A (ja) * 2014-04-10 2015-11-12 株式会社日立製作所 プログラマブルゲートアレイ
JP2016167669A (ja) * 2015-03-09 2016-09-15 富士通株式会社 プログラマブル論理回路装置及びそのエラー検出方法
JP6145482B2 (ja) * 2015-08-13 2017-06-14 富士通株式会社 伝送装置および故障検出方法
JP6717059B2 (ja) * 2016-06-06 2020-07-01 オムロン株式会社 制御システム
JP6880795B2 (ja) * 2017-02-08 2021-06-02 オムロン株式会社 制御装置およびその制御方法
JP6546213B2 (ja) 2017-04-13 2019-07-17 ファナック株式会社 回路構成最適化装置及び機械学習装置
JP6502998B2 (ja) 2017-04-13 2019-04-17 ファナック株式会社 回路構成最適化装置及び機械学習装置
US11562101B2 (en) * 2017-11-13 2023-01-24 Intel Corporation On-device bitstream validation
US10684913B2 (en) * 2018-04-25 2020-06-16 Dell Products L.P. Systems and methods for detecting errors and/or restoring non-volatile random access memory using error correction code
JP7427000B2 (ja) * 2018-08-08 2024-02-02 ヌマスカル エイエス デジタル回路試験及び分析モジュール、システム及びそれの方法
CN111984457B (zh) 2019-05-23 2022-09-02 华为技术有限公司 对存储信息更新的方法和装置
US11294804B2 (en) 2020-03-23 2022-04-05 International Business Machines Corporation Test case failure with root cause isolation

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4369511A (en) 1979-11-21 1983-01-18 Nippon Telegraph & Telephone Public Corp. Semiconductor memory test equipment
US4389511A (en) * 1981-12-04 1983-06-21 General Electric Company Blends of polyphenylene ether resins and styrene-tert-butylstyrene copolymers
JPH10146437A (ja) * 1996-11-18 1998-06-02 Sankyo Kk 遊技機
JPH11161559A (ja) * 1997-11-28 1999-06-18 Oki Electric Ind Co Ltd パリティチェック機能付き記憶装置
US6553523B1 (en) * 1999-08-13 2003-04-22 Jeffrey V. Lindholm System and method for verifying configuration of a programmable logic device
US6886116B1 (en) * 2001-07-26 2005-04-26 Emc Corporation Data storage system adapted to validate error detection logic used in such system
EP1438662A2 (en) * 2001-10-11 2004-07-21 Altera Corporation Error detection on programmable logic resources
US7257750B1 (en) * 2005-01-13 2007-08-14 Lattice Semiconductor Corporation Self-verification of configuration memory in programmable logic devices
JP2006221334A (ja) * 2005-02-09 2006-08-24 Tdk Corp メモリコントローラ、フラッシュメモリシステム及びフラッシュメモリの制御方法

Also Published As

Publication number Publication date
US20070011578A1 (en) 2007-01-11
US7620876B2 (en) 2009-11-17
CN1892611B (zh) 2010-07-14
EP1732083A1 (en) 2006-12-13
JP2006344223A (ja) 2006-12-21
CN1892611A (zh) 2007-01-10

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