JP5030047B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- JP5030047B2 JP5030047B2 JP2006132221A JP2006132221A JP5030047B2 JP 5030047 B2 JP5030047 B2 JP 5030047B2 JP 2006132221 A JP2006132221 A JP 2006132221A JP 2006132221 A JP2006132221 A JP 2006132221A JP 5030047 B2 JP5030047 B2 JP 5030047B2
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- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 150000004767 nitrides Chemical class 0.000 claims description 31
- 239000010410 layer Substances 0.000 claims description 27
- 239000011229 interlayer Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910019044 CoSix Inorganic materials 0.000 claims description 4
- 229910004166 TaN Inorganic materials 0.000 claims description 4
- 229910008486 TiSix Inorganic materials 0.000 claims description 4
- 229910008764 WNx Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 229910020286 SiOxNy Inorganic materials 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 125000006850 spacer group Chemical class 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
102:第1酸化膜
104:第1窒化膜
106:第2酸化膜
108:第2窒化膜
110:フォトレジストパターン
112:層間絶縁膜
114:第3酸化膜
116:第1導電層
116A:第1ゲート電極
116B:第2ゲート電極
118:ゲート酸化膜
120:第2導電層
120A:第3ゲート電極
122:第3導電層
122A:第4ゲート電極
124:スペーサ
200:ホール
300:ソース及びドレイン
Claims (4)
- 半導体基板の上部に第1酸化膜、第1窒化膜および第2酸化膜を形成する段階と、
上記第2酸化膜の上部に窒化膜パターンを形成する段階と、
上記窒化膜パターンの両側に露出した前記第2酸化膜を除去する段階と、
上記窒化膜パターンの両側に露出した前記第1窒化膜の上部に層間絶縁膜を形成する段階と、
上記窒化膜パターンを除去し、これによって上記層間絶縁膜は側壁が露出される段階と、
上記第2酸化膜を除去する段階と、
上記層間絶縁膜と前記第1窒化膜を含む全体構造の表面に沿って第3酸化膜を形成し、上記第1酸化膜と上記第1窒化膜と上記第3酸化膜とが積層された誘電体膜が形成される段階と、
上記誘電体膜を含む全体構造の上部に第1導電層を形成した後、全面エッチングして上記誘電体膜によって上記半導体基板と絶縁される第1および第2ゲート電極を、上記層間絶縁膜の側壁に形成する段階と、
上記第1および第2ゲート電極の間に露出した上記誘電体膜を除去し、上記第1および第2ゲート電極によって入口がポジティブスロープを有するホールが形成される段階と、
上記誘電体膜が除去され、露出された上記半導体基板を含む全体構造の表面に沿ってゲート酸化膜を形成する段階と、
上記ゲート酸化膜を含む全体構造の上部に第2導電層を形成した後、全面エッチングして上記ゲート酸化膜により上記半導体基板、上記第1および第2ゲート電極と絶縁される第3ゲート電極を上記ホール内に形成する段階と、
上記第3ゲート電極を含む全体構造の上部に第3導電層を形成した後、全面エッチングして上記第1、第2および第3ゲート電極と連結される第4ゲート電極を上記ホール内に形成する段階と、
上記層間絶縁膜を除去した後、上記半導体基板の所定領域にソースおよびドレインを形成する段階と、
を有する半導体素子の製造方法。 - 上記層間絶縁膜は、酸化膜またはSiOxNyの物質で形成される請求項1に記載の半導体素子の製造方法。
- 上記第1導電層は、埋め込む領域の幅の1/5〜1/2の厚さで蒸着する請求項1に記載の半導体素子の製造方法。
- 上記第1、第2、第3及び第4ゲート電極はドーピングされたポリシリコン膜を用いるか、またはAl、W、WSix、CoSix、WNx、TiSix、Ti、Ta、TaN、Ru、Ptを用いるか、またはこれを混合して用いる請求項1に記載の半導体素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2005-0111327 | 2005-11-21 | ||
KR1020050111327A KR100687402B1 (ko) | 2005-11-21 | 2005-11-21 | 반도체 소자 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007142358A JP2007142358A (ja) | 2007-06-07 |
JP5030047B2 true JP5030047B2 (ja) | 2012-09-19 |
Family
ID=38054090
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006132221A Expired - Fee Related JP5030047B2 (ja) | 2005-11-21 | 2006-05-11 | 半導体素子の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7348239B2 (ja) |
JP (1) | JP5030047B2 (ja) |
KR (1) | KR100687402B1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7682905B2 (en) | 2007-05-09 | 2010-03-23 | Spansion Llc | Self aligned narrow storage elements for advanced memory device |
KR101033402B1 (ko) | 2008-11-06 | 2011-05-09 | 주식회사 동부하이텍 | 플래시 메모리 소자 및 그 제조 방법 |
US8217456B1 (en) * | 2011-03-11 | 2012-07-10 | International Business Machines Corporation | Low capacitance hi-K dual work function metal gate body-contacted field effect transistor |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6093945A (en) * | 1998-07-09 | 2000-07-25 | Windbond Electronics Corp. | Split gate flash memory with minimum over-erase problem |
JP4904631B2 (ja) * | 2000-10-27 | 2012-03-28 | ソニー株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
US6670240B2 (en) * | 2001-08-13 | 2003-12-30 | Halo Lsi, Inc. | Twin NAND device structure, array operations and fabrication method |
TW573344B (en) * | 2002-05-24 | 2004-01-21 | Nanya Technology Corp | Separated gate flash memory and its manufacturing method |
KR100537276B1 (ko) | 2002-11-18 | 2005-12-19 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100480645B1 (ko) * | 2003-04-01 | 2005-03-31 | 삼성전자주식회사 | 역자기 정합 방식을 이용한 트윈―ono 형태의sonos 메모리 소자 제조 방법 |
US7129539B2 (en) * | 2003-05-15 | 2006-10-31 | Sharp Kabushiki Kaisha | Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card |
KR100546401B1 (ko) * | 2003-12-17 | 2006-01-26 | 삼성전자주식회사 | 자기정렬된 전하트랩층을 포함하는 반도체 메모리 소자 및그 제조방법 |
-
2005
- 2005-11-21 KR KR1020050111327A patent/KR100687402B1/ko not_active IP Right Cessation
-
2006
- 2006-05-11 JP JP2006132221A patent/JP5030047B2/ja not_active Expired - Fee Related
- 2006-06-16 US US11/454,587 patent/US7348239B2/en active Active
-
2008
- 2008-01-28 US US12/021,018 patent/US20080116531A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2007142358A (ja) | 2007-06-07 |
US7348239B2 (en) | 2008-03-25 |
US20080116531A1 (en) | 2008-05-22 |
US20070117316A1 (en) | 2007-05-24 |
KR100687402B1 (ko) | 2007-02-26 |
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