JP5026578B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, a swivel type gaming machine, an arrangement ball machine, or a sparrow ball gaming machine, and more particularly to a gaming machine that has excellent recyclability and is less likely to be illegally modified.

  Among popular entertainment devices, pachinko machines and the like are widely popular as those that can acquire premiums that are more than invested for good luck. In this pachinko machine, various characters appear on a liquid crystal screen or the like, and the game progresses.

  In general, players who enjoy such a gaming machine tend to always desire new game characteristics, and therefore, new game machines are introduced one after another in the game hall to meet the expectations of the players. For this reason, gaming machines such as pachinko machines are actually removed from the gaming hall in a relatively short period of time regardless of their durable years.

  Therefore, how to dispose of gaming machines removed from game halls is a major issue, and considering that it costs considerable to dispose of or incinerate, it is not expected that all game halls will be treated appropriately. Can not. Therefore, as a gaming machine manufacturer, it is necessary to tackle the problem of recycling of gaming machines from the front, and it is necessary to construct a reliable recycling system and complete equipment that can be easily recycled in terms of equipment design. That is, the circuit design should include many parts that can be used for general purposes in consideration of recyclability while providing new models with different game characteristics one after another in response to the player's request. However, it should not be a game machine that can be easily tampered with in order to pursue recyclability.

  The present invention has been made in view of such points, and it is an object of the present invention to provide a gaming machine that not only has many parts that can be used for general purposes but has excellent recyclability, and is also difficult to tamper with.

In order to solve the above-described problems, the present invention performs a lottery to alternatively generate a first state that is advantageous to the player and a disadvantageous second state with respect to a game, and a game operation based on the lottery result In a gaming machine that controls the first board , a memory that stores a control program that realizes a control operation, a first board that includes a CPU that executes the control program , and an operation permission level selection signal at the control terminal. An input circuit that outputs parallel data, and a second board having an output circuit that obtains and outputs parallel data from the first board when receiving an operation permission level selection signal at the control terminal is provided on the first board. The control board is configured to be connected by the first connector and the second connector of the second board, and the number of connector terminals for selection signals of the first connector and the second connector is determined by sending a selection signal to the control terminal. Only all of the input circuit and output circuit operating, respectively, exceeds the number capable of transmitting a selection signal.

Since the control board of the present invention is composed of a plurality of boards of the first board and the second board, if a control program is rewritten, a new gaming machine can be realized without changing the circuit configuration of the first board. it can. That is, since the first substrate can be used regardless of the model change, it can be recycled.

Preferably, the resistance value of the fixed resistor constituting the protection element is set to a minimum value corresponding to the maximum rated current of the circuit element on the first substrate side connected to the fixed resistor . In this case, the element on the first substrate side is not damaged even if the program on the first substrate side goes out of control.

N gate circuits are mounted on the first substrate, and N output signals of the address decoder are respectively supplied to one side input terminals of the N gate circuits, while the other side inputs of all the gate circuits. A write control signal output by the CPU is commonly supplied to the terminals, and an operation permission level selection signal among N different output signals of the address decoder based on the write control signal output during the data write operation of the CPU. However, it is preferable to be configured so as to be supplied to the control terminal of the output circuit of the second substrate via the gate circuit that receives this .

  As described above, according to the present invention, it is possible to realize a gaming machine that is improved so as to include many portions that can be used for general purposes and that is difficult to tamper with.

1 is an overall configuration diagram of a pachinko machine according to an embodiment. It is a block diagram which shows the circuit structure of a main control board. It is a block diagram which shows the circuit structure of a main control board in more detail.

  Hereinafter, the present invention will be described in more detail based on examples. FIG. 1 is a circuit configuration diagram showing a control system of a pachinko machine according to the present embodiment. This pachinko machine has a main control board 1 consisting of two boards, a symbol control board 2, a voice control board 3, a lamp control board 4, and a payout control board 5 as the main components. The computer circuit includes a CPU, a ROM, and a RAM. The main control board 1 is composed of a first board 1a and a second board 1b, and is a part that centrally controls gaming operations. The other control boards 2 to 5 are configured to receive a control command from the main control board 1 (specifically, the second board 1b) to realize a predetermined game operation.

  The symbol control board 2 is a board that drives the LCD monitor 8. For example, when a game ball enters the winning opening, the screen contents of the LCD monitor 8 are variably displayed according to the control command from the main control board 1. ing. The sound control board 3 and the lamp control board 4 realize an operation for exciting a game operation in a sound or visual manner in accordance with a control command from the main control board 1.

  The payout control board 5 operates in accordance with a control command from the main control board 1, but receives a switch input such as a prize ball counting switch to realize a predetermined number of prize balls. The payout control board 5 also receives information from a replenishment detection switch, a lower tray switch, a ball lending count switch, and the like. Further, the payout control board 5 outputs a command signal (launch permission signal) to the launch board 7, and the launch control board 7 plays a function of launching a game ball in response to the player's operation. . In FIG. 1, a power supply board 6 is a part that receives AC 24V and supplies a DC voltage to each part of the apparatus.

  FIG. 2 illustrates the internal configuration of the main control board 1. As shown in the figure, the main control board 1 is configured by connecting a first board 1a and a second board 1b by connectors CN1 and CN2 and a cable CBL. The first board 1a receives a DC voltage from the power board 6 and supplies it to each part. The first board 1a receives a power reset signal, a power failure signal, etc. from the power board 6 and receives a CPU reset signal or NMI (Non The reset circuit unit 11 generates a maskable interrupt signal, the CPU circuit unit 12 includes a CPU, ROM, RAM, and other ICs, and the decode circuit unit 13 decodes an address signal to generate a chip select signal CS. ing.

  In addition to the function of transmitting the control command received from the first board 1a to the control boards 2 to 5, the second board 1b sends a switch signal from a winning opening or tulip arranged on the game board to the first board 1a. Plays a function to tell. Therefore, the second board 1b receives input from the output port circuit unit 14 for outputting control data from the first board 1a to the other control boards 2 to 5, and data from various game components arranged on the game board. The port circuit unit 15 includes an output drive circuit unit 16 that is an interface unit for output drive, and a switch input circuit unit 17 that is an input interface unit with switches.

  FIG. 3 illustrates the output section of the decode circuit section 13 and the input section of the second substrate 1b. The first substrate 1a is terminated with a connector CN1 through address decoders 20 and 21 and a number of OR gates G1... G1. The address decoders 20 and 21 are, for example, HD74HC138P (3-8 line decoder), and the lower 3 bits AB0 to AB2 of the CPU address bus are connected to the selection input terminal ABC. Further, the chip select signal CS generated by the first substrate 1a is supplied to the enable terminal G2B.

  The inputs to the enable terminals G1 and G2A are different between the two ICs. The address decoder 20 is supplied with address signals AB3 and AB4 and the address decoder 21 is supplied with address signals AB4 and AB3. Has been. Accordingly, when the voltage level of the lower 5 bits of the address bus is LHLLL to LHHHH, the decoder 20 functions and the corresponding bits of Y0 to Y7 become L level. On the other hand, when the voltage level of the lower 5 bits of the address bus is HLLLLL to HLHHH, the decoder 21 functions and the corresponding bits of Y0 to Y7 become L level.

The output signals of the address decoders 20 and 21 are used as chip select signals in the second substrate 1b, but some of the chip select signals CS _{0 to} CS _n-1 are supplied to the OR gate G1 together with the XWR signal, and the OR gate The output of G1 is supplied to the connector CN1 as chip select signals CS _{0 to} CS _n-1 for output ports.

In this embodiment, the number of chip select signals actually required in the second substrate 1b is less than N. However, since the first substrate 1a is used for general purposes by rewriting the control program, the maximum number is intentionally set. Chip select signals CS _{0 to} CS _n-1 are output. Since the XWR signal is a signal indicating that the data bus is in a write cycle, the chip select signals CS _{0 to} CS _n-1 in the connector CN1 are those for which the CPU executes a data output command (OUT command) or the like. It will change to L level according to.

The remaining chip select signals CS _{n to} CS _m generated by the address decoders 20 and 21 are supplied directly to the connector CN1 as chip select signals for input ports in the second substrate 1b. Not all of the chip select signals CS _{n to} CS _m are used on the second substrate 1b, but the first substrate 1a is used for general purposes by rewriting the control program. Chip select signals CS _{n to} CS _m are output.

  Note that a data bus (not shown) is connected to the connector CN1 so that 8-bit data can be exchanged with the second substrate 1b. An RD signal is also output to the connector CN1 in order to activate the bus buffer 23 in accordance with the CPU executing a data input command (IN command) or the like.

The second substrate 1b is provided with a number of D-type flip-flops 22 ... 22 as output ports, and a number of bus buffers 23 ... 23 as input ports. The D-type flip-flop 22 is, for example, an HD74HC273P, receives a signal on the data bus at the D input terminals D8-D1, and receives a chip select signal for the output port generated at the first substrate 1a at the clock terminal CK. Receives CS _i . Here, the D-type flip-flop 22 reads the data of the D input terminals D8 to D1 when the signal of the clock terminal CK rises, but the chip select signal CS _i falls in accordance with the execution of the OUT instruction or the like by the CPU. Therefore, the data output from the first substrate 1a is read into the D-type flip-flop 22 in accordance with this timing.

The bus buffer 23 is, for example, a TC74HC541AP. The bus buffer 23 outputs the data of the YA8-YA1 input terminal to the Y8-Y1 output terminal when both of the G1 and G2 input terminals become L level. Then, the G1 input terminal, through the connector CN2, CN1, the chip select signal CS _j for the input ports are supplied. The RD signal is supplied to the G2 terminal from the first substrate 1a through the connectors CN2 and CN1. Accordingly, since the CPU becomes L level, both the chip select signal CS _j falling G1, G2 input terminal to fit to perform the IN instruction, at this timing, that the output value of the bus buffer 23 changes Become. Since a connection cable connected to the data bus exists between the connectors CN2 and CN1, the output of the bus buffer 23 is read by the CPU.

The data input / output operation is performed as described above. This embodiment is also characterized by a method of terminating unused terminals. As described above, in this embodiment, even if the circuit configuration of the second board 1b is changed according to the model of the pachinko machine, the first board 1a is used for general purposes. CS _{0 to} CS _n-1 and CS _{n to} CS _m are output.

  For this reason, an unused chip select signal may be generated. However, all the terminals corresponding to the unused chip select signal are dropped to the ground via the protective resistor r on the second substrate side 1b. Yes. Here, the value of the protective resistor r is a value that is not more than the maximum rated current even when an H level voltage is output from the corresponding element (in this example, the OR gate G1 or the decoder 21) on the first substrate 1a side. Is set to Therefore, even if the CPU runs out of control on the first substrate side 1a and an H level voltage is output from the OR gate G1 or the decoder 21, these ICs are not damaged.

  Further, it is preferable to select a minimum value as the resistance value of the protective resistor so that only a voltage equal to or lower than the threshold level can always be output. If a current limiting element or circuit is incorporated in the corresponding element on the first substrate 1a side, all the terminals corresponding to unused chip select signals are connected to the ground without using the protective resistor r. Direct connection is preferred.

  In this way, in this embodiment, since the terminal corresponding to the unused chip select signal is connected to the ground directly or through the minimum protective resistance, the gaming machine is illegally used using the unused chip select signal. It cannot be used to get an unfair prize ball. For example, when the terminal corresponding to the unused chip select signal is open or pulled up, the illegal modification program is executed on the first board 1a and the chip select signal that should be unused is connected to the connector. Although it is possible to receive a fraud command from the CN 2 with another fraudulent board and send it to the payout control board 5, such illegal actions are virtually impossible in the configuration of this embodiment. That is, the terminal corresponding to the unused chip select signal is grounded directly or through a minimum protection resistor, and an H level signal cannot be output. Therefore, the protection resistor is left in the form of leaving a scratch on the second substrate. Unless excluded, illegal activities such as those described above cannot be realized.

  As mentioned above, although the Example of this invention was described, the concrete content of an explanation is not the meaning which limits this invention in particular. For example, the circuit configuration of the first substrate can be changed as appropriate, and the CPU circuit unit may be composed of a plurality of ICs or a one-chip microcomputer. Further, although the chip select signal has been described in the embodiment, it is preferable that other unused signals transmitted between the first board and the second board are similarly terminated. Although a D-type flip-flop is illustrated as an output port and a bus buffer is illustrated as an input port, it is needless to say that other circuit configurations may be adopted.

1 Main control circuit (main circuit board)
2 Sub-control circuit 1a First substrate 1b Second substrate

Claims (6)

In a gaming machine that performs a lottery to alternatively generate a first state that is advantageous to a player and an unfavorable second state with respect to a game, and controls a game operation based on the lottery result,
A memory for storing a control program for realizing a control operation , and a first substrate including a CPU for executing the control program ;
When an operation permission level selection signal is received at the control terminal, an input circuit that outputs parallel data to the first board, and when an operation permission level selection signal is received at the control terminal, the parallel data is acquired from the first board and output. A second board on which an output circuit is mounted,
A control board configured to be connected by the first connector of the first board and the second connector of the second board;
The number of connector terminals for the selection signal of the first connector and the second connector exceeds the number that can transmit the selection signal to all of the input circuit and the output circuit that operate by receiving the selection signal at the control terminal. A gaming machine characterized by that. The gaming machine according to claim 1, wherein the connector terminal of the second connector corresponding to the unused selection signal is connected to the ground of the second board directly or through a protective element . The gaming machine according to claim 2, wherein the resistance value of the fixed resistor constituting the protective element is set to a minimum value corresponding to the maximum rated current of the circuit element on the first substrate side connected to the fixed resistor . The output circuit includes eight flip-flops,
The control command is acquired from the first board on condition that an operation permission level selection signal is received at the control terminal, and the control command is output to another control board. The gaming machine described . N gate circuits are mounted on the first substrate, and N output signals of the address decoder are respectively supplied to one side input terminals of the N gate circuits, while the other side inputs of all the gate circuits. The terminal is commonly supplied with a write control signal output by the CPU,
Based on the write control signal output during the data write operation of the CPU, the output signal of the second substrate passes through the gate circuit that receives the selection signal of the operation permission level among the N output signals different from the address decoder. The gaming machine according to claim 1, wherein the gaming machine is configured to be supplied to a control terminal . The read control signal output from the CPU for the data read operation of the CPU is supplied to the control terminal of the input circuit of the second board via the first connector and the second connector . The gaming machine described in 1.

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