JP5016060B2 - 位相ロック・ループ内のジッターを決定するためのオンチップ位相誤差計測のための装置。 - Google Patents
位相ロック・ループ内のジッターを決定するためのオンチップ位相誤差計測のための装置。 Download PDFInfo
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- JP5016060B2 JP5016060B2 JP2009545638A JP2009545638A JP5016060B2 JP 5016060 B2 JP5016060 B2 JP 5016060B2 JP 2009545638 A JP2009545638 A JP 2009545638A JP 2009545638 A JP2009545638 A JP 2009545638A JP 5016060 B2 JP5016060 B2 JP 5016060B2
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- 238000005259 measurement Methods 0.000 title description 15
- 230000008859 change Effects 0.000 claims description 24
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
- G01R31/31709—Jitter measurements; Jitter generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/26—Measuring noise figure; Measuring signal-to-noise ratio
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Description
12:フィードバック・クロック
14:位相・周波数検出器(PFD)
16:電荷ポンプ(CP)
18:ループ・フィルター(LPF)
20:電圧制御発信器(VCO)
22:分周器(DIV)
24:ロック検出器(LD)
100:位相ロック・ループ(PLL)
102、200、300:瞬時位相誤差検出器(IPED)
104:パターン分析器システム
106:閾値
108:点線(複数閾値)
111、112,113:時間ステップ
120、302:XORゲート
122、202、702:遅延ライン
124,304:D型フリップフロップ(DFF)ラッチ
126:ANDゲート
(1)、(2):パルス
(3):クロック入力
400:システム
402、804:マルチプレクサ
404:カウンタ
406:タイマー回路
500、600、700、800:回路
502:アキュムレータ
602:ライン・イネーブル・カウンタ(LE_CNT)
604:カウンタ
606:遅延回路
608:NANDゲート
610:較正処理システム
612:時間窓
614:DLY_TUNE<0:k>(信号入力の付加的なセット)
618:リング発信器
802:遅延ステージ
806:位相検出器
810:入力クロック
Claims (9)
- 位相誤差信号を出力するように構成された位相・周波数検出器(14)を含む位相ロック・ループPLL(100)回路と、
前記位相誤差信号を論理的に結合し、該論理的に結合された位相誤差信号のパルス幅を各基準クロック・サイクルにおいてプログラム可能な遅延時間と比較して、差分信号及び未処理信号を含む瞬時位相誤差変化を決定することにより、ピーク瞬時位相誤差を決定するように構成された位相誤差モニター回路(200、300)と、
前記差分信号及び前記未処理信号を入力として受信し、そのうちの1つを選択するように構成されたマルチプレクサ(402)と、
前記マルチプレクサの出力に結合され、時間窓に関連する瞬時位相誤差変化カウントを蓄積するアキュムレータ(502)と
を備える装置。 - 前記アキュムレータに結合され、前記瞬時位相誤差変化の情報のパターンを決定してロック検出をもたらすパターン分析器(104)をさらに備える、請求項1に記載の装置。
- 前記アキュムレータに結合され、前記瞬時位相誤差変化の情報のパターンを決定して静的位相オフセット・モニタリングをもたらすパターン分析器(104)をさらに備える、請求項1に記載の装置。
- 前記基準クロックに基づいて時間窓を画定するタイマー(406)をさらに備える、請求項1に記載の装置。
- 前記論理的に結合された位相誤差信号の前記パルス幅が、各基準クロック・サイクルにおいて前記プログラム可能な遅延時間を越えた場合に第1の瞬時位相誤差変化信号が供給され、そうでない場合に第2の瞬時位相誤差変化信号が供給される、請求項1に記載の装置。
- 位相誤差信号を出力するように構成された位相・周波数検出器(14)を含む位相ロック・ループPLL(100)回路と、
前記位相誤差信号を論理的に結合し、該論理的に結合された位相誤差信号のパルス幅を各基準クロック・サイクルにおいてプログラム可能な遅延時間と比較して、第1の信号及び差分信号を含む瞬時位相誤差変化を決定することによってピーク瞬時位相誤差を決定するように構成された位相誤差モニター回路(200、300)と、
前記第1の信号及び前記差分信号を入力として受信し、そのうちの1つを選択するように構成されたマルチプレクサ(402)と、
前記マルチプレクサの出力に結合され、複数の瞬時位相誤差閾値に関連する瞬時位相誤差変化カウントを、位相誤差振幅及び時間が与えられてジッター・ヒストグラムが作成されるように、蓄積するための複数のカウンタ(404)とを備える装置。 - 前記基準クロックに基づいて、前記カウンタに対する時間窓を画定するタイマー(406)をさらに備える、請求項6に記載の装置。
- 前記第1の信号は、前記論理的に結合された位相誤差信号の前記パルス幅が、各基準クロック・サイクルにおいて前記プログラム可能な遅延時間を越えたときに供給される第1の瞬時位相誤差変化信号を含み、そうでない場合に第2の瞬時位相誤差変化信号が供給される、請求項6に記載の装置。
- 前記位相誤差モニター回路は、互いに結合された少なくとも2つの記憶素子(124、304)を含み、該少なくとも2つの記憶素子の各々は前記基準クロックによって瞬時位相誤差変化信号を出力し、
論理ゲート(302)が、前記少なくとも2つの記憶素子の出力を論理的に結合して差分信号を供給するように構成される、
請求項6に記載の装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/622,166 US8736323B2 (en) | 2007-01-11 | 2007-01-11 | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
US11/622,166 | 2007-01-11 | ||
PCT/US2008/050493 WO2008088976A2 (en) | 2007-01-11 | 2008-01-08 | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010516195A JP2010516195A (ja) | 2010-05-13 |
JP5016060B2 true JP5016060B2 (ja) | 2012-09-05 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009545638A Expired - Fee Related JP5016060B2 (ja) | 2007-01-11 | 2008-01-08 | 位相ロック・ループ内のジッターを決定するためのオンチップ位相誤差計測のための装置。 |
Country Status (5)
Country | Link |
---|---|
US (3) | US8736323B2 (ja) |
JP (1) | JP5016060B2 (ja) |
KR (1) | KR101159401B1 (ja) |
CN (1) | CN101578527B (ja) |
WO (1) | WO2008088976A2 (ja) |
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US20090302905A1 (en) | 2009-12-10 |
JP2010516195A (ja) | 2010-05-13 |
US20090302906A1 (en) | 2009-12-10 |
US8736323B2 (en) | 2014-05-27 |
US7999584B2 (en) | 2011-08-16 |
KR20090094445A (ko) | 2009-09-07 |
WO2008088976A2 (en) | 2008-07-24 |
WO2008088976A3 (en) | 2008-09-18 |
KR101159401B1 (ko) | 2012-07-10 |
CN101578527A (zh) | 2009-11-11 |
US7999583B2 (en) | 2011-08-16 |
US20080172193A1 (en) | 2008-07-17 |
CN101578527B (zh) | 2013-01-09 |
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