JP5015509B2 - 静電保護回路および半導体装置 - Google Patents
静電保護回路および半導体装置 Download PDFInfo
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- JP5015509B2 JP5015509B2 JP2006204715A JP2006204715A JP5015509B2 JP 5015509 B2 JP5015509 B2 JP 5015509B2 JP 2006204715 A JP2006204715 A JP 2006204715A JP 2006204715 A JP2006204715 A JP 2006204715A JP 5015509 B2 JP5015509 B2 JP 5015509B2
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- protection circuit
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- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 description 27
- 230000015556 catabolic process Effects 0.000 description 25
- 238000010586 diagram Methods 0.000 description 22
- 230000007423 decrease Effects 0.000 description 11
- 238000000605 extraction Methods 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 8
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000003068 static effect Effects 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
(第1実施形態)
(第2実施形態)
(第3実施形態)
(第4実施形態)
(第5実施形態)
2 静電保護回路
3 静電保護回路
4 静電保護回路
5 静電保護回路
10 FET
10a FET
10b FET
12 信号線
14 外部端子
20 P型基板
21 N型埋込層
22 N型領域
23 N型引出領域
24 P型領域
25 P型拡散層
26 N型拡散層
27 P型領域
28 P型拡散層
29 酸化膜
30 ゲート電極
31 N型拡散層
40 P型基板
41 N型埋込層
42 N型領域
43 N型引出領域
44 P型領域
45 P型拡散層
46 P型領域
47 ゲート酸化膜
48 ゲート電極
49 P型拡散層
50 N型拡散層
D1 ダイオード
D2 ダイオード
N ノード
Q1 バイポーラトランジスタ
Q2 バイポーラトランジスタ
Q3 バイポーラトランジスタ
Q4 バイポーラトランジスタ
R1 抵抗素子
R2 抵抗素子
Claims (16)
- 信号線と電源との間に通電方向が互いに逆方向となるように直列に接続された第1および第2の保護素子と、
前記第1および第2の保護素子間にソースおよびバルクが接続され、前記信号線にゲートが接続され、前記電源にドレインが接続された電界効果トランジスタと、
を備えることを特徴とする静電保護回路。 - 請求項1に記載の静電保護回路において、
前記各保護素子は、バイポーラトランジスタである静電保護回路。 - 請求項2に記載の静電保護回路において、
前記第1および第2の保護素子のコレクタどうしが互いに接続されており、
前記第1の保護素子のエミッタおよびベースが前記信号線に接続され、
前記第2の保護素子のエミッタおよびベースが前記電源に接続されている静電保護回路。 - 請求項3に記載の静電保護回路において、
前記バイポーラトランジスタはNPN型であり、前記電界効果トランジスタはPチャネル型である静電保護回路。 - 請求項3に記載の静電保護回路において、
前記バイポーラトランジスタはPNP型であり、前記電界効果トランジスタはNチャネル型である静電保護回路。 - 請求項2に記載の静電保護回路において、
前記第1の保護素子のエミッタおよびベースと前記第2の保護素子のエミッタおよびベースとが互いに接続されており、
前記第1の保護素子のコレクタが前記信号線に接続され、
前記第2の保護素子のコレクタが前記電源に接続されている静電保護回路。 - 請求項6に記載の静電保護回路において、
前記バイポーラトランジスタはNPN型であり、前記電界効果トランジスタはNチャネル型である静電保護回路。 - 請求項6に記載の静電保護回路において、
前記バイポーラトランジスタはPNP型であり、前記電界効果トランジスタはPチャネル型である静電保護回路。 - 請求項1に記載の静電保護回路において、
前記各保護素子は、ダイオードである静電保護回路。 - 請求項9に記載の静電保護回路において、
前記第1および第2の保護素子のカソードどうしが互いに接続されており、
前記第1および第2の保護素子のアノードが、それぞれ前記信号線および前記電源に接続されている静電保護回路。 - 請求項9に記載の静電保護回路において、
前記第1および第2の保護素子のアノードどうしが互いに接続されており、
前記第1および第2の保護素子のカソードが、それぞれ前記信号線および前記電源に接続されている静電保護回路。 - 請求項1乃至11いずれかに記載の静電保護回路において、
前記電界効果トランジスタの前記ゲートは、抵抗素子を介して前記信号線に接続されている静電保護回路。 - 請求項1乃至12いずれかに記載の静電保護回路において、
前記電界効果トランジスタの前記ソースおよび前記バルクは、抵抗素子を介して前記電源に接続されている静電保護回路。 - 請求項1乃至13いずれかに記載の静電保護回路において、
半導体基板中に設けられ、前記電界効果トランジスタの前記ドレインとして機能する不純物拡散層を備え、
前記不純物拡散層は、前記第1または第2の保護素子の一部を構成している静電保護回路。 - 請求項1乃至14いずれかに記載の静電保護回路を備えることを特徴とする半導体装置。
- 請求項15に記載の半導体装置において、
前記電界効果トランジスタは、当該半導体装置の内部回路で用いられる電界効果トランジスタである半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006204715A JP5015509B2 (ja) | 2006-07-27 | 2006-07-27 | 静電保護回路および半導体装置 |
US11/781,009 US7787226B2 (en) | 2006-07-27 | 2007-07-20 | Electrostatic protective circuit and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006204715A JP5015509B2 (ja) | 2006-07-27 | 2006-07-27 | 静電保護回路および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008034524A JP2008034524A (ja) | 2008-02-14 |
JP5015509B2 true JP5015509B2 (ja) | 2012-08-29 |
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JP2006204715A Active JP5015509B2 (ja) | 2006-07-27 | 2006-07-27 | 静電保護回路および半導体装置 |
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---|---|
US (1) | US7787226B2 (ja) |
JP (1) | JP5015509B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7041227B2 (ja) | 2019-11-05 | 2022-03-23 | ブランパン・エス アー | 文字盤を固定かつ/または取り外すシステム |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5396124B2 (ja) * | 2009-03-30 | 2014-01-22 | 新日本無線株式会社 | 半導体静電保護装置 |
US20110290876A1 (en) * | 2010-05-27 | 2011-12-01 | DataScan LP | Integrated inventory scanning and analysis system |
JP5832181B2 (ja) * | 2010-08-06 | 2015-12-16 | 株式会社半導体エネルギー研究所 | 液晶表示装置 |
JP5546991B2 (ja) * | 2010-08-09 | 2014-07-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR101710599B1 (ko) | 2011-01-12 | 2017-02-27 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US9224724B2 (en) * | 2012-05-30 | 2015-12-29 | Texas Instruments Incorporated | Mutual ballasting multi-finger bidirectional ESD device |
US8982518B2 (en) * | 2013-03-14 | 2015-03-17 | The Boeing Company | Methods and apparatus to provide transient event protection for circuits |
US9893516B2 (en) * | 2015-12-03 | 2018-02-13 | Vanguard International Semiconductor Corporation | ESD protection circuits |
JP7383343B2 (ja) | 2019-12-24 | 2023-11-20 | エイブリック株式会社 | 静電保護回路及び半導体装置 |
US20230006060A1 (en) * | 2021-07-01 | 2023-01-05 | Texas Instruments Incorporated | Reducing transistor breakdown in a power fet current sense stack |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4819047A (en) * | 1987-05-15 | 1989-04-04 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
JPH0563545A (ja) * | 1991-09-03 | 1993-03-12 | Nec Corp | Bi−CMOS回路 |
US5637900A (en) * | 1995-04-06 | 1997-06-10 | Industrial Technology Research Institute | Latchup-free fully-protected CMOS on-chip ESD protection circuit |
US5835328A (en) * | 1995-12-21 | 1998-11-10 | Intel Corporation | Breakdown-tiggered transient discharge circuit |
US6064093A (en) * | 1996-03-29 | 2000-05-16 | Citizen Watch Co., Ltd. | Protection circuit with clamping feature for semiconductor device |
US6625464B1 (en) * | 1998-08-13 | 2003-09-23 | Data Fm, Incorporated | Codeable programmable receiver and point to multipoint messaging system |
JP2002050640A (ja) | 2000-05-22 | 2002-02-15 | Sony Corp | 電界効果トランジスタの保護回路及び半導体装置 |
JP3678156B2 (ja) * | 2001-03-01 | 2005-08-03 | 株式会社デンソー | 静電気保護回路 |
JP4282581B2 (ja) | 2004-09-29 | 2009-06-24 | 株式会社東芝 | 静電保護回路 |
KR100808604B1 (ko) * | 2006-04-18 | 2008-02-29 | 주식회사 하이닉스반도체 | 반도체 장치용 정전기 보호 장치 |
JP2008103945A (ja) * | 2006-10-18 | 2008-05-01 | Toshiba Corp | 半導体装置 |
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2006
- 2006-07-27 JP JP2006204715A patent/JP5015509B2/ja active Active
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- 2007-07-20 US US11/781,009 patent/US7787226B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7041227B2 (ja) | 2019-11-05 | 2022-03-23 | ブランパン・エス アー | 文字盤を固定かつ/または取り外すシステム |
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Publication number | Publication date |
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US20080024946A1 (en) | 2008-01-31 |
US7787226B2 (en) | 2010-08-31 |
JP2008034524A (ja) | 2008-02-14 |
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