JP7383343B2 - 静電保護回路及び半導体装置 - Google Patents
静電保護回路及び半導体装置 Download PDFInfo
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- JP7383343B2 JP7383343B2 JP2019233133A JP2019233133A JP7383343B2 JP 7383343 B2 JP7383343 B2 JP 7383343B2 JP 2019233133 A JP2019233133 A JP 2019233133A JP 2019233133 A JP2019233133 A JP 2019233133A JP 7383343 B2 JP7383343 B2 JP 7383343B2
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- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000010586 diagram Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/0281—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements field effect transistors in a "Darlington-like" configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
また、本発明の半導体装置は、信号端子と内部回路の間に上記の静電保護回路を備えたことを特徴とする。
図1は、第一の実施形態の静電保護回路を備えた半導体装置を示す回路図である。
pMOSトランジスタ13は、ゲートがソースと接続されているが、ディプリーション型のためドレイン-ソース間にチャネルが存在する。ダイオード12の流すリーク電流よりもpMOSトランジスタ13の電流供給能力が十分大きければ、pMOSトランジスタ13のオン抵抗による電圧降下は0Vに近くなる。このため、ダイオード12のリーク電流のほとんどがpMOSトランジスタ13を流れ、ダイオード11には電流が流れない。従って、寄生PNPトランジスタに電流が流れないため、信号端子に流れる電流を小さく抑えることができる。
pMOSトランジスタ13は、オーバードライブ電圧が|VTPD|(しきい値電圧)の定電流源として動作する。GND端子からダイオード12とpMOSトランジスタ13を介して信号端子に逆流電流が流れるが、pMOSトランジスタ13によって許容可能な電流に抑制することが可能である。従って、ダイオード11と並列にpMOSトランジスタ13を接続しても、逆接続状態においても半導体装置の動作に問題が生じることはない。
図3は、第二の実施形態の静電保護回路を備えた半導体装置を示す回路図である。
pMOSトランジスタ13のソースとダイオード12のカソードに間に抵抗15が接続されている。抵抗15の抵抗値を十分小さくすれば、図1の静電保護回路10と同様の動作が可能である。
逆接続状態では、pMOSトランジスタ13に流れる電流がおおよそ|VTPD|/Rで決定される。ここで、Rは抵抗15の抵抗値である。即ち、この電流を逆流電流として許容可能な電流値に設定すれば良い。従って、第一の実施形態の静電保護回路10よりもpMOSトランジスタ13のサイズを小さくすることが出来る。
11、12 ダイオード
13 ディプリーション型のpチャネル型MOSトランジスタ
23 ディプリーション型のnチャネル型MOSトランジスタ
31、32 エンハンスメント型のnチャネル型MOSトランジスタ
40 内部回路
100 半導体装置
Claims (4)
- 半導体装置の信号端子の静電保護回路であって、
アノードが前記信号端子に接続された第一ダイオードと、
カソードが前記第一ダイオードのカソードに接続され、アノードがGND端子に接続された第二ダイオードと、
前記第一ダイオードと並列に接続されたディプリーション型のMOSトランジスタと、
を備え、
前記ディプリーション型のMOSトランジスタは、
ドレインが内部回路に接続され、ゲートとソースとバルクが前記第一ダイオードのカソードに接続されたpMOSトランジスタである、
ことを特徴とする静電保護回路。 - 前記pMOSトランジスタのソースと前記第一ダイオードのカソードの間に抵抗が接続された
ことを特徴とする請求項1に記載の静電保護回路。 - 半導体装置の信号端子の静電保護回路であって、
アノードが前記信号端子に接続された第一ダイオードと、
カソードが前記第一ダイオードのカソードに接続され、アノードがGND端子に接続された第二ダイオードと、
前記第一ダイオードと並列に接続されたディプリーション型のMOSトランジスタと、
を備え、
前記ディプリーション型のMOSトランジスタは、
ゲートとソースとバルクが内部回路に接続され、ドレインが前記第一ダイオードのカソードに接続されたnMOSトランジスタである、
ことを特徴とし、
前記nMOSトランジスタのソースと前記内部回路の間に抵抗が接続された
ことを特徴とする静電保護回路。 - 前記信号端子と前記内部回路の間に請求項1から3のいずれか1項に記載の静電保護回路を備えた
ことを特徴とする半導体装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019233133A JP7383343B2 (ja) | 2019-12-24 | 2019-12-24 | 静電保護回路及び半導体装置 |
TW109142448A TW202133385A (zh) | 2019-12-24 | 2020-12-02 | 靜電保護電路以及半導體裝置 |
US17/112,070 US11791330B2 (en) | 2019-12-24 | 2020-12-04 | Electrostatic protection circuit and semiconductor device |
KR1020200178913A KR20210082087A (ko) | 2019-12-24 | 2020-12-18 | 정전 보호 회로 및 반도체 장치 |
CN202011549252.1A CN113035860A (zh) | 2019-12-24 | 2020-12-24 | 静电保护电路及半导体装置 |
US18/466,492 US20240006408A1 (en) | 2019-12-24 | 2023-09-13 | Electrostatic protection circuit and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019233133A JP7383343B2 (ja) | 2019-12-24 | 2019-12-24 | 静電保護回路及び半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2021101456A JP2021101456A (ja) | 2021-07-08 |
JP2021101456A5 JP2021101456A5 (ja) | 2022-07-13 |
JP7383343B2 true JP7383343B2 (ja) | 2023-11-20 |
Family
ID=76438388
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019233133A Active JP7383343B2 (ja) | 2019-12-24 | 2019-12-24 | 静電保護回路及び半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (2) | US11791330B2 (ja) |
JP (1) | JP7383343B2 (ja) |
KR (1) | KR20210082087A (ja) |
CN (1) | CN113035860A (ja) |
TW (1) | TW202133385A (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008034524A (ja) | 2006-07-27 | 2008-02-14 | Nec Electronics Corp | 静電保護回路および半導体装置 |
US20140039520A1 (en) | 2006-06-16 | 2014-02-06 | Hani Haider | Method and apparatus for computer aided surgery |
JP2015095541A (ja) | 2013-11-12 | 2015-05-18 | パナソニックIpマネジメント株式会社 | サージ保護装置 |
JP2016052197A (ja) | 2014-09-01 | 2016-04-11 | 三菱電機株式会社 | 電力用スイッチングデバイス駆動回路 |
US20170025403A1 (en) | 2015-07-24 | 2017-01-26 | Semiconductor Components Industries, Llc | Cascode configured semiconductor component and method |
Family Cites Families (9)
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US5545909A (en) * | 1994-10-19 | 1996-08-13 | Siliconix Incorporated | Electrostatic discharge protection device for integrated circuit |
JP2000223499A (ja) | 1999-01-28 | 2000-08-11 | Mitsumi Electric Co Ltd | 静電保護装置 |
TW483143B (en) * | 2001-02-05 | 2002-04-11 | Vanguard Int Semiconduct Corp | Voltage control device for electrostatic discharge protection and its related circuit |
US6710990B2 (en) * | 2002-01-22 | 2004-03-23 | Lsi Logic Corporation | Low voltage breakdown element for ESD trigger device |
US7817459B2 (en) * | 2007-01-24 | 2010-10-19 | Keystone Semiconductor Inc. | Depletion-mode MOSFET circuit and applications |
KR101799017B1 (ko) * | 2011-08-18 | 2017-11-20 | 에스케이하이닉스 주식회사 | 전압 안정화 회로를 구비한 반도체 집적 회로 |
US9625925B2 (en) * | 2014-11-24 | 2017-04-18 | Silicon Laboratories Inc. | Linear regulator having a closed loop frequency response based on a decoupling capacitance |
CN107658856B (zh) * | 2017-10-30 | 2024-03-26 | 长鑫存储技术有限公司 | 一种静电保护电路以及集成电路芯片 |
US11271392B2 (en) * | 2019-01-17 | 2022-03-08 | Texas Instruments Incorporated | Protection circuit for signal processor |
-
2019
- 2019-12-24 JP JP2019233133A patent/JP7383343B2/ja active Active
-
2020
- 2020-12-02 TW TW109142448A patent/TW202133385A/zh unknown
- 2020-12-04 US US17/112,070 patent/US11791330B2/en active Active
- 2020-12-18 KR KR1020200178913A patent/KR20210082087A/ko active Search and Examination
- 2020-12-24 CN CN202011549252.1A patent/CN113035860A/zh active Pending
-
2023
- 2023-09-13 US US18/466,492 patent/US20240006408A1/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140039520A1 (en) | 2006-06-16 | 2014-02-06 | Hani Haider | Method and apparatus for computer aided surgery |
JP2008034524A (ja) | 2006-07-27 | 2008-02-14 | Nec Electronics Corp | 静電保護回路および半導体装置 |
JP2015095541A (ja) | 2013-11-12 | 2015-05-18 | パナソニックIpマネジメント株式会社 | サージ保護装置 |
JP2016052197A (ja) | 2014-09-01 | 2016-04-11 | 三菱電機株式会社 | 電力用スイッチングデバイス駆動回路 |
US20170025403A1 (en) | 2015-07-24 | 2017-01-26 | Semiconductor Components Industries, Llc | Cascode configured semiconductor component and method |
Also Published As
Publication number | Publication date |
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TW202133385A (zh) | 2021-09-01 |
JP2021101456A (ja) | 2021-07-08 |
CN113035860A (zh) | 2021-06-25 |
US20210193649A1 (en) | 2021-06-24 |
KR20210082087A (ko) | 2021-07-02 |
US11791330B2 (en) | 2023-10-17 |
US20240006408A1 (en) | 2024-01-04 |
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