JP4974462B2 - メモリセルアレイ、半導体デバイス、および有機半導体デバイスの製造方法 - Google Patents
メモリセルアレイ、半導体デバイス、および有機半導体デバイスの製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5664—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using organic memory material storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
- G11C13/0016—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material comprising polymers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
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- Semiconductor Integrated Circuits (AREA)
Description
|VERASE|>|VPROG|>|VREAD|(A)
|V REVERSE BREAKDOWN|>|VFOWARDTURN ON| (B)
ただし、VERASE は、メモリセルを消去するために求められる電圧レベルであり、VPROGは、メモリセルをプログラム(ライト)するために求められる電圧レベルであり、及びVREADは、リードするために求められる電圧レベルである。VREVERSE BREAKDOWNは、順方向に電流が流れることを可能にするためにダイオードをオンにするために要請される順方向電圧レベルである。これらの関係は、これらの電圧レベルの絶対値に基づく。
|Vprog|>|VERASE|>|VREAD| (C)
ただし、Vprogは、メモリセルをプログラム(ライト)するために要求される電圧レベルであり、VERASEは、メモリセルを消去するために要求される電圧レベルであり、VREADは、メモリセルをリードするために要求される電圧レベルである。この関係は、これらの電圧レベルの絶対値に基づく。
ID=IS{exp(qVD/nkT)−1}
ただし、IDは、ダイオードを流れる電流であり、VDは、ダイオード中の電圧である。加えて、ISは、逆方向飽和電流(逆バイアスされたときダイオードを通じて流れる電流。VDはネガ型である)であり、qは、電子電荷(1.602×10−19C)であり、kは、ボルツマン定数(1.38×10−23J/OK)であり、ケルビンにおけるT=接合温度、及びnは、放射係数である。
ただし、DPは、正孔拡散係数であり、τPとτnは、空乏領域における正孔と電子の効果的な寿命係数である。逆方向電流は、中性領域における拡散コンポーネントと空乏領域における発生電流の和である。拡散電流は材料中の電荷の集中における変化に起因する。2番目のタームは、エネルギー帯ギャップ内に存在する深いレベルの電荷の放出から派生したものである。加えて、Wは、空乏領域の幅であり、niは、固有密度であり、NPは、ドナー密度である。
障壁の高さは、その後半導体の金属仕事関数と電子親和度の間の差となる。
次に、薄膜が第2電極2010に形成される。薄膜層は、製造されている形式に適切な方法で第2電極にデポジットされ得る。これは、気圧CVD(APCVD:Atmospheric Pressure CVD)、低圧CVD(LPCVD:Low Pressure CVD)、PECVD、光(紫外線)CVD{(Photochemical(ultraviolet)(LPCVD)}、気相エピタキシー(VPE:Vapor Phase Epitaxy)、及び金属有機CVD(MOCVD:MetalorganicCVD)のようなCVDプロセスを含む。分子線エピタキシー(Molecular Beam Epitaxy:MBE)のようなCVDではない追加の方法も又、可能である。
Claims (7)
- メモリセルアレイであって、
アドレス指定可能な複数のメモリセルデバイスを含み、
前記メモリセルデバイスは、プログラミング、消去及びリードする目的のために一定の降伏電圧を有するダイオード特性を有するものであり、
ダイオード層が少なくとも一つのメモリセルに結合され、かつ、
前記アレイは、更に、少なくとも2つの酸化還元状態を有する材料を備えた受動層を有し、
前記受動層は、酸化還元反応による有機導電層との電気的な相互作用として、電荷を前記有機導電層に提供するとともに、前記有機導電層から電荷を受取り、
少なくとも1つのメモリセルは、第1電極と、前記第1電極上に形成されかつ前記有機導電層を形成するときに触媒として作用する前記受動層(1104)と、前記受動層上に形成された前記有機導電層(1106)とを含む有機メモリセル(1118)であり、
前記ダイオード層は、前記有機メモリセル(1118)上に形成されている、メモリセルアレイ。 - 前記ダイオード特性は、ビット線からワード線への順方向へのツェナー型ダイオードのダイオード特性である、請求項1記載のメモリセルアレイ。
- 前記ダイオード特性は、ワード線からビット線への順方向へのツェナー型ダイオードのダイオード特性である、請求項1記載のメモリセルアレイ。
- 前記ダイオード特性は、アドレス指定可能な複数のメモリセルデバイスのプログラミングを容易にするための抵抗負荷エレメントを含む、請求項1記載のメモリセルアレイ。
- 半導体デバイスであって、
受動層を備えた少なくとも一つの半導体メモリセルを有し、前記受動層は、少なくとも2つの酸化還元状態を有する材料を備えるものであり、少なくとも一つのメモリ半導体セルに結合されるダイオード層と、を含み、
前記受動層は、酸化還元反応による有機導電層との電気的な相互作用として、電荷を前記有機導電層に提供するとともに、前記有機導電層から電荷を受取り、
少なくとも1つのメモリセルは、第1電極と、前記第1電極上に形成されかつ前記有機導電層を形成するときに触媒として作用する前記受動層(1104)と、前記受動層上に形成された前記有機導電層(1106)とを含む有機メモリセル(1118)であり、
前記ダイオード層は、前記有機メモリセル(1118)上に形成されている、デバイス。 - 前記ダイオード層は、前記メモリセルのプログラミングのための抵抗負荷エレメントを与える、請求項5記載のデバイス。
- 有機半導体デバイスの製造方法(2000,2100)であって、
有機半導体セル(2002,2102)の第1電極を形成し、
前記第1電極(2004,2104)上に受動層を形成し、この受動層は、少なくとも二つの酸化還元状態を有し、かつ、有機導電層を形成するときに触媒として作用する材料を備えるものであり、
前記受動層(2006,2106)上に前記有機導電層を形成し、前記受動層は、酸化還元反応による前記有機導電層との電気的な相互作用として、電荷を前記有機導電層へ提供するとともに前記有機導電層から電荷を受取り、且つ、
前記有機導電層(2010,2108)上にツェナー型ダイオード層を形成する、方法。
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US10/287,363 US6847047B2 (en) | 2002-11-04 | 2002-11-04 | Methods that facilitate control of memory arrays utilizing zener diode-like devices |
PCT/US2003/021680 WO2004042738A1 (en) | 2002-11-04 | 2003-07-10 | Control of memory arrays utilizing zener diode-like devices |
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