JP4925115B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4925115B2 JP4925115B2 JP2007111573A JP2007111573A JP4925115B2 JP 4925115 B2 JP4925115 B2 JP 4925115B2 JP 2007111573 A JP2007111573 A JP 2007111573A JP 2007111573 A JP2007111573 A JP 2007111573A JP 4925115 B2 JP4925115 B2 JP 4925115B2
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- diffusion layer
- bonding pad
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/01093—Neptunium [Np]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
(1)外部端子に接続されるボンディグパッドの下層を含む半導体基板に、静電破壊防止に使用される保護ダイオードを形成することにより、格別な保護素子形成領域を設けることなく、静電破壊防止の強化を行うようにすることができる。
Claims (3)
- 半導体基板上に設置された複数のボンディングパッドを含み、
上記ボンディングパッド下層を含む上記半導体基板上に延在するN型の第1拡散層を備え、
上記ボンディングパッドのそれぞれに対応し、上記第1拡散層内に設けられたP型の第2拡散層を備え、
上記ボンディングパッドのうち第1電圧に接続されるボンディングパッドは上記第1拡散層と上記第2拡散層に接続され、
上記ボンディングパッドのうち信号が伝達されるボンディングパッドは、上記第2拡散層と接続され、
上記信号が伝達されるボンディングパッドに接続された上記第2拡散層は上記第1拡散層と第1保護ダイオードを形成し、
上記第1保護ダイオードは上記第1電圧にカソードが、上記信号伝達されるボンディングパッドにアノードが接続され、
上記複数のボンディングパッドと上記第1拡散層、上記第2拡散層との接続は、コンタクトホールを介して行われることを特徴とする半導体装置。 - 半導体基板上に設置された複数のボンディングパッドを含み、
上記ボンディングパッド下層を含む上記半導体基板上に延在するP型の第3拡散層を備え、
上記ボンディングパッドのそれぞれに対応し、上記第3拡散層内に設けられたN型の第4拡散層を備え、
上記ボンディングパッドのうち第2電圧に接続されるボンディングパッドは上記第3拡散層と上記第4拡散層に接続され、
上記ボンディングパッドのうち信号が伝達されるボンディングパッドは、上記第4拡散層と接続され、
上記信号が伝達されるボンディングパッドに接続された上記第4拡散層は上記第3拡散層と第2保護ダイオードを形成し、
上記第2保護ダイオードは上記第2電圧にアノードが、上記信号伝達されるボンディングパッドにカソードが接続され、
上記複数のボンディングパッドと上記第3拡散層、上記第4拡散層との接続は、コンタクトホールを介して行われることを特徴とする半導体装置。 - 半導体基板上に設けられた複数のボンディングパッドと、
上記ボンディングパッドの下層の上記半導体基板に上記ボンディングパッドの配置方向に形成されたN型の第1拡散層と、
上記第1の拡散層に隣接して形成され、上記ボンディングパッドの配置方向に形成されたP型の第3拡散層と、
上記ボンディングパッド下部の第3拡散層内に設けられ、隣接するボンディングパッド間で前記第3拡散層によって分離されたN型の第4拡散層と、
上記ボンディングパッド下部の第1拡散層内に設けられ、隣接するボンディングパッド間で前記第1拡散層によって分離されたP型の第2拡散層とを含み、
前記ボンディングパッドのうち第1電圧が供給されるボンディングパッドは前記第2拡散層と前記第1拡散層に接続され、
前記ボンディングパッドのうち前記第1電圧より低い第2電圧が供給されるボンディングパッドは前記4拡散層と前記第3拡散層に接続され、
前記ボンディングパッドのうち信号が入力または出力または入出力されるボンディングパッドは前記第2拡散層と前記第4拡散層に接続され、それぞれ上記第2拡散層は上記第1拡散層と第1保護ダイオードを、上記第4拡散層は上記第3拡散層と第2保護ダイオードを形成し、
前記ボンディングパッドと前記第1から第4の拡散層とのおのおのの接続はコンタクトホールを介して行なわれることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007111573A JP4925115B2 (ja) | 2007-04-20 | 2007-04-20 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007111573A JP4925115B2 (ja) | 2007-04-20 | 2007-04-20 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000270768A Division JP4017060B2 (ja) | 2000-09-06 | 2000-09-06 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007235156A JP2007235156A (ja) | 2007-09-13 |
JP4925115B2 true JP4925115B2 (ja) | 2012-04-25 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007111573A Expired - Fee Related JP4925115B2 (ja) | 2007-04-20 | 2007-04-20 | 半導体装置 |
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JP (1) | JP4925115B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009047834A1 (ja) * | 2007-10-09 | 2009-04-16 | Fujitsu Microelectronics Limited | フューズ回路 |
JP5252027B2 (ja) * | 2010-06-11 | 2013-07-31 | カシオ計算機株式会社 | 半導体装置の製造方法 |
US8531013B2 (en) | 2010-06-11 | 2013-09-10 | Casio Computer Co., Ltd. | Semiconductor device equipped with bonding wires and manufacturing method of semiconductor device equipped with bonding wires |
JP6454244B2 (ja) * | 2015-09-07 | 2019-01-16 | アルプス電気株式会社 | Esd保護回路及び半導体集積回路装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06188369A (ja) * | 1992-12-21 | 1994-07-08 | Nippon Motorola Ltd | 静電気破壊防止層を有する半導体回路 |
JPH07169807A (ja) * | 1993-12-16 | 1995-07-04 | Nippondenso Co Ltd | 半導体ウェハ |
JP3147849B2 (ja) * | 1998-03-06 | 2001-03-19 | 日本電気株式会社 | 半導体集積回路装置の保護回路 |
JP3948822B2 (ja) * | 1998-04-21 | 2007-07-25 | ローム株式会社 | 半導体集積回路 |
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2007
- 2007-04-20 JP JP2007111573A patent/JP4925115B2/ja not_active Expired - Fee Related
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JP2007235156A (ja) | 2007-09-13 |
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