JP4912900B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP4912900B2
JP4912900B2 JP2007019166A JP2007019166A JP4912900B2 JP 4912900 B2 JP4912900 B2 JP 4912900B2 JP 2007019166 A JP2007019166 A JP 2007019166A JP 2007019166 A JP2007019166 A JP 2007019166A JP 4912900 B2 JP4912900 B2 JP 4912900B2
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Japan
Prior art keywords
semiconductor integrated
roller
integrated circuit
flexible substrate
antenna
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Expired - Fee Related
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JP2007019166A
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Japanese (ja)
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JP2007235114A5 (enExample
JP2007235114A (ja
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理 中村
恭介 伊藤
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication of JP2007235114A5 publication Critical patent/JP2007235114A5/ja
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Thin Film Transistor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
JP2007019166A 2006-02-03 2007-01-30 半導体装置の作製方法 Expired - Fee Related JP4912900B2 (ja)

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JP2007019166A JP4912900B2 (ja) 2006-02-03 2007-01-30 半導体装置の作製方法

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JP2006027737 2006-02-03
JP2006027737 2006-02-03
JP2007019166A JP4912900B2 (ja) 2006-02-03 2007-01-30 半導体装置の作製方法

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JP2007235114A JP2007235114A (ja) 2007-09-13
JP2007235114A5 JP2007235114A5 (enExample) 2010-03-11
JP4912900B2 true JP4912900B2 (ja) 2012-04-11

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY168368A (en) 2010-10-14 2018-10-31 Stora Enso Oyj Method and arrangement for attaching a chip to a printed conductive surface
WO2013051395A1 (ja) * 2011-10-07 2013-04-11 シャープ株式会社 接着装置およびそれを用いて作製した接着基板
KR102417917B1 (ko) * 2016-04-26 2022-07-07 삼성전자주식회사 공정 시스템 및 그 동작 방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169423A (ja) * 1986-01-22 1987-07-25 Hitachi Ltd 部品移載装置
JPS62274636A (ja) * 1986-05-22 1987-11-28 Mitsubishi Electric Corp ボンデイング装置
JP2628392B2 (ja) * 1990-01-16 1997-07-09 新明和工業株式会社 Ｉｃパッケージのハンドリング方法
JP3255065B2 (ja) * 1997-01-22 2002-02-12 松下電器産業株式会社 チップの搭載装置
JP4480840B2 (ja) * 2000-03-23 2010-06-16 パナソニック株式会社 部品実装装置、及び部品実装方法
JP2005522046A (ja) * 2002-04-04 2005-07-21 シリナー，ゲオルグ，ルドルフ 電気部品とくに半導体チップを処理するためのプロセス、およびこのプロセスを実行するための装置
JP2004356376A (ja) * 2003-05-29 2004-12-16 Matsushita Electric Ind Co Ltd 部品実装装置及び部品実装方法
JP2005215754A (ja) * 2004-01-27 2005-08-11 Dainippon Printing Co Ltd Ｉｃタグ付シートの製造方法およびその製造装置

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