JP4869322B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本実施の形態の半導体装置は、側面に第1の樹脂で形成される樹脂層を有する第1の半導体チップと、この第1の半導体チップと略同一平面上に実装される第2の半導体チップとを備えている。さらに、樹脂層と第2の半導体チップとの間に設けられ、第1の半導体チップと第2の半導体チップとを接着する、室温におけるヤング率が第1の樹脂よりも高い第2の樹脂で形成される接着部とを備えている。ここでは、第1の半導体チップとしてMEMSデバイスを有するMEMSチップ、第2の半導体チップとしてCMOSデバイスを有するCMOSチップを例に説明する。
置10は、例えば、半田バンプを介して配線基板に搭載される。本実施の形態の半導体装置の製造方法によれば、チップの薄化工程の際に、低ヤング率樹脂でチップを埋め込んでいることから、接着部を変形させてチップ表面の平坦性を確保しながら高精度の研磨が可能であり、研磨時のチップ端部の欠けのない良好な研磨状態が得られる。特に中空領域を有し、機械的強度の小さいMEMSチップの研磨工程では、低ヤング率樹脂で埋め込んだ状態でチップに掛かる応力が非常に小さいことから、研磨時のMEMSチップの保護が可能であり、MEMSチップの薄化が容易に達成されるという特段の作用・効果が得られる。
本実施の形態の半導体装置は、第1の半導体チップの側面だけでなく裏面にも低ヤング率樹脂の樹脂層が形成される半導体装置である。ここでは、第1の半導体チップとしてMEMSチップを例に説明する。
本実施の形態の半導体装置は、第1の半導体チップの側面の一部に低ヤング率樹脂の樹脂層が形成される半導体装置である。ここでは、第1の半導体チップとしてMEMSチップを例に説明する。MEMSチップの構成が異なる以外は、基本的には第1の実施の形態と同様である。したがって、第1の実施の形態と重複する内容については記載を省略する。
12 MEMSチップ
14 CMOSチップ
16 受動部品チップ
18 樹脂層、低ヤング率樹脂
18a 低ヤング率樹脂フィルム
18b シリコン樹脂
20 接着部、高ヤング率樹脂
22 MEMSデバイス
24 中空領域
26 封止キャップ
28 封止枠
30 接続バンプ
32 引き出し配線
34 貫通ビア
36 電極パッド
40 グローバル配線層
42 平坦化膜
44 接続ビア
46 配線
50 チップ
52 樹脂
56 ウェハー、ウェハー形状の基板
62 粘着フィルム
64 ガラス基板
66 支持基板
68 固定台
70 グラインダ
72 疑似SOC基板
74 第1平坦化膜
76 ビアホール
80 半導体装置
82 MEMSチップ
84 CMOSチップ
86 受動部品チップ
87 スペーサ
88 ハンダボールバンプ
90 半導体装置
92 MEMSチップ
94 CMOSチップ
96 受動部品チップ
Claims (4)
- MEMSデバイスを有する複数の第1の半導体チップを第1の支持基板上に仮固定する工程と、
印刷法により、前記第1の半導体チップの間に第1の樹脂を形成する工程と、
前記第1の樹脂を硬化させる工程と、
前記第1の半導体チップを研磨する工程と、
前記第1の半導体チップを、前記第1の半導体チップの側面に前記第1の樹脂を残した状態で、ダイシングにより個片化する工程と、
前記第1の半導体チップと第2の半導体チップを第2の支持基板上に仮固定する工程と、
印刷法により、前記第1の半導体チップの側面の前記第1の樹脂と前記第2の半導体チップの間に、前記第1の半導体チップと前記第2の半導体チップを接着する、室温におけるヤング率が前記第1の樹脂よりも高い第2の樹脂を形成する工程と、
前記第2の樹脂を硬化させる工程と、
前記第1の半導体チップと前記第2の半導体チップ上に、前記第1の半導体チップと前記第2の半導体チップとを接続する配線層を形成する工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記第1の樹脂の室温におけるヤング率が50MPa以上300MPa以下、前記第2の樹脂の室温におけるヤング率が7000MPa以上であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第2の樹脂が無機材料を主成分とするフィラーを含有することを特徴とする請求項1または請求項2記載の半導体装置の製造方法。
- 前記個片化する工程において、前記第1の樹脂が、前記第1の半導体チップのチップ端部から40μm以内になるようにすることを特徴とする請求項1ないし請求項3いずれか一項記載の半導体装置の製造方法。
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JP2010141173A JP2010141173A (ja) | 2010-06-24 |
JP4869322B2 true JP4869322B2 (ja) | 2012-02-08 |
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CN103765579B (zh) * | 2011-06-30 | 2017-10-31 | 村田电子有限公司 | 系统级封装器件的制造方法和系统级封装器件 |
JP5729290B2 (ja) | 2011-12-16 | 2015-06-03 | 富士通株式会社 | 半導体装置の製造方法、電子装置の製造方法及び基板 |
JP5670392B2 (ja) | 2012-07-27 | 2015-02-18 | 株式会社東芝 | 回路基板 |
JP6116846B2 (ja) * | 2012-10-01 | 2017-04-19 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP5937190B2 (ja) * | 2014-12-12 | 2016-06-22 | 株式会社東芝 | 回路基板 |
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JP3374620B2 (ja) * | 1995-10-25 | 2003-02-10 | 松下電工株式会社 | 半導体圧力センサ |
JPH10223572A (ja) * | 1997-02-10 | 1998-08-21 | Hitachi Ltd | ダイシング方法および半導体装置 |
JP3544902B2 (ja) * | 1999-09-16 | 2004-07-21 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2006120935A (ja) * | 2004-10-22 | 2006-05-11 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4507889B2 (ja) * | 2005-01-18 | 2010-07-21 | パナソニック株式会社 | 半導体装置の製造方法 |
JP4559993B2 (ja) * | 2006-03-29 | 2010-10-13 | 株式会社東芝 | 半導体装置の製造方法 |
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