JP4845170B2 - 超シャロー金属酸化物表面チャネルmosトランジスタ - Google Patents
超シャロー金属酸化物表面チャネルmosトランジスタ Download PDFInfo
- Publication number
- JP4845170B2 JP4845170B2 JP2004370271A JP2004370271A JP4845170B2 JP 4845170 B2 JP4845170 B2 JP 4845170B2 JP 2004370271 A JP2004370271 A JP 2004370271A JP 2004370271 A JP2004370271 A JP 2004370271A JP 4845170 B2 JP4845170 B2 JP 4845170B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- channel
- surface channel
- depositing
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910044991 metal oxide Inorganic materials 0.000 title claims description 33
- 150000004706 metal oxides Chemical class 0.000 title claims description 33
- 239000000463 material Substances 0.000 claims description 64
- 238000000151 deposition Methods 0.000 claims description 58
- 239000012212 insulator Substances 0.000 claims description 56
- 238000000034 method Methods 0.000 claims description 50
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 9
- 229910018921 CoO 3 Inorganic materials 0.000 claims description 7
- 229910003855 HfAlO Inorganic materials 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 7
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 6
- 229910003437 indium oxide Inorganic materials 0.000 claims description 6
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
図1に戻ると、本発明のトランジスタデバイスのゲートスタックは、金属ゲート、高k誘電性ゲート絶縁体、および半導性金属酸化物を含む。ウェルは、P−型シリコンまたはN−型シリコンのいずれであってもよい。ウェル、ソース、およびドレインは、従来のプロセスを用いて形成され得る。本発明のデバイスと従来のMOSトランジスタとの間の違いの1つとして、本発明は、非常に薄い半導体金属酸化物を導電性チャネルとして用いることがある。
102 ソース領域
104 ドレイン領域
106 ウェル領域
110 表面チャネル
112 高k誘電性絶縁体
114 ゲート電極
Claims (19)
- p−チャネルトランジスタとn−チャネルトランジスタとを有する超シャロー表面チャネルCMOSトランジスタを製造する方法であって、
CMOSソースおよびドレイン領域と、間に挟まれた、表面を有するウェル領域とを形成する工程と、
該ウェル領域の上の該表面上に表面チャネルを堆積する工程と、
該表面チャネルの上に高k誘電体を形成する工程と、
該高k誘電体の上に、該p−チャネルトランジスタとn−チャネルトランジスタとの両方で1種類の金属を用いてゲート電極を形成する工程と
を包含し、
前記ウェル領域の上の前記表面上に表面チャネルを堆積する工程は、金属酸化物表面チャネル材料として、酸化インジウム(In 2 O 3 )、ZnO、RuO、ITO、La X−1 Sr X CoO 3 からなる群から選択される金属酸化物材料を堆積する堆積する工程を含む、方法。 - 前記表面チャネルの上にプレースホルダー材料を堆積する工程と、
酸化物を等角的に堆積する工程と、
該表面チャネルの上にゲート領域を形成するように該プレースホルダー材料をエッチングする工程と
をさらに包含する方法であって、
前記高k誘電体の上にゲート電極を形成する工程は、該ゲート領域において該ゲート電極を形成する工程を含む、請求項1に記載の方法。 - 前記プレースホルダーの堆積後に、前記ソースおよびドレイン領域を低ドープドレイン(LDD)処理する工程をさらに包含する方法であって、
前記表面チャネルの上に高k誘電性絶縁体を形成する工程は、該プレースホルダー材料の堆積の前に、該高k誘電体を堆積する工程を含み、
該方法は、
該表面チャネル、高k誘電性絶縁体、およびゲート領域に隣接して側壁絶縁体を形成する工程と、
重いイオン注入を行い、該ソースおよびドレイン領域を活性化する工程と
をさらに包含する、請求項2に記載の方法。 - 前記表面チャネルの堆積の前に、前記ソースおよびドレイン領域を低ドープドレイン(LDD)処理する工程と、
重いイオン注入を行い、該ソースおよびドレイン領域を活性化する工程と
をさらに包含する方法であって、
前記表面チャネルの上に高k誘電性絶縁体を形成する工程は、前記ゲート領域を形成するように前記プレースホルダーをエッチングする工程後に高k誘電体を堆積する工程を含む、請求項2に記載の方法。 - 前記ウェル領域の上の前記表面上に前記金属酸化物表面チャネル材料を堆積する工程は、10〜20ナノメートル(nm)の間の厚さまで前記金属酸化物材料を堆積する工程を含む、請求項1に記載の方法。
- 前記ウェル領域の上の前記表面上に前記金属酸化物表面チャネル材料を堆積する工程は、0.1〜1000オーム・cmの間の抵抗率を有する前記金属酸化物材料を堆積する工程を含む、請求項1に記載の方法。
- 前記表面チャネルの上に高k誘電性絶縁体を形成する工程は、HfO2、HfAlOX、ZrO2、およびAl3O4 からなる群から選択される高k誘電性材料を堆積する工程を含む、請求項1に記載の方法。
- 前記表面チャネルの上に高k誘電性絶縁体を形成する工程は、1〜5nmの間の厚さまで高k誘電体を堆積する工程を含む、請求項1に記載の方法。
- 前記表面チャネルの上にプレースホルダー材料を堆積する工程は、第1の厚さまで、プレースホルダー材料表面を有するプレースホルダー材料を形成する工程を含み、
酸化物を等角的に堆積する工程は、該第1の厚さの1.2〜1.5倍の間の第2の厚さまで酸化物を堆積する工程を含む方法であって、
該プレースホルダー材料表面の高さまで該酸化物の化学機械的研磨(CMP)を行う工程をさらに包含する、請求項2に記載の方法。 - 前記表面チャネル、高k誘電性絶縁体、およびゲート領域に隣接して側壁絶縁体を形成する工程は、Si3N4およびAl2O3 からなる群から選択される材料から側壁を形成する工程を含む、請求項3に記載の方法。
- p−チャネルトランジスタとn−チャネルトランジスタとを有する超シャロー表面チャネルMOSトランジスタであって、
該p−チャネルトランジスタ及び該n−チャネルトランジスタはそれぞれ、
ソース領域と、
ドレイン領域と、
該ソースと該ドレインとの間に挟まれた、表面を有するウェル領域と、
該ウェル領域の上の表面チャネルと、
該表面チャネルの上の高k誘電性絶縁体と、
該高k誘電性層の上のゲート電極と
を含み、
該ゲート電極には、該p−チャネルトランジスタとn−チャネルトランジスタとの両方で1種類の金属を用いており、
前記表面チャネルは、酸化インジウム(In 2 O 3 )、ZnO、RuO、ITO、La X−1 Sr X CoO 3 からなる群から選択される材料で構成されている、トランジスタ。 - 一時的なゲート領域を形成する、前記表面チャネルの上のプレースホルダーをさらに含むトランジスタであって、
前記ゲート電極は、該ゲート領域において形成される、請求項11に記載のトランジスタ。 - 前記プレースホルダーは、前記高k誘電性絶縁体の上に直接、一時的に形成されるトランジスタであって、
前記表面チャネル、高k誘電性絶縁体、およびゲート領域に隣接して側壁絶縁体をさらに含む、請求項12に記載のトランジスタ。 - 前記プレースホルダーは、前記表面チャネルの上に直接、一時的に形成される、請求項12に記載のトランジスタ。
- 前記表面チャネルは、10〜20ナノメートル(nm)の間の厚さを有する、請求項11に記載のトランジスタ。
- 前記表面チャネルは、0.1〜1000オーム・cmの間の抵抗率を有する、請求項11に記載のトランジスタ。
- 前記高k誘電性絶縁体は、HfO2、HfAlOX、ZrO2、およびAl3O4 からなる群から選択される材料である、請求項11に記載のトランジスタ。
- 前記高k誘電性絶縁体は、1〜5nmの間の厚さを有する、請求項11に記載のトランジスタ。
- 前記側壁絶縁体は、Si3N4およびAl2O3 からなる群から選択される材料である、請求項13に記載のトランジスタ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/761,704 | 2004-01-21 | ||
US10/761,704 US7256465B2 (en) | 2004-01-21 | 2004-01-21 | Ultra-shallow metal oxide surface channel MOS transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005210096A JP2005210096A (ja) | 2005-08-04 |
JP4845170B2 true JP4845170B2 (ja) | 2011-12-28 |
Family
ID=34750231
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004370271A Expired - Fee Related JP4845170B2 (ja) | 2004-01-21 | 2004-12-21 | 超シャロー金属酸化物表面チャネルmosトランジスタ |
Country Status (2)
Country | Link |
---|---|
US (1) | US7256465B2 (ja) |
JP (1) | JP4845170B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101078509B1 (ko) * | 2004-03-12 | 2011-10-31 | 도꾸리쯔교세이호징 가가꾸 기쥬쯔 신꼬 기꼬 | 박막 트랜지스터의 제조 방법 |
JP2006344849A (ja) * | 2005-06-10 | 2006-12-21 | Casio Comput Co Ltd | 薄膜トランジスタ |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63122177A (ja) * | 1986-11-11 | 1988-05-26 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置とその製造方法 |
EP0926739A1 (en) * | 1997-12-24 | 1999-06-30 | Texas Instruments Incorporated | A structure of and method for forming a mis field effect transistor |
WO2001093338A1 (en) * | 2000-05-26 | 2001-12-06 | Amberwave Systems Corporation | Buried channel strained silicon fet using an ion implanted doped layer |
US6900094B2 (en) * | 2001-06-14 | 2005-05-31 | Amberwave Systems Corporation | Method of selective removal of SiGe alloys |
JP4920836B2 (ja) * | 2001-07-30 | 2012-04-18 | シャープ株式会社 | 半導体素子 |
US6656852B2 (en) * | 2001-12-06 | 2003-12-02 | Texas Instruments Incorporated | Method for the selective removal of high-k dielectrics |
US6794234B2 (en) * | 2002-01-30 | 2004-09-21 | The Regents Of The University Of California | Dual work function CMOS gate technology based on metal interdiffusion |
KR100410574B1 (ko) * | 2002-05-18 | 2003-12-18 | 주식회사 하이닉스반도체 | 데카보렌 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법 |
US6621114B1 (en) * | 2002-05-20 | 2003-09-16 | Advanced Micro Devices, Inc. | MOS transistors with high-k dielectric gate insulator for reducing remote scattering |
US6982474B2 (en) * | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
ITMI20022634A1 (it) * | 2002-12-13 | 2004-06-14 | St Microelectronics Srl | Dispositivo elettronico integrato e metodo |
US7250930B2 (en) * | 2003-02-07 | 2007-07-31 | Hewlett-Packard Development Company, L.P. | Transparent active-matrix display |
-
2004
- 2004-01-21 US US10/761,704 patent/US7256465B2/en not_active Expired - Fee Related
- 2004-12-21 JP JP2004370271A patent/JP4845170B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050156254A1 (en) | 2005-07-21 |
JP2005210096A (ja) | 2005-08-04 |
US7256465B2 (en) | 2007-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6696333B1 (en) | Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes | |
JP4728323B2 (ja) | 調整可能なゲート電極の仕事関数を備えたデュアルメタルのcmosトランジスタおよびその製造方法 | |
US8735232B2 (en) | Methods for forming semiconductor devices | |
US20110018072A1 (en) | Metal gate transistor and method for fabricating the same | |
JP5544367B2 (ja) | トランジスタにおいて進歩したシリサイド形成と組み合わされる凹型のドレイン及びソース区域 | |
US8679923B2 (en) | Method for forming metal gate | |
US8716103B2 (en) | Semiconductor device and method of fabricating same | |
US7919379B2 (en) | Dielectric spacer removal | |
US9679963B2 (en) | Semiconductor structure and a method for processing a carrier | |
TWI777971B (zh) | 雙極性電晶體及其製作方法 | |
US7528451B2 (en) | CMOS gate conductor having cross-diffusion barrier | |
US7179714B2 (en) | Method of fabricating MOS transistor having fully silicided gate | |
KR20100138973A (ko) | 높이가 감소된 금속 게이트 스택을 포함하는 반도체 디바이스 및 상기 반도체 디바이스를 제조하는 방법 | |
US7348233B1 (en) | Methods for fabricating a CMOS device including silicide contacts | |
US20080093666A1 (en) | Semiconductor Device and Manufacturing Method Thereof | |
JP2007511907A (ja) | 完全に量子井戸が空乏化した低出力のマルチチャネルcmosfet | |
JP2006013270A (ja) | 半導体装置およびその製造方法 | |
JP4845170B2 (ja) | 超シャロー金属酸化物表面チャネルmosトランジスタ | |
US20090221118A1 (en) | High Voltage Semiconductor Devices | |
US7439596B2 (en) | Transistors for semiconductor device and methods of fabricating the same | |
JP2004235345A (ja) | 半導体装置及びその製造方法 | |
KR100549001B1 (ko) | 완전한 실리사이드 게이트를 갖는 모스 트랜지스터 제조방법 | |
TWI782941B (zh) | 製作p型場效電晶體的方法 | |
KR100501542B1 (ko) | 반도체 소자의 트랜지스터 제조 방법 | |
US20180090389A1 (en) | Integrated circuit comprising mos transistors and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070302 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080827 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110121 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111007 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111007 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141021 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D04 |
|
LAPS | Cancellation because of no payment of annual fees |