JP4791722B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4791722B2 JP4791722B2 JP2004273849A JP2004273849A JP4791722B2 JP 4791722 B2 JP4791722 B2 JP 4791722B2 JP 2004273849 A JP2004273849 A JP 2004273849A JP 2004273849 A JP2004273849 A JP 2004273849A JP 4791722 B2 JP4791722 B2 JP 4791722B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicide
- layer
- gate electrode
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 54
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 54
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 52
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 description 180
- 229910021332 silicide Inorganic materials 0.000 description 135
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 133
- 239000010410 layer Substances 0.000 description 124
- 238000000034 method Methods 0.000 description 30
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 18
- 230000000694 effects Effects 0.000 description 11
- 238000001020 plasma etching Methods 0.000 description 11
- 108091006146 Channels Proteins 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000004151 rapid thermal annealing Methods 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910021334 nickel silicide Inorganic materials 0.000 description 4
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000010306 acid treatment Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000001015 X-ray lithography Methods 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Kedzierski等による"Issues in NiSi-gated FDSOI device integration(NiSiゲートFDSOI装置の集積に関する発表)"IEDM Tech. Dig., 2003,pp.441−444
図1(A)は、本発明に係る第1の実施形態に従った半導体装置のフルシリサイド領域における第1のトランジスタ101の断面図である。図1(B)は、本発明に係る第1の実施形態に従った半導体装置のノンフルシリサイド領域における第2のトランジスタ102の断面図である。第1のトランジスタ101および第2のトランジスタ102は、同一の半導体チップ上に形成されている。
図14(A)本発明に係る第2の実施形態に従った半導体装置のフルシリサイド領域における第1のトランジスタ101の断面図である。図14(B)は、本発明に係る第2の実施形態に従った半導体装置のノンフルシリサイド領域における第2のトランジスタ102の断面図である。
101…第1のトランジスタ
102…第2のトランジスタ
13a…第1のソース層
13b…第2のソース層
23a…第1のドレイン層
23b…第2のドレイン層
14a…第1のシリサイド層
20a…第2のシリサイド層
14b…第3のシリサイド層
20b…第4のシリサイド層
5a、5b…ゲート絶縁膜
6a…第1のゲート電極
6b…第2のゲート電極
9a…シリコン窒化膜
Claims (1)
- 半導体基板上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に50nm以下のゲート長を有する複数のゲート電極を形成し、
前記複数のゲート電極の側壁に28nm以下の膜厚のシリコン酸化膜を形成し、
前記複数のゲート電極の側壁に前記シリコン酸化膜を介してシリコン窒化膜を形成し、
前記複数のゲート電極のうち第1のゲート電極の側壁に前記シリコン酸化膜および前記シリコン窒化膜を残存させたまま、第2のゲート電極の側壁の前記シリコン窒化膜を除去し、
前記複数のゲート電極の側壁にさらにシリコン酸化膜を形成し、
前記複数のゲート電極上に金属層を堆積し、
前記半導体基板を熱処理することによって前記複数のゲート電極の少なくとも上部をシリサイド化することを具備する半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004273849A JP4791722B2 (ja) | 2004-09-21 | 2004-09-21 | 半導体装置の製造方法 |
US11/053,600 US7427796B2 (en) | 2004-09-21 | 2005-02-09 | Semiconductor device and method of manufacturing a semiconductor device |
CNB2005101097503A CN100418224C (zh) | 2004-09-21 | 2005-09-21 | 半导体器件及半导体器件的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004273849A JP4791722B2 (ja) | 2004-09-21 | 2004-09-21 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006093233A JP2006093233A (ja) | 2006-04-06 |
JP4791722B2 true JP4791722B2 (ja) | 2011-10-12 |
Family
ID=36074611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004273849A Active JP4791722B2 (ja) | 2004-09-21 | 2004-09-21 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7427796B2 (ja) |
JP (1) | JP4791722B2 (ja) |
CN (1) | CN100418224C (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5023425B2 (ja) * | 2004-09-28 | 2012-09-12 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
JP2007165558A (ja) * | 2005-12-13 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
CN103021951B (zh) * | 2011-09-27 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | 闪存存储器及其制作方法、不同厚度栅极的形成方法 |
US20140353729A1 (en) * | 2013-05-29 | 2014-12-04 | United Microelectronics Corp. | Semiconductor structure and method for forming the same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11261020A (ja) * | 1998-03-11 | 1999-09-24 | Nec Corp | 半導体装置およびその製造方法 |
KR100327347B1 (en) * | 2000-07-22 | 2002-03-06 | Samsung Electronics Co Ltd | Metal oxide semiconductor field effect transistor having reduced resistance between source and drain and fabricating method thereof |
JP2003168740A (ja) * | 2001-09-18 | 2003-06-13 | Sanyo Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
US6498067B1 (en) * | 2002-05-02 | 2002-12-24 | Taiwan Semiconductor Manufacturing Company | Integrated approach for controlling top dielectric loss during spacer etching |
EP1411146B1 (en) * | 2002-10-17 | 2010-06-09 | Samsung Electronics Co., Ltd. | Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film |
US7112483B2 (en) * | 2003-08-29 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a device having multiple silicide types |
JP4457688B2 (ja) * | 2004-02-12 | 2010-04-28 | ソニー株式会社 | 半導体装置 |
US7122472B2 (en) * | 2004-12-02 | 2006-10-17 | International Business Machines Corporation | Method for forming self-aligned dual fully silicided gates in CMOS devices |
-
2004
- 2004-09-21 JP JP2004273849A patent/JP4791722B2/ja active Active
-
2005
- 2005-02-09 US US11/053,600 patent/US7427796B2/en not_active Expired - Fee Related
- 2005-09-21 CN CNB2005101097503A patent/CN100418224C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2006093233A (ja) | 2006-04-06 |
CN100418224C (zh) | 2008-09-10 |
US20060063362A1 (en) | 2006-03-23 |
US7427796B2 (en) | 2008-09-23 |
CN1753183A (zh) | 2006-03-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6720630B2 (en) | Structure and method for MOSFET with metallic gate electrode | |
JP3998893B2 (ja) | T型素子分離膜の形成方法 | |
US8004050B2 (en) | Semiconductor device comprising gate electrode having arsenic and phosphorous | |
JP3762378B2 (ja) | 半導体装置及びその製造方法 | |
JP2002539638A (ja) | Mis電界効果型トランジスタの製造方法 | |
JPH11284179A (ja) | 半導体装置およびその製造方法 | |
JP2002353449A (ja) | 半導体素子の製造方法 | |
KR100318311B1 (ko) | 반도체장치의 실리사이드층 형성방법 | |
US7427796B2 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
JP2009117621A (ja) | 半導体装置及びその製造方法 | |
JP2001185731A (ja) | 半導体装置及びその製造方法 | |
US20050212040A1 (en) | Semiconductor device having gate sidewall structure in silicide process and producing method of the semiconductor device | |
JP3190858B2 (ja) | 半導体装置およびその製造方法 | |
US20020001892A1 (en) | Method for fabricating semiconductor device | |
US6507075B1 (en) | Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby | |
JP2002217311A (ja) | 半導体装置及びその製造方法 | |
JP2007305889A (ja) | 半導体装置およびその製造方法 | |
JP2007251194A (ja) | 半導体装置およびその製造方法 | |
JP2005259945A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP2002246593A (ja) | 半導体装置及びその製造方法 | |
JP2006086467A (ja) | 半導体装置及びその製造方法 | |
KR100247811B1 (ko) | 반도체장치의 제조방법 | |
JP5096055B2 (ja) | Cmos型半導体集積回路の製造方法 | |
JPH07249761A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP2006140290A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060406 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081224 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090106 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090226 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090821 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090909 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100604 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100614 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110701 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110722 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140729 Year of fee payment: 3 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4791722 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |