JP4791313B2 - 配線基板および電子装置 - Google Patents
配線基板および電子装置 Download PDFInfo
- Publication number
- JP4791313B2 JP4791313B2 JP2006269809A JP2006269809A JP4791313B2 JP 4791313 B2 JP4791313 B2 JP 4791313B2 JP 2006269809 A JP2006269809 A JP 2006269809A JP 2006269809 A JP2006269809 A JP 2006269809A JP 4791313 B2 JP4791313 B2 JP 4791313B2
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- Prior art keywords
- face
- electrode
- electronic component
- electrodes
- wiring board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Structure Of Printed Boards (AREA)
Description
また、絶縁基板は複数の絶縁層を含み、端面電極が設けられる少なくとも2層の絶縁層は、端面電極が設けられない絶縁層を間に積層し、端面電極が設けられない絶縁層は、端面電極が設けられる絶縁層よりも外形が小さいことから、複数の絶縁層を積層して絶縁基板とした際、端面電極が設けられる絶縁層と端面電極が設けられない絶縁層の外形差により凹部を形成することができるので、精度良く、かつ効率良く端面電極と端面電極との間に凹部を形成することができる。
1a〜1h 絶縁層
2a〜2h 端面電極
3 凹部
4 配線導体
5 電子部品
6 切欠き部
7 凸部
8,9 収納領域
Claims (4)
- 絶縁基板の端面に電子部品を実装するための端面電極が設けられた配線基板において、
前記端面電極は1つの端面に複数設けられ、前記端面電極と前記端面電極との間には凹部が設けられており、
前記絶縁基板は、複数の絶縁層を含んでなり、前記端面電極が設けられる少なくとも2層の絶縁層は、前記端面電極が設けられない絶縁層を間に積層し、前記端面電極が設けられない絶縁層は、前記端面電極が設けられる絶縁層よりも外形が小さいことを特徴とする配線基板。 - 前記端面電極を挟んで前記凹部とは反対側に、凸部が設けられることを特徴とする請求項1記載の配線基板。
- 前記凹部は厚み方向に複数配列しており、平面視で重なり合わないように設けられることを特徴とする請求項1または2記載の配線基板。
- 請求項1〜3のいずれか1つに記載の配線基板の端面に電子部品が搭載され、該電子部品は、前記凹部を跨ぐように前記端面電極に電気的に接続されることを特徴とする電子装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006269809A JP4791313B2 (ja) | 2006-09-29 | 2006-09-29 | 配線基板および電子装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006269809A JP4791313B2 (ja) | 2006-09-29 | 2006-09-29 | 配線基板および電子装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008091561A JP2008091561A (ja) | 2008-04-17 |
JP4791313B2 true JP4791313B2 (ja) | 2011-10-12 |
Family
ID=39375423
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006269809A Active JP4791313B2 (ja) | 2006-09-29 | 2006-09-29 | 配線基板および電子装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4791313B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016046482A (ja) * | 2014-08-26 | 2016-04-04 | 住友電気工業株式会社 | 接続構造、接続構造用基板、及び接続構造の製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0429337A (ja) * | 1990-05-24 | 1992-01-31 | Shimadzu Corp | フリップチップ実装用プリント基板 |
JP2563859B2 (ja) * | 1991-09-03 | 1996-12-18 | 双信電機株式会社 | 表面実装用ハイブリッドicの端子構造 |
JP3447908B2 (ja) * | 1997-02-13 | 2003-09-16 | 富士通株式会社 | ボールグリッドアレイパッケージ |
JPH11330298A (ja) * | 1998-05-12 | 1999-11-30 | Murata Mfg Co Ltd | 信号端子付パッケージおよびそれを用いた電子装置 |
JP3435106B2 (ja) * | 1999-10-12 | 2003-08-11 | 日本電波工業株式会社 | 圧電装置 |
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2006
- 2006-09-29 JP JP2006269809A patent/JP4791313B2/ja active Active
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Publication number | Publication date |
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JP2008091561A (ja) | 2008-04-17 |
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