JP4666907B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP4666907B2
JP4666907B2 JP2003414146A JP2003414146A JP4666907B2 JP 4666907 B2 JP4666907 B2 JP 4666907B2 JP 2003414146 A JP2003414146 A JP 2003414146A JP 2003414146 A JP2003414146 A JP 2003414146A JP 4666907 B2 JP4666907 B2 JP 4666907B2
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Japan
Prior art keywords
conductive layer
pattern
etching
semiconductor device
forming
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JP2003414146A
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Japanese (ja)
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JP2004207715A5 (enExample
JP2004207715A (ja
Inventor
慎也 笹川
尚 横島
滋春 物江
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2003414146A 2002-12-13 2003-12-12 半導体装置の作製方法 Expired - Fee Related JP4666907B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003414146A JP4666907B2 (ja) 2002-12-13 2003-12-12 半導体装置の作製方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002361924 2002-12-13
JP2003414146A JP4666907B2 (ja) 2002-12-13 2003-12-12 半導体装置の作製方法

Publications (3)

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JP2004207715A JP2004207715A (ja) 2004-07-22
JP2004207715A5 JP2004207715A5 (enExample) 2007-01-18
JP4666907B2 true JP4666907B2 (ja) 2011-04-06

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JP2003414146A Expired - Fee Related JP4666907B2 (ja) 2002-12-13 2003-12-12 半導体装置の作製方法

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867983A (zh) * 2015-04-13 2015-08-26 北京大学 一种LDD/Offset结构薄膜晶体管及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4939690B2 (ja) * 2001-01-30 2012-05-30 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4854866B2 (ja) * 2001-04-27 2012-01-18 株式会社半導体エネルギー研究所 半導体装置の作製方法

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JP2004207715A (ja) 2004-07-22

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