TW554393B - Bonding structure on the panel for driver IC bonding - Google Patents

Abstract

A bonding structure on the panel for driver IC bonding comprised a lining layer forming under data lines. The lining layer can reduce the damage of the substrate. By the way, the roughness of films formed on the lining layer subsequently can be reduced, and the reliability of bonging between the bonding structure situated at the end of the data line and the driver IC will be improved.

Description

554393 V. Description of the invention (1) The present invention relates to a driving chip bonding point structure, and in particular, f relates to a driving chip bonding point structure which can be arranged at the end of a signal wiring and can improve the driving chip pressure = 4 . In response to the development trend of thin film transistor liquid crystal displays (TFT_LCD) towards large size, high resolution, and high resolution, thin film transistor components must be relatively small. In the thin film transistor manufacturing process, the etching methods are mainly divided into wet etching (Wet Etch) and dry etching (). Wet etching uses a chemical reaction of an acidic solution to remove each layer of the thin film transistor. The etching speed is fast and uniform in this way, but the disadvantage is that the solution cost is high. At the same time, due to the uniformity of the solution reaction, the etching rate in the vertical and horizontal directions is equal, which results in the variation of the critical critical dimension (Critical Dimension, CD). Alas. Compared with the wet etching method, the dry etching has a much greater ability to control the dimensions of small-size films. Dry etching mainly uses ^ counter-response and ion impact methods to etch. The vertical / lateral etching rate selection ratio is high, the horizontal key dimension variation is low, and the reaction f is relatively low. Because of & the shrinking of thin-film transistor components: The trend: ‘dry μ-cut is an inevitable choice for future advanced processes. First, please refer to FIG. 1A and FIG. 1B, which are cross-sectional schematic diagrams showing the bonding points of the driving wafers at the ends of the conventional wiring and signal wiring, respectively. 1 The driving of the end of the scanning wiring (scan 1 ine) in FIG. 1A The wafer pressure 2 points are mainly through the scanning wiring 102 on the substrate 1000 and the gate insulating layer. 104. A protective layer 106 and a transparent electrode 108 are formed. Among them, the scan line 10 \ is electrically connected to the gate of the thin film transistor, the same as the two = the gate insulation layer 10 and the protective layer 丨 06 and = placed above the scan wiring 1 〇2, Have

8172twf.ptd Page 4 554393 V. Description of the invention (2) An opening 11 0, and the scanning wiring 102 is exposed through the opening 110. The transparent electrode 108 is disposed above the scanning wiring 102 and is electrically connected to the scanning wiring 102 through the opening 110. ^ ^ In the first β diagram, the driving chip bonding point at the end of the signal wiring (da ta 1 i ne) is mainly through the gate insulating layer 104, the signal wiring 112, the protective layer 106, and the substrate 100. It is composed of a transparent electrode 108. Among them, the gate and the layer 104 are disposed on the substrate 100, the signal wiring 12 is disposed on the gate insulating layer 104, and the signal wiring 112 is electrically connected to the source of the thin film transistor. In addition, the protection layer 106 disposed above the signal wirings 1 and 2 has an opening 114, and the signal wirings 112 are exposed through the openings 114. The transparent electrode 108 is disposed above the signal wiring 112 and is electrically connected to the signal wiring 112 through the opening 114. @ # 习 知 Thin film transistor manufacturing process, where the film (gate metal layer, spar crystal layer, drain / source metal layer, protective layer and day electrode) is mostly transferred by electric field. In dry etching, the local flow rate is not good due to the gas flow distribution and the necessary item i. In order to ensure that the etching is complete, over-etching must be performed. This will cause different levels of the underlying film = extremely metallic layers. The surface of the layer will therefore be uneven. After the layer and pixel electrode are formed, each pair of post-crystals: characteristics, but will still be uneven and does not appear in the presence of =

^ 172twf.ptd Page 5 554393 V. Description of the invention (3) The driving chip bonding point at the end of the wiring does not appear uneven, and it can ensure the trust of the bonding between the driving chip and the driving chip bonding point. ^ However, there will be unevenness at the driving chip bonding point at the end of the wiring #, which will affect the reliability of the bonding between the driving chip and the driving chip bonding point. / The 2A and 2β images are SEM images showing whether the surface of the glass substrate is over-etched or not ^ ^ The effect of the subsequent formation of the surface of each film layer. The bottom ^ 1 in the figure is a glass substrate on which a silicon nitride layer is formed. Fig. 2A shows the case where the substrate surface is not etched; Fig. 2A shows the case where the glass substrate has t_. Comparing the two sides of the glass substrate and the nitrided layer in Figure 2B and Figure 2B, it is obvious that the subsequent formation of the glass substrate in Figure 2β due to over-etching = unevenness of the surface of each film layer. :: Ϊ tImproving equipment for uniformity of etching rate will be a major issue for the implementation of dry etching *. However, due to the fact that the dry-type equipment has its largest I civil system, so the dry-type engraving is uneven. The problem cannot be completely eradicated. In order to change the structure of 1 ^ Γ, the purpose is to propose a kind of pressure bonding between the driving chip bonding points ^ ^ ^ The driving chip and driving chip bonding point at the end of the wiring is based on a general layer, 1_ ' The invention proposes a driving wafer bonding point structure layer and a first dielectric layer, a first conductor layer, a second dielectric, and a first dielectric layer: a bulk layer. Among them, the lining layer is disposed on the substrate, the conductor layer, and the Z layer is disposed on the outline layer and the substrate to cover the outline layer with a portion of the 'first wiring;-on the second electrical layer' and the first conductive layer belongs to # No. 77 'Di dielectric layer is disposed on the first conductor layer and the first dielectric

Page 6 554393 V. Description of the invention (4) and the second dielectric layer has a J-layer; the two-conductor layer is arranged on the first: the first conductor layer of the dielectric layer: Is electrically connected to the first conductor layer. And the second conductor layer is invented under the first dielectric layer, and a dry etching structure used in the first dielectric layer is used, so that the system is flat. Due to the engraving on the substrate, the unevenness on the substrate has been improved, and the subsequent formation of the film layer has been improved. Therefore, the driving chip and the driving chip can be improved: further improving the signal wiring and the i-lining, -Dielectric layer: -i: lamination reliability. ; And the production of the second conductor layer: said: the body layer, the second dielectric layer =, for example, the liner layer and the thin film transistor: the body array-and made. The electrical layer is, for example, made with the gate insulating layer ::: gate at the same time. No.-the source / drain are produced at the same time, and " produced. The first conductor layer is, for example, a toilet part. Example of the second dielectric layer; the conductive layer belongs to the signal wiring: 2 if it is made with the day electrode at the same time: protect]: made at the time. The material of the second conductor is the same, the second. Therefore, the material of the 'lining layer will be the same as that of the material, and the material of the second embodiment and the material of the source / drain electrode will be the same in the present invention. Its material can include 4 in order to prevent the substrate from being excessively etched, so it is the first-conductor; the conductor of other metals such as metal or other non-conductor materials can be made of a conductor including metals such as aluminum and titanium. The material of the first dielectric layer ^ includes indium tin oxide and other insulating materials with conductive effect 7 and the shell can be silicon oxide, silicon nitride and other silicon, silicon nitride and other insulating materials; ::: of The material can include oxidation 8172twf.ptd Page 7 554393 V. Description of the invention (5) In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, in conjunction with the attached The drawings are described in detail as follows: Symbols of the drawings: 100 substrate 102 scanning wiring 104 gate insulation layer 106 protective layer 108 transparent electrodes 110, 114: opening 112 signal wiring 200 liquid crystal panel 202 display area 204 ', 20 6 ： Drive chip 208 Drive chip lamination (210 signal wiring 300 substrate 302 outline layer 304 first dielectric layer 306 first __ _ dielectric layer 30 8 Second conductor layer 310 On D 312 First-conductor layer 402 Gate layer

8172twf’.ptd Page 8 554393

554393 V. Description of the invention (7) The phenomenon of flatness, so that it will not be difficult to determine the indentation of the anisotropic conductive film when it is bonded to the driver wafer. However, it can be clearly seen from FIG. 1B and FIG. 2β that the bonding point of the driving chip disposed at the end of the signal wiring is uneven due to the unevenness of the substrate. Therefore, when it is bonded to the driving chip, It may be difficult to determine the indentation of the anisotropic conductive film. In this embodiment, structural adjustment is made to the driving chip bonding point at the end of the signal wiring to avoid the error of the indentation determination of the anisotropic conductive film \ and further increase the bonding reliability between the driving chip and the liquid crystal panel.

The underlayer 302 and the substrate 300 are covered with the underlayer 30. The first conductive layer 312 is disposed on the underlayer 302 and the first dielectric layer 304, and the first conductive layer 312 is part of the signal wiring. The second dielectric layer 306 is disposed on the first conductor layer 3, 12 and the first dielectric layer 304, and the second dielectric layer 306 has the first conductor layer 312 with an opening 31 == exposed. The second conductor layer 308 is configured.) From above the layer 312, the second conductor layer 308 is electrically connected to the first conductor layer 312 through the opening 31. Next, please refer to FIG. 4, which illustrates a schematic cross-sectional view of a driving chip bonding point and a thin film transistor of a signal wiring terminal according to a preferred embodiment of the present invention. The driving chip bonding point is structured on a substrate 300. The driving chip bonding point is composed of a liner layer 3002, a first dielectric layer 300, a first conductor layer 312, and a second dielectric. The electric layer 306 and a second conductor layer 308 are formed. Among them, the liner layer 302 is disposed on the substrate 300, and the first dielectric layer 304 is disposed on

It is obtained that a liner 302 structure is added under the first dielectric layer 304, and the dry etching used by the 430A + A pole 4 will not cause the substrate to be uneven due to over-etching. Due to the unevenness on the substrate 300,

554393

V. Description of the invention (8) It is improved, so it can effectively improve the flatness of the subsequent film formation, and further improve the credibility between the driving chip and the bonding point of the driving chip at the end of the signal wiring. '' At present, the production of thin film transistors is generally five photomask processes, which are the gate layer 402, the gate insulation layer 404 and the channel layer 405, the source / drain layer 412, the protective layer 406, and the day electrode. Production of 408. The driving sources of thin film transistors can be divided into scanning wiring and signal wiring according to their functions. Wherein, the trace wiring is produced simultaneously when the gate layer 402 is patterned, and the signal wiring is produced simultaneously when the source / drain layer 412 is patterned. Therefore, the fabrication of the liner layer 302, the first dielectric layer 304, the first conductor layer 312, the second dielectric layer 306, and the second conductor layer 308 in this embodiment can be combined with the thin film transistor array.

The backing layer 302 is, for example, simultaneously f gated with the gate layer 402 in the thin film transistor. This step can be achieved only by a slight modification of the photomask. The first dielectric layer 304 is formed at the same time as the gate insulating layer 400, for example. The first conductor layer W 2 is made at the same time as the source / drain layer 4 1 2, and the first conductor layer 3 i 2 is a part of the signal wiring in the original layout design (1 ayout). The second electrical layer 306 is formed at the same time as the protective layer 406, for example. The opening 3 1 0 of the second dielectric layer is, for example, formed with the opening 4 10 when the protective layer 4 06 is defined, and the second conductive layer 3 0 8 is produced at the same time as the pixel electrode 4 08. Therefore, in this embodiment, the material of the lining layer 3 02 is the same as the material of the gate layer hi +, for example, aluminum, titanium, or the like. The material of the first conductor layer 3 1 2 is the same as the material of the source / drain layer 41 2, such as aluminum and titanium. The material of the second standing layer 308 is, for example, the same as that of the pixel electrode 408, and is, for example,

554393 V. Description of the invention (9) Siliconized silicon nitride Integrated indium tin oxide (I TO). The material of the first dielectric layer 304 is, for example, the same as the material of the gate insulating layer 404, such as stone oxide, nitrogen ▲ *-and the material of the second dielectric layer 306 is, for example, the protective layer 406, For example, as described above, the driving chip bonding point structure of the present invention has at least the following advantages: 1 The driving chip bonding point structure of the present invention can improve the pressure between the driving chip and the driving chip bonding point at the end of the signal wiring. Total reliability. 2 · In the driving wafer bonding point structure of the present invention, the portion of the substrate covered by the liner is not affected by dry etching, so there is no problem of flatness. In addition, it also has a positive effect on the process margin of the J system. u (3 poles, ϊ, i, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 驱动, 需, 驱动, 驱动, 驱动, 需, 需, 需 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, and / or ' Although the present invention has been clarified. To limit the present invention, anyone familiar with this technique 4 does not use it within the scope of the gods, but when the seven kappa does not depart from the scope of the present invention, it should be treated as an attached applicant = This hair ... 8! 72twf.ptci $ 12 page 554393 Brief description of the drawing Figures 1A and 1B are cross-sectional schematic diagrams of the driving chip bonding points at the ends of the conventional scanning wiring and signal wiring, respectively;. Section 2A Figures and 2B are SEM images showing the influence of the surface of the glass substrate on the surface of each film layer formed after being over-etched; Figure 3 shows the driving wafer pressure at the end of the scanning wiring and signal wiring on the LCD panel A schematic diagram of the configuration of the joints; and FIG. 4 is a schematic cross-sectional view of the bonding point of the driving chip and the thin-film transistor at the end of the signal wiring according to a preferred embodiment of the present invention.

8172twf.ptd Page 13

Claims (1)

554393 VI. Application Patent Scope 1. A driving chip bonding point structure is suitable for arranging the end of a signal wiring on a thin film transistor array substrate to be electrically connected with a contact on a driving chip. The junction structure includes at least: a backing layer disposed on the thin film transistor array substrate; a first dielectric layer disposed on the substrate of the backing disk; A conductor layer, the first conductor layer is disposed between the liner layer and the first dielectric layer, and the first conductive layer belongs to two parts of the signal wiring; a second dielectric layer, the second A dielectric layer is disposed on the first conductor layer and σHeldi " on the electrical layer, and the second dielectric layer has an opening to expose the first conductor layer; and β a second conductor layer, the second conductor layer is disposed above the first conductor layer, And the second conductor layer is electrically connected to the first conductor layer through the opening 2. The driving chip bonding point junction described in item 丨 of the patent application range: each of the following: Ξ ΐThe transistor array substrate has A plurality of thin film ° transistors. Body ::-These thin film transistor systems consist of a gate electrode, an inter-electrode insulation layer, a = layer, a source electrode, a non-polar electrode, a protective layer, and a pixel electrode. The structure Λ =! Is the driving chip bonding point structure described in the first item, wherein the material of the sacrificial liner is a conductor layer. ^ The structure of the driving chip compression point according to item 1 of the scope of the patent application, wherein the material of the first conductor layer includes aluminum and titanium. 5. The driving wafer bonding point junction as described in the i-th member of the scope of patent application H172twr.ptd 554393 6. The scope of the patent application, wherein the material of the second conductor layer includes indium tin oxide. 6. The driving wafer bonding point structure described in item 1 of the scope of the patent application, wherein the material of the first dielectric layer includes oxide stone and nitride stone. 7. The driving chip bonding point structure according to item 1 of the scope of patent application, wherein the material of the second dielectric layer includes silicon nitride. 8. The driving chip bonding point structure described in item 2 of the scope of patent application, wherein the material of the outline layer is the same as that of the gate electrode. Isomorphism Isomorphism 9. The driving chip bonding point junction described in item 2 of the scope of patent application, wherein the material of the first conductor layer is in phase with the material of the source electrode and the drain electrode. The driving chip bonding point junction described in item 2 wherein the material of the second conductor layer is the same as the material of the day electrode 11. The driving chip bonding point junction described in item 2 of the patent application scope wherein the first dielectric The material of the electrical layer is the same as the material of the gate insulating layer. 1 The driving wafer bonding point junction described in item 2 of the patent application, wherein the material of the second dielectric layer is the same as that of the protective layer. 8172twf.ptd Page 15