JP2009278049A - Wiring structure, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide wiring structure preventing the occurrence of connection failure and application of damage to a wiring layer and achieving a connection state of high reliability in high yield, and to provide a display device. <P>SOLUTION: In the wiring structure, wide portion (wiring portion 22) of wiring formed on a substrate is electrically connected to connection pads (e.g. OLB pads 4) for external connection through contact holes formed on an insulating film 23 formed on the wiring. The insulating film 23 covering the wiring is formed by an application method, and in the wide wiring portion 22, the contact holes 26 are formed only in a peripheral area. Or, the opening dimensions of each of contact holes 26 formed on the peripheral area of the wide wiring portion 22 may be formed smaller than the opening dimensions of contact holes 28, 29 formed in an inner area. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a wiring structure and a display device in which interlayer connection is achieved by forming a contact hole in a coating type insulating film, and in particular, to ensure interlayer connection in a connection pad for external connection. Regarding improvements.

  For example, since a liquid crystal display device is a flat display device having excellent characteristics such as thinness, light weight, and low power consumption, a mobile device such as a so-called PDA or a mobile phone, a display unit of a personal computer, and further a liquid crystal display It is used for a wide range of applications such as television.

  The liquid crystal display device includes a liquid crystal display panel having a structure in which a liquid crystal layer is sandwiched between a pair of display panel substrates, that is, an array substrate and a counter substrate, and is selected for each pixel between the array substrate and the counter substrate. In addition, the liquid crystal layer is controlled by applying a voltage to display an image. Here, for example, in an active matrix liquid crystal display panel, thin film transistors (TFTs) are formed as switching elements using amorphous silicon or polysilicon semiconductor on an array substrate, and pixel electrodes and scanning lines connected to the switching elements. , Signal lines and the like are formed. On the other hand, a counter electrode made of indium tin oxide (ITO) or the like, a color filter, or the like is formed on the counter substrate.

  In the manufacture of a liquid crystal display panel having the above-described structure, a thin film transistor that constitutes a drive circuit such as a driver circuit or a power supply circuit is formed on a substrate. For example, it is installed as an external integrated circuit (IC). The drive circuit that has been used has been built into the frame area of the liquid crystal display panel. However, liquid crystal display panels used for mobile products, for example, are required to suppress the increase in size as much as possible, and the frame area necessary for wiring formation around the liquid crystal display panel is reduced. It has become a big issue.

  Therefore, conventionally, for example, in process technology, an attempt has been made to shift from wet etching to dry etching, to reduce the etching conversion difference, thereby realizing miniaturization of wiring and to narrow the frame. However, as the miniaturization of wiring advances, it is necessary to increase the wiring film thickness instead of reducing the wiring width in order to realize a low resistance wiring. However, it is becoming increasingly difficult to narrow the frame.

Under such circumstances, as in the semiconductor field, etc., there has been an active movement to incorporate multilayer wiring technology (see, for example, Patent Document 1). Patent Document 1 includes an array substrate having a display portion and a frame portion. The display portion includes a plurality of wirings and a plurality of thin film transistors connected to the wirings. The frame portion drives the thin film transistors. There is disclosed an image display device including a driving circuit that includes a first wiring layer formed of a first wiring material and a second wiring layer formed on the first wiring layer. In the invention described in Patent Document 1, the wiring is composed of the first wiring layer and the second wiring layer, and a material suitable for miniaturization and a low-resistance material are selectively used according to the role in these wiring layers. Has been realized.
JP 2002-297057 A

  By the way, when the wiring has two layers, the formation of an interlayer insulating film becomes a big problem. For example, in the conventional method, the interlayer insulating film is mainly formed by the CVD method, but the wiring step cannot be filled, so the wiring formed on the insulating film intersects the wiring under the insulating film. In many cases, so-called thinning or disconnection is often generated, and it is difficult to form a multilayer wiring.

  In recent years, attention has been paid to the formation of an insulating film by a coating method instead of the CVD method. In the case of an insulating film formed by a coating method, a wiring step can be reduced, so that even if the wiring intersects with the insulating film between the upper and lower sides, no thinning or disconnection occurs.

  However, as a result of repeated studies by the present inventors, in the insulating film forming method by the coating method, even if a relatively thin wiring can fill a step, a wide wiring is formed on the wiring. It has been found that the thickness of the insulating film is not uniform, which causes troubles in forming contact holes. For example, in an array substrate or the like of a liquid crystal display device, in addition to fine wiring such as signal lines, in a connection pad forming portion for external connection for connection to an external circuit, the wiring has a wide wiring pattern (wide portion However, when a contact hole for electrical connection with a connection pad for external connection is formed in this wide portion, due to the non-uniformity of the film thickness of the insulating film, Insufficient etching causes connection failure, and conversely, excessive etching damages the underlying wiring layer.

  The present invention has been proposed in view of such a conventional situation, can prevent the occurrence of connection failure and damage to the wiring layer, and can provide good yield and the connection pad for external connection. An object of the present invention is to provide a wiring structure capable of realizing a highly reliable connection state, and further to provide a display device.

  In order to achieve the above-described object, the wiring structure of the present invention is connected to an external connection through a contact hole provided in an insulating film formed on the wiring in a wide portion of the wiring formed on the substrate. A wiring structure in which electrical connection with a pad is achieved, wherein an insulating film covering the wiring is an insulating film formed by a coating method, and at least in a wide portion of the wiring, a peripheral region of the wide portion A contact hole is formed only in the region.

  Alternatively, in a wiring structure in which electrical connection with a connection pad for external connection is achieved through a contact hole provided in an insulating film formed on the wiring in a wide portion of the wiring formed on the substrate. The insulating film covering the wiring is an insulating film formed by a coating method, and at least in the wide portion of the wiring, the opening size of the contact hole formed in the peripheral region of the wide portion is formed in the internal region. The opening size of the contact hole is smaller.

  Furthermore, the display device of the present invention is characterized by having an array substrate having these wiring structures.

  As described above, in the insulating film formed on the wide portion of the wiring by the coating method, the film thickness is not uniform, and the film thickness tends to be thicker at the center of the wiring than at the wiring end. For example, when the wiring width exceeds 20 μm, the film thickness of the insulating film increases from 1.5 times to 2 times from the wiring end toward the center.

  Here, when a contact hole is formed in such an insulating film, since there is almost no photosensitive insulating material for the insulating film formed by the coating method, it is formed by a dry etching method using a resist mask. I must. However, when processing (contact hole formation) for obtaining the connection between the upper and lower wirings by this method is performed, a difference occurs between the etching time in the thin part and the etching time in the thick part, It is difficult to form good contact holes. For example, when forming a contact hole for interlayer connection in a normal wiring (narrow wiring) and a contact hole for interlayer connection with a connection pad in a wide wiring (said wide portion) simultaneously, When etching is performed by paying attention to the thick insulating film on the upper side, the insulating film on the normal wiring is thin, so that the contact hole for interlayer connection of the normal wiring penetrates earlier. Therefore, it takes a long time for the normal wiring to be exposed to the plasma at the time of dry etching, and the normal wiring directly under the contact hole may be damaged, which may cause a connection failure such as an increase in contact resistance. On the other hand, if etching is performed with a focus on a thin insulating film on the normal wiring, the contact hole on the wide wiring is not opened, and there is a possibility that connection failure may occur.

  On the other hand, in the present invention, in the wide portion of the wiring, the contact hole is formed only in the peripheral region of the wide portion. In the insulating film formed on the wide portion of the wiring, the film thickness of the peripheral region is thin and thick at the center portion. Therefore, the contact hole formed in the peripheral region of the wide portion of the wiring and the contact hole formed in the normal wiring are penetrated simultaneously without causing a difference in etching time. Therefore, no damage due to over-etching or no opening occurs, and a good connection state is realized in any contact hole.

  Alternatively, in the present invention, in the wide portion of the wiring, the opening size of the contact hole formed in the peripheral region of the wide portion is smaller than the opening size of the contact hole formed in the internal region. Also in this case, the contact hole formed in the peripheral region of the wide portion is penetrated simultaneously with the contact hole formed in the normal wiring. On the other hand, the contact hole formed in the inner region is also penetrated simultaneously with the contact hole formed in the normal wiring. This is because the insulating film is thick at the central portion of the wide portion, but when the contact hole has a large opening size, the etching progresses quickly and the difference in etching time is offset.

  According to the present invention, it is possible to reliably prevent the occurrence of connection failure due to non-opening and damage to the wiring layer due to over-etching, and high reliability with a connection pad for external connection with high yield. It is possible to realize a connection state. Therefore, a highly reliable wiring structure and display device can be provided with high yield and low cost.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a wiring structure and a display device to which the present invention is applied will be described in detail with reference to the drawings.

  First, a schematic configuration of a liquid crystal display device to which the wiring structure of the present invention is applied will be described. As shown in FIG. 1, the liquid crystal display device includes a liquid crystal display panel 1 including an array substrate 2 and a counter substrate 3, and a liquid crystal layer between the array substrate 2 and the counter substrate 3 is placed on the array substrate 2. An image is displayed by driving the formed thin film transistor (pixel transistor) as a switching element.

  Here, in the display region H that is a display unit, pixel electrodes are formed in a matrix corresponding to each pixel on the array substrate 2, and scanning lines are formed along the row direction of the pixel electrodes. A signal line is formed along the line. Further, the pixel transistor is formed at the intersection of each scanning line and signal line.

  On the other hand, in the peripheral area of the array substrate 2 (the frame area of the liquid crystal display panel 1), a signal line drive circuit that supplies drive signals to the signal lines arranged and formed on the array substrate 2 and a drive signal is supplied to the scanning lines. A driving circuit such as a scanning line driving circuit is formed, and an OLB pad 4 for connecting the driving circuit and an external circuit is formed. The signal line driving circuit and the scanning line driving circuit are composed of, for example, a plurality of thin film transistors and wirings connected to the thin film transistors. The OLB pad 4 is a connection pad for external connection, and is formed as a conductive pad that is electrically connected to the wiring. Then, for example, by connecting the terminal portion of the wiring for external connection formed on the flexible wiring board using an anisotropic conductive adhesive film or the like, the drive circuit and the external circuit can be electrically connected.

  In the liquid crystal display device of the present embodiment, the wiring is a two-layer wiring, and the frame region is narrowed. With the two-layer wiring structure, the degree of freedom of wiring routing can be increased and the wiring width can be set large, so that the area of the frame region can be reduced while reducing the resistance of the wiring.

  As described above, when the two-layer wiring structure including the upper wiring layer and the lower wiring layer is adopted, the selection of the interlayer insulating film is important. For example, as shown in FIGS. 2A and 2B, an insulating film needs to be formed between the lower wiring layer 12 and the upper wiring layer 13 formed on the substrate 11, but the conventional method (CVD) The step of the wiring cannot be filled with the CVD insulating film 14 formed by the method. For this reason, in the portion where the lower wiring layer 12 and the upper wiring layer 13 intersect, wiring thinness 13a and disconnection often occur in the upper wiring layer 13, making it difficult to form a multilayer wiring.

  In order to solve this problem, in this embodiment, as shown in FIGS. 3A and 3B, an interlayer insulating film is formed by a coating method to form a planarizing insulating film 15. The planarization insulating film 15 formed by the coating method is formed so as to fill the wiring step, and the upper surface is substantially planarized. Therefore, the wiring level difference is alleviated, and in the upper wiring layer 13 formed on the planarization insulating film 15, the wiring is thinned or disconnected even in the portion 13b where the lower wiring layer 12 and the upper wiring layer 13 intersect. There is no.

  However, when the insulating film is formed by the coating method as described above, the film thickness of the insulating film is not uniform on the wide wiring, and the film thickness at the center of the wiring is thicker than the wiring edge. . FIG. 4 schematically shows the film thickness distribution of the insulating film 23 formed by the coating method on the wiring portion 22 connected to the thin film transistor of the driving circuit and the wiring portion 22 corresponding to the OLB pad 4, for example. The thin film transistor of the driver circuit is configured by forming a source region 24a and a drain region 24b in a semiconductor layer 24 formed on a substrate 20, and forming a gate electrode 25 on a channel. The wiring 21 is formed on the semiconductor layer 24 via the first interlayer insulating film S1, and is connected to the source region 24a and the drain region 24b of the thin film transistor. On the other hand, the wiring portion 22 corresponding to the OLB pad 4 is formed wider than the wiring 21 corresponding to the OLB pad 4.

  When the insulating film 23 that is the second interlayer insulating film is formed by a coating method so as to cover the wiring 21 and the wiring portion 22, a wiring step in a narrow line width portion such as the wiring 21 can be filled. The film thickness of the insulating film 23 formed in this is different between the wiring end and the wiring center. For example, the film thickness T2 at the center of the wiring is larger than the film thickness T1 at the wiring end. The film thickness T1 at the wiring end is substantially equal to the film thickness T3 of the insulating film 23 formed on the wiring 21 having a narrow line width.

  If a contact hole for connection to the upper layer wiring or OLB pad is to be formed in the insulating film 23 on the wiring 21 and the wiring portion 22 in such a state, it is difficult to perform appropriate etching due to a difference in etching time. For example, when a contact hole is formed in the center of each of the narrow wiring 21 and the wide wiring portion 22, the etching is performed by paying attention to a thick insulating film (the insulating film 23 in the central portion of the wide wiring portion 22). As shown in FIG. 5A, when the contact hole 26 formed in the insulating film 23 on the wiring portion 22 penetrates, the contact hole 27 formed in the insulating film 23 on the wiring 21 Over-etching occurs, and the time during which the wiring 21 is exposed to plasma during dry etching becomes longer and is damaged. This damage to the wiring 21 causes a connection failure such as an increase in contact resistance. Conversely, when etching is performed while paying attention to a thin insulating film (insulating film 23 on the wiring 21), a contact hole formed in the insulating film 23 on the wiring 21 as shown in FIG. When 27 penetrates, the contact hole 26 formed in the insulating film 23 on the wide wiring portion 22 is not opened. If the contact hole 26 is not opened, electrical continuity with the OLB pad 4 which is a connection pad for external connection cannot be achieved.

  Therefore, in the present invention, the contact hole 27 is formed only in the peripheral region of the wide wiring portion 22 to solve the above problem. As described above, the film thickness T1 of the insulating film 23 at the wiring end of the wiring part 22 is substantially equal to the film thickness T3 of the insulating film 23 formed on the wiring 21 having a narrow line width. Therefore, in the formation of the contact hole 26 in the wiring portion 22 and the formation of the contact hole 27 in the wiring 21, the difference in etching time can be eliminated, and the occurrence of poor connection can be avoided.

  Specifically, for example, as shown in FIGS. 6A and 6B, a circular contact hole 26 is formed in a peripheral region of the wide wiring portion 22 (here, a region along three sides of the wiring portion 22). To form an array. The size of each contact hole 26 may be equal to the size of the contact hole 27 formed on the wiring 21. By forming the contact hole 26 in a concentrated manner at the end of the wiring in this way, the film thickness of the insulating film on the wiring becomes substantially uniform, and the etching time of the contact hole 26 and the etching time of the contact hole 27 become substantially constant. . Therefore, it is possible to form the contact holes 26 and 27 without damaging the wiring 21 under the insulating film 23, and it is possible to eliminate factors affecting the drive circuit such as an increase in contact resistance.

  In the same way, as shown in FIG. 7, it is possible to form the contact hole 26 as a groove-shaped pattern around the wiring end of the wide wiring portion 22. By making the contact hole 26 into a slit shape and forming it in a region along the three sides of the wiring portion 22, the same effect can be obtained.

  Further, as shown in FIGS. 8A and 8B, circular contact holes 26 are formed in an array in the peripheral region of the wide wiring portion 22 (here, the region along the three sides of the wiring portion 22). In addition, it is possible to form a contact hole 28 or a contact hole 29 having an opening size larger than that of the contact hole 26 in an inner region (inner region). Depending on the material of the insulating film 23, that is, when the insulating film 23 is formed of a material having a different etching rate depending on the processing shape, the contact hole diameter is increased even if the thickness of the insulating film 23 is increased. Thus, it is possible to make the etching time difference caused by the film thickness difference substantially the same. In this case, the diameters of the contact holes 26, 28, and 29 to be formed may be sequentially increased at a rate of 50% or less toward the center of the wiring portion 22.

Of these methods, which method should be adopted may be determined by the material characteristics. For example, when the insulating film 23 is formed of a material that has a high viscosity and is difficult to obtain sufficient flatness, the method shown in FIGS. 6 and 7 is effective. The method shown in FIG. 6 is effective when the insulating film 23 is formed of an inorganic material close to SiO ₂ and can be processed under the same conditions as the CVD film, and is effective when fine processing is possible. . On the other hand, when an organic material having a carbide in the side chain is used, the dry etching process itself is often difficult, and is effective when a large processing area is required. From the viewpoint of connection reliability, in the formation of the groove-shaped contact portion having a large connection area as shown in FIG. 7, a higher connection yield can be obtained, so that the insulating film is made of an inorganic material close to SiO _2. Needless to say, it can also be applied to materials. Further, when the machining shape dependency is large, the method shown in FIG. 8 is effective. As in the method shown in FIG. 8, the contact portion is provided on almost the entire surface of the wiring portion 22 in order to increase the connection area and obtain a higher connection yield. Whichever method is selected, the wiring can be formed without damaging the wiring under the insulating film 23.

  As mentioned above, although embodiment of this invention has been described, it cannot be overemphasized that this invention is not what is limited to the above-mentioned embodiment. For example, in the above-described embodiment, an example in which the present invention is applied to a liquid crystal display device has been described. However, the display device is not limited to a liquid crystal display device, and can be applied to, for example, an organic EL display device.

  Hereinafter, specific examples to which the present invention is applied will be described based on experimental results.

Example 1
Thin film transistors were formed by repeating film formation and patterning in the same manner as the process for forming ordinary TFTs. Thereafter, an interlayer insulating film was formed to a thickness of 600 nm, and a contact hole for connection with the TFT was formed. Next, a first signal wiring was formed, and an insulating film based on silsesquioxane close to an inorganic material was applied as a second interlayer insulating film so as to have a film thickness of 600 nm. There is no problem whether the coating method is a spin method or a slit method. With regard to this material, from a prior verification, when applied to a substrate with a film thickness of 600 nm, the insulation film thickness on a 300 nm thick wiring having a width of 15 μm or more is the insulation on the wiring having a wiring width smaller than that. It has been found to be 1.5 times the film thickness. In addition, it has almost the same processing characteristics as CVD-type SiO ₂ that insulates the TFT from the first signal wiring, and a fine contact hole can be formed.

  Then, for the wiring having a width of 15 μm or more, as in the example shown in FIG. 6A, a line is formed around the wiring end so that the end of the contact hole is arranged at a position of 0.5 μm from the wiring end. Contact holes with a diameter of 3.0 μm were arranged at equal intervals. Thereafter, the second signal wiring is arranged so as to be connected to the first signal wiring, and an array substrate is manufactured. The second signal wiring has a large number of regions intersecting the first signal wiring through the coating type insulating film, but no thinning or disconnection occurs at all, and a connection failure occurs in each contact hole. It was confirmed by a TFT element inspection device that the above was not performed.

(Example 2)
Thin film transistors were formed by repeating film formation and patterning in the same manner as the process for forming ordinary TFTs. Thereafter, an interlayer insulating film was formed to a thickness of 600 nm, and a contact hole for connection with the TFT was formed. Next, a first signal wiring was formed, and an insulating film based on polysiloxane which is an organic material was applied as a second interlayer insulating film so as to have a film thickness of 600 nm. With regard to this material, from the prior verification, when applied to a substrate with a film thickness of 600 nm, the insulation film thickness on a 300 nm-thick wiring having a width of 15 μm or more is the insulation on a wiring having a wiring width smaller than that. It has been found to be 1.9 times the film thickness. However, CVD-type SiO ₂ that insulates the TFT from the first signal wiring does not show the same characteristics and is difficult to finely process.

  Therefore, as in the example shown in FIG. 7, for the wiring having a width of 5 μm or more, the groove around the wiring end is arranged so that the end of the groove-shaped contact region is arranged at a position of 0.5 μm from the wiring end. A contact region (slit contact hole) having a width of 3.0 μm was disposed. Thereafter, the second signal wiring is arranged so as to be connected to the first signal wiring, and an array substrate is manufactured. The second signal wiring has many regions intersecting with the first signal wiring through the coating type insulating film, but there is no occurrence of thinning or disconnection at all, and connection failure occurs in each contact hole. It was confirmed by a TFT device inspection apparatus that the above was not present.

(Example 3)
Thin film transistors were formed by repeating film formation and patterning in the same manner as the process for forming ordinary TFTs. Thereafter, an interlayer insulating film was formed to a thickness of 600 nm, and a contact hole for connection with the TFT was formed. Next, a first signal wiring was formed, and an insulating film based on an F-based polymer, which is an organic material, was applied as a second interlayer insulating film to a thickness of 600 nm. With regard to this material, from the prior verification, when applied to a substrate with a film thickness of 600 nm, the insulation film thickness on a 300 nm-thick wiring having a width of 15 μm or more is the insulation on a wiring having a wiring width smaller than that. It has been found to be 2.1 times the film thickness. Furthermore, there is a processing shape dependency, and processing of a pattern having a hole thickness of 5.0 μm or more in a uniform film thickness is 1/3 of the etching time when forming a processing shape having a hole diameter of 2.0 μm. Something has been obtained as data.

  Therefore, as in the example shown in FIG. 8, the contact holes are arranged at the center of the wiring so that the contact hole diameters are sequentially increased by 45% with respect to the direction. Thereafter, the second signal wiring is arranged so as to be connected to the first signal wiring, and an array substrate is manufactured. The second signal wiring has a large number of regions intersecting with the first signal wiring through the coating type insulating film, but there is no occurrence of thinning or disconnection at all, and connection failure occurs in each contact hole. It was confirmed by a TFT element inspection apparatus that there was no such element.

It is a perspective view which shows schematic structure of a liquid crystal display device. The wiring formation state at the time of forming an insulating film by CVD method is shown, (a) is a schematic plan view, (b) is a schematic sectional drawing. The wiring formation state at the time of forming an insulating film by the apply | coating system is shown, (a) is a schematic plan view, (b) is a schematic sectional drawing. It is a schematic sectional drawing which shows the film thickness difference of the insulating film formed by the apply | coating system. (A) is a schematic sectional drawing which shows the etching state at the time of etching paying attention to a thick insulating film, (b) shows the etching state at the time of etching paying attention to a thin insulating film It is a schematic sectional drawing. (A) is a schematic plan view which shows the example of formation of a contact hole, (b) is the schematic sectional drawing. (A) is a schematic plan view which shows the other example of formation of a contact hole. (A) is a schematic plan view which shows the other example of formation of a contact hole, (b) is the schematic sectional drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel, 2 Array substrate, 3 Opposite substrate, 4 OLB pad, 21 wiring, 22 Wide wiring part, 23 Insulating film, 24 Semiconductor layer, 26, 27, 28, 29 Contact hole

Claims (6)

A wiring structure in which a wide portion of a wiring formed on a substrate is electrically connected to a connection pad for external connection through a contact hole provided in an insulating film formed on the wiring. ,
The insulating film covering the wiring is an insulating film formed by a coating method,
At least in a wide portion of the wiring, a contact hole is formed only in a peripheral region of the wide portion. A wiring structure in which a wide portion of a wiring formed on a substrate is electrically connected to a connection pad for external connection through a contact hole provided in an insulating film formed on the wiring. ,
The insulating film covering the wiring is an insulating film formed by a coating method,
At least in the wide part of the wiring, the opening size of the contact hole formed in the peripheral region of the wide part is smaller than the opening size of the contact hole formed in the internal region.   3. The wiring structure according to claim 1, wherein the wiring is composed of two or more wiring layers, and an insulating film between the wiring layers is an insulating film formed by the coating method.   4. The wiring structure according to claim 1, wherein an opening shape of the contact hole is substantially circular, and a plurality of contact holes are formed in each connection pad. 5.   The wiring structure according to claim 1, wherein an opening shape of the contact hole is a slit shape.   A display device comprising an array substrate provided with the wiring structure according to claim 1.

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