JP4599808B2 - Electro-optical panel drive circuit, and electro-optical device and electronic apparatus including the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a drive circuit for driving an electro-optical panel such as a liquid crystal panel, an electro-optical device such as a liquid crystal device including the electro-optical panel and the drive circuit, and a liquid crystal projector including the electro-optical device. Belongs to the technical field of electronic equipment.
[0002]
[Background]
Examples of this type of electro-optical panel driving device include a data line driving circuit that drives data lines of the electro-optical panel. The data line driving circuit is configured to sequentially output the transfer signal output from the shift register circuit as a sampling pulse to the sampling circuit. In response to the sampling pulse, the sampling circuit is configured to sample the image signal on the image signal line and supply it to the data line.
[0003]
In such a drive circuit configuration, the output of the transfer signal from the shift register circuit is performed in synchronization with the clock cycle of the clock signal supplied to the data line drive circuit and the inverted clock signal obtained by inverting the clock signal. It is common. Here, in general, the phase difference between the clock signal and the inverted clock signal deviates more or less from 180 degrees, which is an ideal phase difference corresponding to the inverted state, according to their generation method.
[0004]
Therefore, conventionally, as disclosed in, for example, Patent Document 1, before the clock signal and the inverted clock signal are input to the shift register circuit, the phase difference for correcting the phase difference between the clock signal and the inverted clock signal is corrected. A technique for providing a correction circuit has been developed. According to this technique, it is possible to obtain a clock signal and an inverted clock signal that are very close to an inverted state, and thereby, it is possible to perform a driving operation in the data line driving circuit with high accuracy.
[0005]
[Patent Document 1]
JP 2001-166743 A
[0006]
[Problems to be solved by the invention]
However, the phase difference correction circuit includes an inverter circuit, for example, and current is consumed according to the phase difference to be corrected, and heat is generated from the phase difference correction circuit accordingly. The amount of heat generated is usually significantly larger than that of other drive circuits formed on the element substrate constituting the electro-optical device. Incidentally, the amount of heat generated in such a phase difference correction circuit can be several tens or hundreds of times larger than that of a shift register circuit in the data line driving circuit, for example. As a result, the portion of the image display area close to the location where the phase difference correction circuit is disposed has a display contrast different from that of other places due to local temperature rise caused by heat generation, and cannot be ignored in the image display area. There is a technical problem that a degree of contrast spots may occur. For example, the phase difference correction circuit is arranged, for example, near one corner of the image display area according to the routing method of the signal wiring of the clock signal and the inverted clock signal on the substrate. Contrast spots occur in the vicinity.
[0007]
In order to cope with such a problem, a countermeasure for arranging the phase difference correction circuit as far as possible from the image display area can be considered. However, the phase difference correction circuit is separated from the image display area on a limited element substrate. There is an essential limit to moving away from it, and it becomes an obstacle to downsizing the element substrate or downsizing the entire electro-optical device.
[0008]
The present invention has been made in view of the above problems. For example, an electro-optical panel driving circuit capable of reducing adverse effects on image quality due to heat generated in a phase difference correction circuit provided in the electro-optical panel driving circuit, It is an object of the present invention to provide an electro-optical device including the driving circuit and an electro-optical panel, and various electronic apparatuses including the electro-optical device.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a drive circuit for a first electro-optical panel according to the present invention includes a pixel electrode, a switching element that controls switching of the pixel electrode, and an image signal via the switching element on the pixel electrode. An electro-optical panel driving circuit for driving an electro-optical panel having a data line for supplying a first clock signal, the first clock signal being formed on the substrate and having a phase different from that of the first clock signal. A plurality of phase difference correction circuits for correcting a phase difference between two clock signals, and a data line driving circuit for driving the data lines based on the first and second clock signals whose phase differences are corrected. And The data line driving circuit transfers the image signal as a sampling pulse that defines the timing to sample the image signal and supply it to the data line according to the clock period of the first and second clock signals with the phase difference corrected A series of shift register circuits including a plurality of shift register stages that sequentially output a signal by sequentially shifting one transfer start signal; Said plural The phase difference correction circuit ,in front A peripheral area outside the image display area along the side of the image display area in which the pixel electrodes are arranged in a plane on the recording substrate. The plurality of shift register stages are arranged in the same direction as each other, and each is connected to the shift register stages having the same number of stages. .
[0010]
According to the driving circuit of the first electro-optical panel of the present invention, during the operation, the sampling circuit samples the image signal in accordance with the sampling pulse output from the data line driving circuit. Thereby, the sampled image signal is supplied to the data line. Then, in the electro-optical panel, an image signal supplied via a data line is referred to as a thin film transistor (hereinafter referred to as “TFT” as appropriate) in accordance with a scanning signal supplied via a separate scanning line, for example. ) And the like are supplied to the pixel electrode through the switching element. As a result, image display by active matrix driving becomes possible.
[0011]
During such operation, the phase difference between the first clock signal before being input to the data line driving circuit and the second clock signal that is the inverted clock signal, for example, is corrected by the phase difference correction circuit. Is done. Accordingly, it is possible to input the first and second clock signals in an ideal state very close to an assumed phase difference (for example, a phase difference of 180 degrees) to the data line driving circuit, and thereby the data line driving circuit. It is possible to carry out the driving operation with high accuracy.
[0012]
In particular, the phase difference correction circuit is divided into at least two circuit portions. In addition, the at least two circuit portions are arranged in the peripheral region along the side of the image display region that is normally rectangular on the substrate. For example, at least two circuit portions are arranged along one side of the image display area close to one side of the element substrate on which the external circuit input terminals are arranged. Therefore, as in the prior art, one phase difference correction circuit is arranged at a predetermined position in the peripheral region, and is divided into at least two circuit portions as compared with the case where heat is generated from almost one place or one region. In addition, heat generation is performed in a wide area by the amount arranged along the side of the image display area. For this reason, according to the present invention, the situation in which the display contrast is different from other places due to a local temperature rise due to heat generation occurs, the number of divided circuit parts and the phase correction for the sides of the image display area It can be effectively reduced or prevented according to the length of the circuit. Thereby, it is possible to effectively prevent the occurrence of contrast spots in the image display area, and high-quality image display is possible. As in the prior art described above, the occurrence of contrast spots near the corners of the image display area where the phase difference correction circuit is arranged is hardly or not at all.
[0013]
In other words, even if a large current flows in accordance with the amount of correction of the phase difference in the inverter circuit or the like constituting the phase difference correction circuit, even if a large amount of heat is generated by this, the above-described phase difference correction circuit With this configuration, the influence on the image display can be hardly or practically not surfaced, which is very convenient practically.
[0014]
As a result, according to the first electro-optical panel drive circuit of the present invention, it is possible to reduce adverse effects on image quality due to heat generated in the phase difference correction circuit provided in the drive circuit of the electro-optical panel.
[0017]
One of the drive circuits for the first electro-optical panel of the present invention In the aspect, a sampling circuit that samples the image signal according to the sampling pulse and supplies the image signal to the data line may be further provided on the substrate.
[0018]
According to this configuration, the sampling circuit samples the image signal in accordance with the sampling pulse sequentially output from the shift register circuit.
[0021]
Another drive circuit for the first electro-optical panel of the present invention In an aspect, said Multiple phase difference correction circuits Are arranged along the side, and Each of a plurality of phase difference correction circuits Are provided corresponding to each of the plurality of shift register stages.
[0022]
With this configuration, a plurality of at least two circuit portions are provided corresponding to each of the plurality of shift register stages. Such a shift register stage is provided for each bundle of a plurality of data lines that are simultaneously driven in parallel-serial development, for example. For example, a shift register stage is provided for each bundle of data lines such as 6 simultaneous drive, 12 simultaneous drive, and 24 simultaneous drive. Incidentally, in the case of six simultaneous driving, there are as many shift register stages as the total number of data lines divided by 6, and the phase difference correction circuit is divided into the same number of circuit portions. Accordingly, heat generation that is equalized along the side occurs corresponding to the arrangement state of the plurality of shift register stages. For this reason, it is possible to effectively reduce or prevent the occurrence of a situation in which the display contrast is different from that in other places due to a local temperature rise accompanying heat generation.
[0023]
In another aspect of the first electro-optical panel drive circuit of the present invention, Multiple phase difference correction circuits Are arranged symmetrically with respect to the center of the side. Phase difference correction circuit Consists of.
[0024]
According to this aspect, since the at least two circuit portions are arranged at positions symmetrical with respect to the center of the side of the image display area, the left and right symmetry or the vertical symmetry with respect to the side is centered on the center. An equalized fever occurs. For this reason, it is possible to effectively reduce or prevent the occurrence of a situation in which the display contrast differs in the left-right direction or the up-down direction due to a local temperature rise accompanying heat generation.
[0025]
In this embodiment, the two Phase difference correction circuit May be arranged at both ends of the side.
[0026]
According to this configuration, the local abnormal portion of the contrast becomes less noticeable by causing heat generation from the circuit portion in the vicinity of both the left and right corners in the image display region or in the vicinity of both the upper and lower corners.
[0027]
In another aspect of the drive circuit for the first electro-optical panel of the present invention, the phase difference is formed on the substrate and is used to input the first and second clock signals in the phase difference correction circuit. A signal wiring having one end connected to the correction circuit; and an external circuit connection terminal formed on the substrate and connected to the other end of the signal wiring, the phase difference correction circuit, The signal wiring and the external circuit connection terminal are arranged in a plane so that the distance from the phase difference correction circuit to the external circuit connection terminal is within 10 mm, and the external circuit connection terminal is It functions as a heat dissipation path for radiating heat from the phase difference correction circuit via the signal wiring.
[0028]
According to this aspect, the heat generated in the phase difference correction circuit is guided to the external circuit connection terminal using the signal wiring as a heat dissipation path. Therefore, for example, by constructing the external circuit connection terminal as a metal pad having a relatively large area, it is possible to efficiently radiate heat through the signal wiring as the heat dissipation path and the external circuit connection terminal. In addition, since the distance from the phase difference correction circuit to the external circuit connection terminal is set to a relatively short distance of 10 mm or less, as a heat dissipation path for heat generated in the phase difference correction circuit, the external circuit connection terminal Everything can be dominant. As a result, it is possible to effectively reduce or prevent the occurrence of display contrast spots due to a local temperature rise accompanying heat generation in the phase difference correction circuit.
[0029]
In this aspect, the external circuit connection terminal may be configured to be connected with a flexible connector that conducts heat from the phase difference correction circuit and functions as a heat radiating unit via the signal wiring. Good.
[0030]
If comprised in this way, since a flexible connector functions also as thermal radiation means, such as a thermal radiation fin, efficient thermal radiation becomes possible via the signal wiring and external circuit connection terminal as a thermal radiation path | route. As a result, it is possible to effectively reduce or prevent the occurrence of display contrast spots due to a local temperature rise accompanying heat generation.
[0031]
In the aspect according to the external circuit connection terminal described above, the distance may be configured to be within 2 mm.
[0032]
With this configuration, the distance from the phase difference correction circuit to the external circuit connection terminal is set to a very short distance of 2 mm or less. What leads to the circuit connection terminal can be made more dominant.
[0033]
In another aspect of the first electro-optical panel drive circuit of the present invention, Multiple phase difference correction circuits Is in parallel with two identical clock signal lines to which the first or second clock signal is respectively supplied. Is provided . Accordingly, although the phase difference correction circuit is divided into a plurality of circuit portions, it is possible to prevent a situation where a clock signal or an inverted clock signal having the same phase or wavelength is input between these circuit portions.
[0034]
However, a plurality of clock signal lines to which the first clock signal is supplied may be wired, or a plurality of clock signal lines to which the second clock signal is supplied may be wired.
[0040]
In order to solve the above problems, an electro-optical device according to the present invention provides the above-described first of the present invention. 1's An electro-optical panel drive circuit (including various aspects thereof) and the electro-optical panel are provided.
[0041]
According to the electro-optical device of the present invention, the above-described first of the present invention. 1's Since the electro-optical panel drive circuit is provided, adverse effects due to heat generation of the phase difference correction circuit are reduced, and high-quality image display is possible.
[0042]
In order to solve the above-described problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).
[0043]
Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a projection display device, a liquid crystal television, a mobile phone, an electronic notebook, a word processor, and a viewfinder type capable of displaying a high-quality image. Alternatively, various electronic devices such as a monitor direct-view video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.
[0044]
Such an operation and other advantages of the present invention will become apparent from the embodiments described below.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the present invention is applied to a TFT active matrix driving type liquid crystal device.
[0046]
(First embodiment)
A first embodiment of the electro-optical device according to the invention will be described with reference to FIGS. 1 to 8.
[0047]
First, the overall configuration of the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing the overall configuration of the liquid crystal device according to this embodiment.
[0048]
As shown in FIG. 1, the liquid crystal device includes a liquid crystal panel 100, a timing generator 200, and an image signal processing circuit 300.
[0049]
In the liquid crystal panel 100, an element substrate on which a TFT 116 is formed as a switching element and a counter substrate are pasted with their electrode formation surfaces facing each other with a certain gap therebetween, and liquid crystal is sandwiched between the gaps. The timing generator 200 outputs various timing signals used in each unit, and a timing signal output unit that is a part of the timing generator 200 generates a dot clock that scans each pixel as a minimum unit clock. In particular, the transfer clock CLX according to the present embodiment is generated based on the dot clock. When one system image signal VID is input, the image signal processing circuit 300 performs serial-parallel conversion on the six-phase image signals VID1 to VID6 and outputs them.
[0050]
Particularly in the present embodiment, the liquid crystal panel 100 is a drive circuit built-in type, and includes a scanning line drive circuit 130, a sampling circuit 140, and a data line drive circuit 150 as the drive circuit 120 on the element substrate, and further includes a clock. A signal phase difference correction circuit 500 is provided.
[0051]
In FIG. 1, the clock signal phase difference correction circuit 500 is schematically shown as a block as a part of the block diagram, but the actual layout and shape on the element substrate and the operational effects relating to the heat generation are described. This will be described in detail later.
[0052]
The liquid crystal panel 100 further includes data lines 114 and scanning lines 112 wired vertically and horizontally in an image display area 110 occupying the center of the element substrate, and is arranged in a matrix at each pixel corresponding to the intersection. A pixel electrode 118 and a TFT 116 for controlling the switching of the pixel electrode 118 are provided. The image signals supplied to the image signal supply lines VID1 to VID6 are sampled by the sampling circuit 140 according to the sampling signals S1, S2,. It is comprised so that it may supply.
[0053]
The data line 114 to which the image signal is supplied in this way is electrically connected to the source electrode of the TFT 116, while the scanning line 112 to which the scanning signal is supplied is electrically connected to the gate electrode of the TFT 116. In addition, the pixel electrode 118 is connected to the drain electrode of the TFT 116. Each pixel is composed of a pixel electrode 118, a common electrode formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes. As a result, each pixel corresponds to each intersection of the scanning line 112 and the data line 114. Thus, they are arranged in a matrix.
[0054]
In order to prevent the held image signal from leaking, a storage capacitor (not shown) may be added in parallel with the liquid crystal capacitor formed between the pixel electrode 118 and the counter electrode. For example, since the voltage of the pixel electrode 118 is held by the storage capacitor for a time that is three orders of magnitude longer than the time when the source voltage is applied, the holding characteristics are improved, and as a result, a high contrast ratio is realized. .
[0055]
The driving circuit 120 includes a scanning line driving circuit 130, a sampling circuit 140, and a data line driving circuit 150 in a peripheral area located around the image display area 110. The active elements of these circuits can be formed by a combination of a p-channel TFT and an n-channel TFT. Therefore, if they are formed by a common manufacturing process with the TFT 116 that switches pixels, integration, manufacturing costs, and elements are reduced. This is advantageous in terms of uniformity of the image quality.
[0056]
Here, the scanning line driving circuit 130 of the driving circuit 120 has a shift register, and the clock signal CLY from the timing generator 200 and its inverted clock signal CLY. _INV The scanning signal is sequentially output to each scanning line 112 based on the transfer start pulse DY and the like.
[0057]
Next, the configuration and operation of the sampling circuit 140 and the data line driving circuit 150 of this embodiment will be described with reference to FIGS. FIG. 2 is a block diagram showing details of the sampling circuit and the data line driving circuit according to this embodiment, and FIG. 3 is a timing chart showing changes with time of various signals related to them.
[0058]
As shown in FIG. 2, in this embodiment, the data line driving circuit 150 includes a bidirectional shift register 160 for enabling the data lines 114 to be sequentially driven from both directions. The shift direction is determined by the direction control signal D. When the direction indication signal D is at a high level, the transfer start signal SP is input to the shift register 160 from the left side, and the shift register 160 is sequentially shifted from left to right, and is output as transfer signals SR1 to SRn from each output stage of the shift register 160. Is done. Inversion direction control signal D _INV Is positive, SP is input from the right direction of the shift register 160 and is sequentially shifted from right to left. SP is input and shifted sequentially from right to left.
[0059]
The transfer signals SR1 to SRn output from the shift register 160 are supplied to enable circuits 170a and 170b. Enable signals ENB1 and ENB2 are input to the other inputs of the enable circuits 170a and 170b, respectively. As a result, the data line 114 is driven only when the transfer signals SR1 to SRn are output and the enable signal ENB1 or ENB2 is output. That is, the enable signal ENB1 or ENB2 controls the data line 114 to be activated when the image signal VID is stably output.
[0060]
The transfer signals SR1 to SRn are ANDed with the enable signals by the enable circuits 170a and 170b, and then the data line drive signal or the sampling circuit drive signal (hereinafter referred to as “sampling circuit”) which is an example of the “sampling pulse” according to the present invention. (Referred to as “signal”) are supplied to the sampling circuit 140 as S1 to Sn. The sampling circuit 140 includes a plurality of single-channel TFTs 141 for sampling, that is, as sampling switches. Six data lines 114 are grouped into one group, and the image signals VID1 to VID6 developed in six phases according to the sampling signals S1 to Sn are sampled to the data lines 114 belonging to these groups, and sequentially supplied to the data lines 114. To do. Specifically, the sampling circuit 140 is provided with a switch 141 made of the TFT at one end of each data line 114, and the source electrode of each switch 141 is a signal line to which any one of the image signals VID1 to VID6 is supplied. The drain electrode is connected to one data line 114. The gate electrode of each switch 141 is connected to one of signal lines to which sampling signals S1 to Sn are supplied corresponding to the group. In the present embodiment, since the image signals VID1 to VID6 are supplied at the same time, they are simultaneously sampled by the sampling signal S1.
[0061]
In the case where the image signals VID1 to VID6 are supplied at the sequentially shifted timing, they are sequentially sampled by the sampling signals S1, S2,.
[0062]
As shown in the timing chart of FIG. 3, the transfer start signal SP input to the shift register 160 is a data line transfer clock CLX (hereinafter simply referred to as “transfer clock CLX”) and its inverted clock signal CLX. _INV , The data line transfer signals (hereinafter referred to as “transfer signals”) SR1 to SRn, which are shifted in half cycle units of the transfer clock CLX and delayed from each output stage of the shift register 160 by the half cycle of the transfer clock, are sequentially output. The
[0063]
The transfer signals SR1 to SRn are ANDed with the enable signal ENB by the enable circuits 170a and 170b in order to synchronize the drive period of the data line 114 with the stable output period of the image signals VID1 to VID6. Output as Sn. As a result, the image signal and the sampling signal (for example, VID1 to VID6 and S1) are synchronized and correct display is possible.
[0064]
In this embodiment, the ENB1 or ENB2 is supplied in accordance with the even or odd stages of the shift register 160. However, sampling may be performed with one ENB signal. Alternatively, each of the transfer signals SR1 to SRn output from each stage SRS (i) (where i = 1, 2, 3,... N) of the shift register 160 is divided into a plurality and output in parallel. A plurality of sampling signals obtained by ANDing a plurality of enable signals corresponding to the number may be output. That is, each of the significant SRS (i) of the shift register 160 controls a plurality of sampling circuit groups, and the number of stages of the shift register 160 can be reduced.
[0065]
Thus, the “shift register stage” according to the present invention corresponds to the stage SRS (i) of the shift register 160 as shown in FIG. 2 in the present embodiment.
[0066]
Next, the configuration and operation of the clock phase difference correction circuit according to the present embodiment will be described with reference to FIGS. 4 to 7 in addition to FIG. FIG. 4 is a circuit diagram showing a configuration of the clock phase difference correction circuit according to the present embodiment, and FIG. 5 is a timing chart showing changes with time of various signals related to the clock phase difference correction circuit. FIG. 6 is a circuit diagram for explaining the load capacity of each signal path in the clock phase difference correction circuit according to the present embodiment. FIG. 7 shows the second buffer in the clock phase difference correction circuit according to the present embodiment. It is a circuit diagram at the time of comprising a circuit with a multistage inverter circuit.
[0067]
In the liquid crystal device of this embodiment, as shown in FIG. 1, CLX and CLX which are input units for supplying a clock signal and an antiphase clock signal are provided. _INV And a clock phase difference correction circuit 500 having a bistable circuit is provided between the data line driving circuit 150 and the driving means having the shift register. The clock phase difference correction circuit 500 includes a clock signal CLX and an antiphase clock signal CLX supplied from an external control circuit. _INV These phases are adjusted by the clock phase difference correction circuit 500 and then supplied to the data line driving circuit 150. Therefore, a good image signal writing operation to each pixel is performed without causing the data line driving circuit 150 and the scanning line driving circuit 130 to malfunction.
[0068]
As shown in FIG. 4, the clock signal phase difference correction circuit 500 of this embodiment includes, for example, a first buffer circuit 501, a bistable circuit 502, and a second buffer circuit 503. The inverters 501a, 501b, 502a, 502b, 503a and 503b are configured.
[0069]
As shown in FIG. 5, the clock signal CL is an antiphase clock signal CL. _INV On the other hand, even if a phase difference occurs for the period T at the points R1 and R1, the phase difference is corrected by the bistable circuit 502 in this embodiment, and at the points R3 and R3 ′ output from the bistable circuit 502, Little or no phase difference occurs in practice.
[0070]
In the clock signal phase difference correction circuit 500, the clock signal CL and the anti-phase clock signal CL in the buffer circuit 501 formed of the inverters 501a and 501b. _INV The output of one inverter 502a of the bistable circuit 502 is supplied to the input of the other inverter 502b, and the output of the other inverter 502b is supplied to the input of the one inverter 502a, respectively. By doing so, the phase difference is eliminated by applying positive feedback to the input signals of the respective inverters 502a and 502b.
[0071]
In the clock signal phase difference correction circuit 500, the second buffer circuit 503 is provided after the bistable circuit 502, and the function of the second buffer circuit 503 prevents a decrease in driving capability of the bistable circuit 502. is doing. That is, the clock signal line is routed from the bistable circuit 502, and the clock signal CL and the antiphase clock signal CL are sent to each driving circuit. _INV Clock signal CL and anti-phase clock signal CL due to the capacity of the clock signal line. _INV However, according to the present embodiment, a decrease in the driving capability of the bistable circuit 502 is prevented by the second buffer circuit 503, and the clock signal CL and the antiphase clock signal CL are prevented. _INV Can be satisfactorily supplied to each drive circuit.
[0072]
As shown in FIG. 6, when the clock phase difference correction circuit 500 adopts the above-described configuration, the on-resistances of the inverter circuits 503a and 503b of the second buffer circuit 503 are set as low as possible. preferable. This is because if the on-resistances of the final stage inverter circuits 503a and 503b are high, the output signal is lost, the voltage of the signal applied to the clocked inverter of the bidirectional shift register 160 is lowered, and the bidirectional shift register 160 is It is because it becomes impossible to drive. Therefore, it is necessary to design the inverter circuits 503a and 503b to have sufficient driving capability with respect to the load and driving frequency of the clock signal line electrically connected to the second buffer circuit 503.
[0073]
Further, the capacitive load of the signal transmission path constituted by the inverters A, B and C or the inverters A ′, B ′ and C ′ shown in FIG. It is preferable to design so that the capacity load of the transmission path is the same. Therefore, it is preferable to design the inverters A, A ′, B, and B ′ to have substantially the same size. This is to ensure that the phase difference can be corrected without making the potential of either path dominant.
[0074]
Further, the inverter circuits 503a and 503b constituting the second buffer circuit 503 of the clock signal phase difference correction circuit 500 may have one stage, and when the capacitance added to the clock signal line and the antiphase clock signal line is large, For example, as shown in FIG. 7, a plurality of stages of inverter circuits may be connected in cascade, and then connected to the clock signal line and the antiphase clock signal line. At this time, the cascade-connected inverter circuits are designed to be about 2 to 4 times larger than the size of the preceding inverter circuit. In the case of the CMOS cascade, if the size of the inverter circuit of the next stage electrically connected to the inverter circuit of the own stage is increased by about e (2.72) times, the total number of the second buffer circuits 503 is increased. The delay time can be minimized (e times theorem). For example, in the example of FIG. 7, the inverter D (D ′) may be formed to have a size of the inverter C (C ′) × e (2.72) times. Further, the inverter E (E ′) is preferably formed in a size that is twice as large as the inverter D (D ′) × e (2.72). Further, at this time, it is preferable to form the on-resistance of the inverter E (E ′) in the final stage as small as possible.
[0075]
As described above, the clock phase difference correction circuit 500 of the present embodiment has the clock signal CLX and the anti-phase clock signal CLX. _INV In order to adjust the phase of the clock signal line, the bistable circuit 502 is configured to apply a positive feedback to the input signal by routing the clock signal line. Further, in order to supplement the driving capability according to the capacity and the driving frequency of the clock signal line. In addition, the inverter is connected in multiple stages. Accordingly, since the clock phase difference correction circuit 500 has a relatively large power consumption, the energy is dissipated as heat. Therefore, in the present embodiment, in order to prevent contrast spots and the like due to the temperature difference in the image display area 110 due to such heat generation from the clock phase difference correction circuit 500, a configuration in which heat generation sources are appropriately distributed in a plane. And an arrangement method is adopted.
[0076]
The configuration and arrangement method of such a clock phase difference correction circuit 500 will be described below with reference to FIG. FIG. 8 is a block diagram showing an arrangement example of the clock phase difference correction circuit 500 in the liquid crystal panel 100. FIG. 8 shows only the connection method and the relative positional relationship between the main components in the liquid crystal panel 100. Details of the relationship between the sizes of the components and the distances between the components and the following description will be given. Other signal lines that are not related are not shown.
[0077]
As shown in FIG. 8, in this embodiment, two clock phase difference correction circuits 500 are provided in parallel on the same clock signal line in the previous stage of the data line driving circuit 150. That is, the clock phase difference correction circuit 500 includes the image display area 110 in the peripheral area on the element substrate as shown as “phase difference correction circuit L” and “phase difference correction circuit R” in the drawing. It is arranged near both ends of the lower side. At this time, the clock signal lines (CLX, CLX) output from the respective clock phase difference adjustment circuits 500 arranged on the left and right sides. _INV ), Each stage SRS (i) of the bidirectional shift register 160 is connected in parallel.
[0078]
As described above, the clock phase difference correction circuit 500 is divided into two left and right parts, so that the heat generation sources are distributed with respect to the image display region 100. Therefore, the temperature difference (temperature distribution gradient) in the horizontal direction along the substrate surface in the image display region 110 is reduced, and contrast spots caused by the difference can be suppressed.
[0079]
More specifically, the bidirectional shift register 160 connected to each of the divided clock phase difference correction circuits 500 is connected to be equal in the number of stages as shown in FIG. In addition, two clock phase difference correction circuits 500 are linearly arranged in the same direction (horizontal direction) as the arrangement of each stage SRS (i) of the bidirectional shift register 160, and the image display area 110 is further displayed. Are arranged symmetrically with respect to the center line. By arranging in this way, it is possible to prevent the heat source from localizing in the image display area 110 and to reduce the temperature difference (temperature distribution gradient) in the horizontal direction in the image display area 110. It becomes.
[0080]
Further, the number of stages of the bidirectional shift registers 160 driven by the respective clock phase difference correction circuits 500 is halved on the left and right, and the clock signal lines between the individual clock phase difference correction circuits 500 and the bidirectional shift registers 160. Are substantially equal on the left and right, so that the capacitive load of the clock signal line is equally divided in half. For this reason, it is possible to set the driving capabilities of the left and right individual clock phase difference correction circuits 500 to be equal. Therefore, as compared with the case where all the stages SRS (i) of the bidirectional shift register 160 are driven by one clock phase difference correction circuit 500, each clock phase difference correction circuit 500 may be half in size. Individual power consumption and calorific value can be reduced to half.
[0081]
As described above, according to the first embodiment, due to the divided arrangement of the clock phase difference correction circuit 500, the heat generation amount of each heat source is reduced and the temperature difference (temperature distribution gradient) in the horizontal direction in the image display region 110 is reduced. By reducing the contrast, contrast spots caused by it can be prevented.
[0082]
(Second Embodiment)
A second embodiment of the electro-optical device of the invention will be described with reference to FIG. The second embodiment differs from the first embodiment described above in the number and arrangement of clock phase difference correction circuits 500 in the liquid crystal panel 100, and the other configurations and operations are the same. For this reason, below, the structure different from 1st Embodiment is demonstrated. FIG. 9 is a block diagram showing an arrangement example of a plurality of clock phase difference correction circuits 500 in the liquid crystal panel 100. FIG. 9 shows only the connection method and relative positional relationship between the main components in the liquid crystal panel 100, and details of the relationship between the sizes of the components and the distances between the components and the following explanations. The other signal lines not related to are omitted from the illustration as in the case of FIG.
[0083]
As shown in FIG. 9, in this embodiment, the clock phase difference correction circuit 500 is further divided into a plurality of parts as compared with the first embodiment and provided in parallel on the same clock signal line. The clock phase difference correction circuit 500 is divided into n pieces with respect to the n stages of the bidirectional shift register 160, and one clock phase difference correction circuit 500 is connected to each stage of the bidirectional shift register 160. Yes.
[0084]
As described above, the clock phase difference correction circuit 500 is further divided into a plurality of parts, so that the amount of heat generated per clock phase difference correction circuit 500 is reduced in proportion to the number of divisions. As compared with the above, the heat source is more finely dispersed and distributed. Therefore, the temperature distribution in the horizontal direction in the image display region 110 becomes uniform, and it becomes easier to suppress contrast spots caused by the temperature difference without localizing a large heat generation source.
[0085]
More specifically, the bidirectional shift register 160 connected to each divided clock phase difference correction circuit 500 is connected so that the number of stages is equal. A plurality of divided clock phase difference correction circuits 500 are arranged in a plurality of lines in the same direction (horizontal direction) as the arrangement of each stage of the bidirectional shift register 160, and further on the center line of the image display area 110. They are arranged in line symmetry. By arranging in this way, it is possible to prevent the heat source from being localized in the image display area 110 and to reduce the temperature difference (temperature distribution gradient and variation) in the horizontal direction in the image display area 110. It becomes possible. Furthermore, the number of stages of the bidirectional shift registers 160 driven by the respective clock phase difference correction circuits 500 is the same, and the length of the clock signal line to the corresponding bidirectional shift register 160 is the individual clock phase difference correction circuit. Since the capacitive loads of the clock signal lines are evenly divided, the driving capabilities of the individual clock phase difference correction circuits 500 can be set equal. Therefore, as compared with the case where all the stages of the bidirectional shift register 160 are driven by one clock phase difference correction circuit 500, each clock phase difference correction circuit 500 is reduced in proportion to the number of divisions in its size. be able to. Individual power consumption and heat generation can also be suppressed to 1 / n.
[0086]
As described above, according to the second embodiment, the heat generation amount of each heat generation source and the horizontal temperature difference (temperature distribution gradient in the image display region 110) are obtained by dividing the clock phase difference correction circuit 500 into a plurality of parts. ) Is reduced, it is possible to prevent contrast spots resulting therefrom.
[0087]
(Third embodiment)
A third embodiment of the electro-optical device of the invention will be described with reference to FIG. The third embodiment differs from the first embodiment described above in the number and method of arrangement of the clock phase difference correction circuit 500 in the liquid crystal panel 100, and the other configurations and operations are the same. For this reason, below, the structure different from 1st Embodiment is demonstrated. FIG. 10 is a block diagram showing an arrangement example of a plurality of clock phase difference correction circuits 500 in the liquid crystal panel 100. FIG. 10 shows only the connection method and the relative positional relationship between the main components in the liquid crystal panel 100. The details of the relationship between the size of each component and the distance between the components and the following description will be given. The other signal lines not related to are omitted from the illustration as in the case of FIG.
[0088]
As shown in FIG. 10, in this embodiment, the clock phase difference correction circuit 500 is further divided into a plurality of parts as compared with the first embodiment and provided in parallel on the same clock signal line. The clock phase difference correction circuit 500 is divided into n / 2 pieces with respect to the n stages of the bidirectional shift register 160, and is provided in parallel on the same clock line. For one clock phase difference correction circuit 500, two stages of the bidirectional shift register 160 are connected in parallel.
[0089]
As described above, the clock phase difference correction circuit 500 is further divided into a plurality of parts, so that the amount of heat generated per clock phase difference correction circuit 500 is reduced in proportion to the number of divisions. As compared with the above, the heat source is more finely dispersed and distributed. Therefore, the temperature distribution in the horizontal direction in the image display region 110 becomes uniform, and it becomes easier to suppress contrast spots caused by the temperature difference without localizing a large heat generation source.
[0090]
More specifically, as in the case of the second embodiment, the heat source is prevented from being localized with respect to the image display area 110, and the temperature difference (temperature distribution gradient and temperature distribution) in the horizontal direction in the image display area 110 is prevented. (Variation) can be reduced, and the driving capability of each clock phase difference correction circuit 500 can be set equal. Therefore, as compared with the case where all the stages of the bidirectional shift register 160 are driven by one clock phase difference correction circuit 500, each clock phase difference correction circuit 500 is reduced in proportion to the number of divisions in its size. be able to. And unlike the case of 2nd Embodiment, it becomes possible to suppress each power consumption and the emitted-heat amount to 1 / (n / 2).
[0091]
As described above, according to the third embodiment, the amount of heat generated by each heat source and the horizontal temperature difference (temperature distribution gradient) in the image display region 110 are obtained by further dividing the clock phase difference correction circuit 500 into a plurality of parts. By reducing, it becomes possible to prevent contrast spots resulting therefrom.
[0092]
(Overall configuration of liquid crystal device)
The overall configuration of the liquid crystal device according to the first and second embodiments of the present invention configured as described above will be described with reference to FIGS. FIG. 11 is a plan view of the TFT array substrate 10 viewed from the side of the counter substrate 20 together with the components formed thereon, and FIG. 12 is a cross-sectional view taken along the line HH ′ of FIG. .
[0093]
11 and 12, an image display region defined by a plurality of pixel electrodes 118 (that is, a liquid crystal device in which an image is actually displayed by a change in the alignment state of the liquid crystal layer 50 is formed on the liquid crystal device substrate 1. A sealing material 52 made of a photocurable resin that surrounds the liquid crystal layer 50 by bonding both substrates around the region) is provided along the image display region. A light-shielding frame light-shielding film 53 is provided between the image display area on the counter substrate 2 and the sealing material 52.
[0094]
When the liquid crystal device substrate 10 is placed in a light-shielding case in which an opening is provided later corresponding to the image display area, the frame light-shielding film 53 is formed on the opening of the case due to a manufacturing error or the like. A band-shaped light-shielding material having a width of at least 500 μm around the image display region so as not to be hidden behind the edge, that is, for example, to allow a displacement of about several hundred μm with respect to the case of the substrate 10 for the liquid crystal device It is formed from. Such a light-shielding frame light-shielding film 53 is formed on the counter substrate 20 by sputtering, photolithography, and etching using a metal material such as Cr (chromium) or Ni (nickel), for example. Or it forms from materials, such as resin black which disperse | distributed carbon and Ti (titanium) in the photoresist. Further, the light shielding frame 53 and the light shielding layer 23 may be formed on the liquid crystal device substrate 1. By adopting such a configuration, the bonding accuracy between the liquid crystal device substrate 1 and the counter substrate 2 can be ignored, and thus there is an advantage that the transmittance of the liquid crystal device does not vary.
[0095]
Scanning line drive circuits 130 are provided on both sides of the image display region 110 along the left and right sides. Here, when the driving delay of the scanning line 112 does not become a problem, the scanning line driving circuit 130 may be formed only on one side with respect to the scanning line 112.
[0096]
A data line driving circuit 150 and an external circuit connection terminal 102 for inputting an external signal and the like are provided along the lower side of the image display area in the area outside the sealing material 52. Scanning line driving circuits 130 are provided on both sides of the image display area along the two sides. Here, the data driving circuits 150 may be provided on both sides along the upper and lower sides of the image display area. At this time, for example, the odd-numbered data lines are electrically connected to one data line driving circuit 150, and the even-numbered data lines are electrically connected to the other data line driving circuit 150. Alternatively, it may be driven like a comb. Further, a plurality of wirings 105 for supplying power and driving signals to the scanning line driving circuit 130 are provided on the upper side of the image display area. In addition, a vertical conduction member 106 for providing electrical conduction between the liquid crystal device substrate 1 and the counter substrate 2 is provided at at least one corner of the counter substrate 2. The counter substrate 2 having substantially the same outline as the sealing material 52 is fixed to the liquid crystal device substrate 1 by the sealing material 52.
[0097]
In each of the above-described embodiments, a case where an external control circuit that outputs a clock signal, an image signal, or the like to the data line driving circuit 150 and the scanning line driving circuit 130 is provided outside the liquid crystal device will be described. However, the present invention is not limited to this, and the control circuit may be provided in the liquid crystal device.
[0098]
In particular, for the clock signal, only the clock signal may be supplied from an external control circuit, and a circuit for generating an anti-phase clock signal on the liquid crystal device substrate may be provided.
[0099]
(Embodiment related to external circuit connection terminal and flexible connector)
Next, the configuration and heat dissipation effect of the external circuit connection terminal 102 and the flexible connector connected thereto shown in FIGS. 11 and 12 in this embodiment will be described with reference to FIGS. 13 to 14. FIG. 13 is a perspective view showing the entire liquid crystal device and a connection state between the liquid crystal device and the flexible connector 600. FIG. 14 is a plan view showing an arrangement example of the clock phase difference correction circuit 500, and shows an A portion of FIG. 11 in an enlarged manner.
[0100]
As shown in FIG. 13, a flexible connector (FPC) 600 is connected to the external circuit connection terminal 102 via, for example, an anisotropic conductive film (ACF) 610 and the like, and an external signal is input. The flexible connector 600 has a good heat dissipation property because a metal film such as a copper foil having a good thermal conductivity is widely laminated on the insulating material as a lead-out wiring. Since it is in contact with 102, heat is easily released from the liquid crystal substrate, particularly from each circuit portion. Here, as described above, the clock phase difference correction circuit 500 in each embodiment of the present invention has relatively high power consumption and large heat generation compared to other data line driving circuits and the like. In order to prevent problems such as image contrast spots caused by the above, it is effective to release heat to the outside and perform cooling.
[0101]
Therefore, particularly in the present invention, the clock phase difference correction circuit 500 is provided in the vicinity of the external circuit connection terminal 102.
[0102]
Here, FIG. 14 shows an arrangement example of the clock phase difference correction circuit 500 in the peripheral portion of the external circuit connection terminal 102 and the data line driving circuit 110. FIG. 14- (a) shows an enlarged view of part A in FIG. 11, and shows an example in which two clock phase difference correction circuits 500 are arranged divided into left and right as in the first embodiment described above. . FIG. 14B shows an example in which the portion A is similarly enlarged, and a plurality of clock phase difference correction circuits are arranged linearly in parallel with the data line driving circuit as in the second embodiment described above. . As shown in FIG. 14- (a) or (b), the distance L from the clock phase difference correction circuit 500 to the external circuit connection terminal 102 is arranged to be within 10 mm. With this arrangement, the heat generated in the clock phase difference correction circuit 500 is guided to the external circuit connection terminal 102 using the clock signal wiring 103 as a heat dissipation path. Therefore, since the external circuit connection terminal 102 is composed of, for example, a metal pad having a relatively large area, it is possible to efficiently dissipate heat through the clock signal wiring 103 and the external circuit connection terminal 102 as a heat dissipation path. Is possible. In addition, since the distance from the clock phase difference correction circuit 500 to the external circuit connection terminal 102 is set to a relatively short distance of 10 mm or less, a heat dissipation path for heat generated in the clock phase difference correction circuit 500 is external. What reaches the circuit connection terminal 102 can be made more dominant. As a result, it is possible to effectively reduce or prevent the occurrence of display contrast spots due to a local temperature rise accompanying heat generation in the phase difference correction circuit.
[0103]
The distance L from the clock phase difference correction circuit 500 to the external circuit connection terminal 102 may be configured to be 2 mm or less. With this configuration, since the distance L from the clock phase difference correction circuit 500 to the external circuit connection terminal 102 is set to a very short distance, a heat dissipation path for heat generated in the phase difference correction circuit is set. What leads to the external circuit connection terminals can be made more dominant. Therefore, it is possible to more effectively reduce or prevent the occurrence of display contrast spots due to a local temperature rise accompanying heat generation.
[0104]
The liquid crystal device described above can be applied to a color liquid crystal projector or the like. In this case, three liquid crystal devices are used as RGB light valves, and each panel is for RGB color separation. The light of each color separated through the dichroic mirror is incident as incident light. Therefore, in each embodiment, the counter substrate 2 is not provided with a color filter. However, in the liquid crystal device, an RGB color filter may be formed on the counter substrate 2 together with the protective film in a predetermined region facing the pixel electrode 11 where the light shielding layer 23 is not formed. In this way, the liquid crystal device of this embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflective type color liquid crystal television other than the liquid crystal projector.
[0105]
Further, the switching element used in the liquid crystal device may be a positive stagger type or coplanar type polysilicon TFT, and this embodiment also applies to other types of TFT such as an inverted stagger type TFT or an amorphous silicon TFT. It is valid.
[0106]
Furthermore, in the liquid crystal device, the liquid crystal layer 50 is composed of nematic liquid crystal as an example. If polymer dispersed liquid crystal in which liquid crystal is dispersed as fine particles in a polymer is used, an alignment film, the polarizing film, A polarizing plate or the like is not necessary, and the advantages of high brightness and low power consumption of the liquid crystal device due to increased light utilization efficiency can be obtained.
[0107]
The data line driving circuit 10 and the scanning line driving circuit 130 are not provided on the liquid crystal device substrate 1, but are mounted on a liquid crystal device substrate, for example, on a driving LSI mounted on a TAB (tape automated bonding substrate). You may make it connect electrically and mechanically through the anisotropic conductive film provided in the peripheral part of 1. FIG.
[0108]
In the above-described embodiment, the configuration of the scanning line driving circuit 130 is not described in detail, but the configuration similar to that of the data line driving circuit 150 can be adopted particularly for the shift register portion.
[0109]
(Electronics)
Next, an embodiment of an electronic apparatus provided with the liquid crystal device 1 described in detail above will be described with reference to FIGS.
[0110]
First, FIG. 15 shows a schematic configuration of an electronic apparatus including the liquid crystal device 1 as described above.
[0111]
In FIG. 15, an electronic device includes a display information output source 1000, the above-described external display information processing circuit 1002, a display driving circuit 1004 including the above-described scanning line driving circuit 130 and data line driving circuit 150, the liquid crystal device 1, and a clock generation circuit. 1008 and a power supply circuit 1010 are provided. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs a television signal, and the like. Based on the clock signal, display information such as an image signal in a predetermined format is output to the display information processing circuit 1002. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit. The display information processing circuit 1002 receives the clock signal from the clock generation circuit 1008. A digital signal is sequentially generated from the display information input based on this, and is output to the display drive circuit 1004 together with the clock signal CLK. The display driving circuit 1004 drives the liquid crystal device 1 by the above-described driving method by the scanning line driving circuit 130 and the data line driving circuit 150. The power supply circuit 1010 supplies predetermined power to the above-described circuits. The display drive circuit 1004 may be mounted on the liquid crystal device substrate constituting the liquid crystal device 1, and in addition to this, the display information processing circuit 1002 may be mounted.
[0112]
As an electronic device having such a configuration, a liquid crystal projector shown in FIG. 16, a personal computer (PC) and engineering workstation (EWS) compatible with multimedia shown in FIG. 17, or a mobile phone, a word processor, a television, a viewfinder type, or Examples include a monitor direct-view video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, and a device equipped with a touch panel.
[0113]
Next, FIGS. 16 to 18 show specific examples of the electronic apparatus configured as described above.
[0114]
In FIG. 16, a liquid crystal projector 1100 as an example of an electronic device is a projection-type liquid crystal projector, and includes a light source 1110, dichroic mirrors 1113, 1114, reflection mirrors 1115, 1116, 1117, an incident lens 1118, a relay lens 1119, An exit lens 1120, liquid crystal light valves 1122, 1123, 1124, a cross dichroic prism 1125, and a projection lens 1126 are provided. The liquid crystal light valves 1122, 1123, and 1124 are prepared as three liquid crystal display modules including the liquid crystal device 1 in which the driving circuit 1004 described above is mounted on a substrate for a liquid crystal device, and each is used as a liquid crystal light valve. The light source 1110 includes a lamp 1111 such as a metal halide and a reflector 1112 that reflects light from the lamp 1111.
[0115]
In the liquid crystal projector 1100 configured as described above, the dichroic mirror 1113 that reflects blue light and green light transmits red light of white light flux from the light source 1110 and reflects blue light and green light. . The transmitted red light is reflected by the reflection mirror 1117 and is incident on the liquid crystal light valve 1122 for red light. On the other hand, of the color light reflected by the dichroic mirror 1113, green light is reflected by the dichroic mirror 1114 that reflects green light and enters the liquid crystal light valve 1123 for green light. Blue light also passes through the second dichroic mirror 1114. For blue light, in order to prevent light loss due to a long optical path, light guiding means 1121 including a relay lens system including an incident lens 1118, a relay lens 1119, and an output lens 1120 is provided, and blue light is transmitted through the blue light. The light enters the light liquid crystal light valve 1124. The three color lights modulated by the respective light valves enter the cross dichroic prism 1125. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. These dielectric multilayer films combine the three color lights to form light representing a color image. The synthesized light is projected onto the screen 1127 by the projection lens 1126 which is a projection optical system, and the image is enlarged and displayed.
[0116]
In FIG. 17, a laptop personal computer 1200, which is another example of an electronic device, houses a liquid crystal display 1206 in which the above-described liquid crystal device 1 is provided in a top cover case, a CPU, a memory, a modem, and the like, and a keyboard. And a main body 1204 in which 1202 is incorporated.
[0117]
Further, as shown in FIG. 18, a TCP (Tape with an IC chip 1324 mounted on a polyimide table 1322 having a metal conductive film formed on one of two transparent substrates 1304a and 1304b constituting a substrate 1304 for a liquid crystal device. Carrier Package) 1320 can be connected to produce, sell, and use as a liquid crystal device that is a component for electronic equipment.
[0118]
As described above, in addition to the electronic devices described with reference to FIGS. 16 to 18, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, a workstation, a mobile phone A telephone, a videophone, a POS terminal, a device provided with a touch panel, and the like are examples of the electronic device illustrated in FIG.
[0119]
The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the gist or concept of the invention that can be read from the claims and the entire specification. The device, its driving circuit and electronic equipment are also included in the technical scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device of the present invention.
FIG. 2 is a logic circuit diagram showing details of a data line driving circuit 150 and a sampling circuit 140 of FIG.
3 is a timing chart showing a state of main signals in the logic circuit diagram of FIG. 2. FIG.
4 is a circuit diagram showing a configuration of a clock phase difference correction circuit in the liquid crystal device of FIG. 1. FIG.
FIG. 5 is a timing chart showing signals at respective positions in the circuit of FIG. 4;
FIG. 6 is a circuit diagram for explaining a load capacity of each signal path in the clock phase difference correction circuit.
FIG. 7 is a circuit diagram in the case where the second buffer circuit is configured by a multi-stage inverter circuit in the clock phase difference correction circuit.
FIG. 8 is a block diagram showing an arrangement example of clock phase difference correction circuits in the first embodiment.
FIG. 9 is a block diagram showing an arrangement example of clock phase difference correction circuits in the second embodiment.
FIG. 10 is a block diagram showing an arrangement example of clock phase difference correction circuits in the third embodiment.
FIG. 11 is a plan view showing an overall configuration of a liquid crystal device.
12 is a cross-sectional view showing the overall configuration of the liquid crystal device, and is a cross-sectional view taken along the line HH ′ of FIG.
FIG. 13 is a perspective view showing the entire liquid crystal device and a connection state between the liquid crystal device and a flexible connector.
14 is a plan view showing an arrangement example of the clock phase difference correction circuit 500, and shows an A portion of FIG. 11 in an enlarged manner. (A) shows the example of arrangement | positioning of the clock phase difference correction circuit in 1st Embodiment. FIG. 6B shows an arrangement example of the clock phase difference correction circuit in the second embodiment.
FIG. 15 is a block diagram showing a schematic configuration of an embodiment of an electronic apparatus according to the invention.
FIG. 16 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus.
FIG. 17 is a front view showing a personal computer as another example of an electronic apparatus.
FIG. 18 is a perspective view illustrating a liquid crystal display device using TCP as an example of an electronic apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 10 ... Substrate for liquid crystal device, 20 ... Counter substrate, 21 ... Common electrode, 23 ... Light shielding layer, 50 ... Liquid crystal layer, 52 ... Sealing material 53... Frame shading film, 100... Liquid crystal panel, 110... Image display area, 102... External circuit connection terminal, 103. ... Data line, 116 ... TFT, 118 ... Pixel electrode, 130 ... Scanning line drive circuit, 140 ... Sampling circuit, 141 ... Single channel TFT, 150 ... Data line Driving circuit 160... Bidirectional shift register 170... Enable circuit 200... Timing generator 300... Image signal processing device 500. First bag § over circuit, 502 ... bistable circuit, 503 ... second buffer circuit, 600 ... flexible connectors, 610 ... anisotropic conductive film (ACF)

Claims (11)

Driving an electro-optical panel having a pixel electrode, a switching element for controlling the switching of the pixel electrode, and a data line for supplying an image signal to the pixel electrode via the switching element on the substrate A circuit,
A plurality of phase difference correction circuits which are formed on the substrate and correct a phase difference between a first clock signal and a second clock signal having a phase different from that of the first clock signal;
A data line driving circuit for driving the data line based on the first and second clock signals with the phase difference corrected, and
Wherein the data line driving circuit, according to the clock cycle of the first and second clock signal the phase difference is corrected, the transfer of a sampling pulse defining a timing of supplying to the data line by sampling the image signal A series of shift register circuits including a plurality of shift register stages that sequentially output a signal by sequentially shifting one transfer start signal ;
The plurality of phase difference correction circuits have the same direction as the arrangement of the plurality of shift register stages in a peripheral region outside the image display region along a side of the image display region in which the pixel electrodes are arranged in a plane on the substrate And an electro-optical panel drive circuit, wherein the shift register stages are connected to the shift register stages having the same number of stages.   The electro-optical panel drive circuit according to claim 1, further comprising a sampling circuit on the substrate for sampling the image signal in accordance with the sampling pulse and supplying the image signal to the data line. The plurality of phase difference correction circuits are arranged along the side,
3. The drive circuit for an electro-optical panel according to claim 1, wherein each of the plurality of phase difference correction circuits is provided corresponding to each of the plurality of shift register stages. It said plurality of phase difference correction circuit, electric according to any one of claims 1 to 3, characterized in that it consists of two phase-difference correcting circuit disposed at symmetrical positions with respect to the center of the sides Optical panel drive circuit. The electro-optical panel driving circuit according to claim 4 , wherein the two phase difference correction circuits are arranged at both ends of the side. A signal wiring formed on the substrate and having one end connected to the phase difference correction circuit for inputting the first and second clock signals in the phase difference correction circuit;
An external circuit connection terminal formed on the substrate and connected to the other end of the signal wiring;
The phase difference correction circuit, the signal wiring, and the external circuit connection terminal are arranged in a plane so that a distance from the phase difference correction circuit to the external circuit connection terminal is within 10 mm,
The external circuit connection terminals, the heat from the phase difference correcting circuit, electric according to any one of claims 1 5, characterized in that functions as a heat dissipation path for dissipating via the signal line Optical panel drive circuit. Wherein the external circuit connection terminals, according to claim 6, characterized in that the flexible connector heat from the phase difference correcting circuit through the signal lines functions as a heat dissipating means with the conduction is connected Electro-optical panel drive circuit. 8. The electro-optical panel drive circuit according to claim 6 , wherein the distance is within 2 mm. It said plurality of phase difference correction circuit, the first or the second clock signal with respect to two of the same clock signal lines are respectively supplied, according to claim 1 to 8, characterized in that provided in parallel The drive circuit for the electro-optical panel according to any one of the above. Electro-optical apparatus comprising the driving circuit and the electro-optical panel of the electro-optical panel according to any one of claims 1 to 9. An electronic apparatus comprising the electro-optical device according to claim 10 .

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