JP3484963B2 - Driving circuit for electro-optical device, electro-optical device, and electronic apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit of an electro-optical device such as a liquid crystal panel of an active matrix drive system by driving a thin film transistor (hereinafter referred to as TFT), an electro-optical device including the drive circuit, TECHNICAL FIELD The technical field of an electro-optical device in which a drive circuit is provided on a substrate or an electronic device using the electro-optical device belongs to the technical field of a drive circuit including a precharge circuit, an electro-optical device, and an electronic device. Belong to.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal panel of an active matrix driving system driven by TFT, a large number of scanning lines and data lines arranged vertically and horizontally and a large number of pixel electrodes corresponding to respective intersections of the scanning lines and data lines. Are provided on the TFT array substrate. In addition to these, various peripheral circuits having TFTs as constituent elements such as a scanning line driving circuit, a data line driving circuit, and a sampling circuit may be provided on such a TFT array substrate.

Of these peripheral circuits, the sampling circuit is a circuit for sampling an image signal in order to stably supply a high-frequency image signal to each data line at a predetermined timing in synchronization with the scanning signal. . In addition to the above, various peripheral circuits using TFTs or the like can be provided on the TFT array substrate from the viewpoints of improving image quality in liquid crystal display, reducing power consumption, reducing cost, and the like.

Further, the precharge circuit samples the image signal with respect to the data line by the sampling circuit for the purpose of improving the contrast ratio, stabilizing the potential level of the data line, reducing line unevenness on the display screen, and the like. This circuit reduces the load when writing the image signal to the data line by supplying the precharge signal (image auxiliary signal) at the timing preceding the timing when the image signal is written. In particular, the so-called 1H in which the voltage polarity of the data line, which is usually performed for AC driving the liquid crystal, is inverted and driven every horizontal scanning period.
In the inversion driving method, if a precharge signal of a predetermined potential is written in the data line in advance after the polarity of the image signal is switched in one horizontal blanking period before one horizontal effective display period, the image signal is The amount of charge required when writing to the data line can be significantly reduced.

Conventionally, since such a precharge is performed for all the data lines within one horizontal blanking period, the delay of the precharge signal due to the capacitance of the data lines,
In consideration of an increase in the driving load of the TFT of the precharge circuit for writing the precharge signal to the data line, a relatively long time, for example, at least 1.0 μsec or more, immediately after the start of the one horizontal retrace period. It was configured to supply the precharge signal to the data line.

However, as the definition of the liquid crystal panel becomes higher and the number of pixels in the horizontal direction becomes very large, the ratio of one horizontal effective display period in one horizontal scanning period becomes large and one horizontal blanking period becomes short. Therefore, the precharge signal cannot be sufficiently supplied to the data line.
There is also a problem that the number of data lines that need to be written at one time increases, and the driving load of the TFT of the precharge circuit that writes a precharge signal to the data lines increases. Further, since a large amount of current is supplied at one time, the potential of the power supply line becomes unstable. Furthermore, as the number of data lines for writing the precharge signal increases, the signal line for supplying the precharge signal to the data line becomes longer, and a resistance is added. There was a problem of deterioration. As a result, there is a problem in that the potentials written in the respective data lines vary, causing line unevenness on the display screen.

Therefore, for example, Japanese Patent Laid-Open No. 7-295520
As described in Japanese Patent Laid-Open Publication No. 2004-242242, a method of writing a precharge signal line-sequentially for each data line has been proposed prior to writing an image signal to each data line. An example of such a precharge circuit is disclosed.

According to this precharge circuit, the number of data lines for writing the precharge signal at one time is one, the driving load of the TFT of the precharge circuit can be reduced, and the potentials of the power supply line and the data line can be reduced. Can be stabilized.

[0009]

However, in the conventional method represented by the above publication, a circuit for sampling the precharge signal for each data line in order to write the precharge signal line by line for each data line. Then, a shift register for supplying a drive signal to the circuit in a line sequential manner is required. This conventional shift register is, for example, as disclosed in the above-mentioned publication, configured so that signals having the same width as the signal input to the first stage of the shift register are sequentially shifted without overlapping with each other. It had a complicated circuit configuration.

Therefore, when attempting to miniaturize the liquid crystal panel, the area of the peripheral circuit region provided outside the pixel region becomes small, so that a shift register having a very complicated circuit configuration as described above is used. Forming in a region severely limits the area for other circuits.
As a result, the precharge circuit for writing the precharge signal in the data line must be formed in a small area, and the size of the TFT configuring the precharge circuit must be reduced.

That is, since it is impossible to reduce the on-resistance of the TFT of the precharge circuit, the TFT concerned
However, there is a problem in that the pulse width of the drive signal for sampling the precharge signal must be maintained to some extent in order to reduce the current supply capability and to perform sufficient precharge.

However, in the high-speed display mode such as the EWS mode, one horizontal retrace line period is extremely short. Therefore, in order to keep the pulse width of the drive signal long, the precharge signal and the image signal are Would be written to the data line almost continuously, and the image signal would not be supplied correctly due to the influence of the precharge signal, resulting in a problem that the image would be adversely affected.

Further, since the circuit for shifting the sampling pulse has a complicated structure as described above, the area occupied by the circuit on the liquid crystal device also becomes large,
There is a problem that it is difficult to downsize the liquid crystal device. In particular, in the case of a configuration in which a circuit for shifting a sampling pulse of an image signal and a circuit for shifting a sampling pulse of a precharge signal are provided independently, it is necessary to input a clock signal for shifting to both circuits,
There is a problem that the area occupied by the circuit for shifting the sampling pulse of the precharge signal is further increased due to the routing of the pattern of the clock signal.

The present invention has been made in view of the above-mentioned problems, and even when the precharge signal is line-sequentially supplied to the data line, the precharge signal is supplied at a timing and a supply time within one horizontal blanking period. An object of the present invention is to provide a driving device of a liquid crystal device, a liquid crystal device, and an electronic device that can have a degree of freedom and can be further downsized.

[0015]

A driving circuit for an electro-optical device according to claim 1, wherein a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, and each of the data lines are provided. And a driving circuit of an electro-optical device comprising switching means connected to each scanning line and a pixel electrode connected to the switching means, for sampling the image signal and supplying the image signal to the data line. Sampling circuit, a first shift register for supplying a control signal to the sampling circuit, and a precharge signal to the data line prior to a sampling period for supplying the image signal to the data line. A precharge circuit and a second shift register for supplying a control signal to the precharge circuit are provided, and the first and second shift registers are provided. The data clock signal from a common clock signal supply lines, characterized by comprising supplied.

According to the drive circuit of the electro-optical device of the first aspect, the precharge signal is not deteriorated as in the case of writing the precharge signal to all the data lines at a time, so the precharge signal is written. The period can be shortened. Therefore, even when the high-speed display mode is adopted, sufficient precharge can be performed, and a sufficient period from the end of writing the precharge signal to the start of writing the image signal can be ensured. Allow writing.

Further, by shortening the writing period of the precharge signal, it is possible to deal with the high speed display mode, and by shortening the writing period of the precharge signal, it is possible to deal with the high speed display mode, and the first and second shifts are possible. Since the clock signal is supplied to the register from the common clock signal supply line, the occupied area is reduced with a simple configuration, and the electro-optical device can be downsized without arranging the clock signal supply line.

An electro-optical device according to a second aspect is connected to a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, each of the data lines and each of the scanning lines. And a sampling circuit for sampling the image signal and supplying it to the data line, the driving circuit of the electro-optical device comprising: switching means; and a pixel electrode connected to the switching means. A first shift register for supplying a control signal to the data line, a precharge circuit for supplying a precharge signal to the data line prior to a sampling period for supplying the image signal to the data line, and the precharge A second shift register for supplying a control signal to the circuit, and the first and second shift registers are provided between the first and second shift registers. Common clock signal supply lines for supplying a clock signal to the second shift register is characterized by comprising disposed.

According to the drive circuit of the electro-optical device of the second aspect, as in the first aspect, the deterioration of the precharge signal does not occur unlike the case of writing the precharge signal to all the data lines at once. The period for writing the precharge signal can be shortened. Therefore, even when the high-speed display mode is adopted, sufficient precharge can be performed, and a sufficient period from the end of writing the precharge signal to the start of writing the image signal can be ensured. Allow writing.

Moreover, the first and second shift registers are provided at positions close to each other, and the first and second shift registers are connected to each other from the common clock signal supply line formed between the first shift register and the second shift register. Since the clock signal is supplied to the two shift registers, it is not necessary to route the clock signal supply line in a complicated manner, and the area occupied by the first and second shift registers is further reduced.

Further, it is possible to support a high speed display mode by shortening the writing period of the precharge signal, and since the clock signal is supplied to the first and second shift registers from a common clock signal supply line, it is simple. With such a configuration, the occupied area is reduced and the electro-optical device is downsized.

A drive circuit for an electro-optical device according to a third aspect is the drive circuit according to any one of the first and second aspects, wherein after the second transfer start signal is output to the second shift register, the second shift register is output. The first shift register is further provided with a transfer start signal control means for outputting the first transfer signal.

According to the drive circuit of the electro-optical device described in claim 3, the image signal is written to the precharge signal and the image signal after the writing of the precharge signal with respect to the respective data lines. The charge amount of the image signal may be small according to the charge amount supplied as the charge signal, and the voltage level of each data line becomes a predetermined value.
Stabilize the voltage level of the data line.

According to another aspect of the drive circuit of the electro-optical device, a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is sequentially supplied, the plurality of data lines and the plurality of data lines. A driving circuit for an electro-optical device comprising switching means connected to a scanning line and pixel electrodes connected to each switching means, each being interposed between the data line and the image signal supply line. Sampling circuits having a plurality of first thin film transistors, sampling the image signal by conduction of the first thin film transistors and supplying the image signals to the data lines respectively, and interposing between a precharge signal supply line and the data lines. Multiple second to
A precharge circuit that has a thin film transistor and supplies the precharge signal to the data line by conduction of the second thin film transistor, a signal receiving unit that takes in the input signal in synchronization with a clock signal, and outputs the taken signal First and second shifts each having a signal propagating section for propagating as a signal and a feedback section for feeding back an output signal from the signal propagating section to a signal input side of the signal propagating section in synchronization with a clock signal A clock signal is supplied to the first and second shift registers from a common clock signal supply line, and the first and second shift registers are provided with a clock signal in the transfer direction corresponding to at least the first direction with respect to the sampling circuit. 1
Sequentially outputting a first drive signal for electrically connecting the first thin film transistor from each stage of the shift register, and electrically connecting a second thin film transistor from each stage of the second shift register to the precharge circuit in the transfer direction. Data line driving means for sequentially outputting a second drive signal, and transfer start signal control for outputting a first transfer start signal to the first shift register after outputting a second transfer start signal to the second shift register. Means and are provided.

According to the drive circuit of the electro-optical device according to the fourth aspect, when the writing period of the image signal such as one horizontal scanning period ends, the transfer start signal control means first causes the second data line driving means to operate. The second transfer start signal is output to the shift register. The second shift register to which the second transfer start signal is input captures the input second transfer start signal in synchronization with the clock signal in the signal capturing unit and propagates the signal as an output signal in the signal transmitting unit. Further, the feedback section feeds back the output signal from the signal propagation section to the signal input side of the signal propagation section in synchronization with the clock signal. As a result, a second drive signal based on the second transfer start signal is generated, and the second drive signal is output from the transfer start stage of the second shift register and the second drive signal is generated.
Is output as an input signal in the next stage of the shift register. In the next stage, similarly to the previous stage, the input signal is fetched and propagated in synchronization with the clock signal, and feedback is performed. As a result, the second drive signal in this stage is generated and output as this second drive signal, and
Further, it is output as an input signal in the next stage.

In the same manner, the second drive signal is output as an output signal of each stage while being sequentially transferred by each stage of the second shift register, and the second thin film transistors corresponding to each data line are sequentially turned on. Let In the precharge circuit, by sequentially conducting these second thin film transistors, the precharge signal supplied from the precharge signal supply line is line-sequentially supplied to each data line to write the precharge signal. .

On the other hand, the transfer start signal control means outputs the first transfer start signal to the first shift register after a lapse of a predetermined period from the output of the second transfer start signal. In the first shift register, similarly to the second shift register, the generation and output of the first drive signal based on the first transfer start signal and the transfer to the next stage are repeated, and the first shift register corresponds to each data line. One thin film transistor is sequentially turned on. In the sampling circuit, the image signals supplied from the image signal supply lines are line-sequentially supplied to the respective data lines by sequentially conducting the first thin film transistors, thereby writing the image signals.

As described above, the precharge signal and the image signal are written in the data lines in a line-sequential manner. However, regarding each data line, the image signal is written after the precharge signal is written. Therefore, the charge amount of the image signal can be small according to the charge amount supplied as the precharge signal, and the voltage level of each data line can be surely equal to or higher than a predetermined value, thus stabilizing the voltage level of the data line.

By supplying the precharge signals to the data lines line-sequentially as described above, the load corresponding to the capacitance of the data lines at the time of writing the precharge signal to the data lines once is reduced. This is remarkably reduced as compared with the case where the precharge signal is written to all the data lines, and the driving load of the second thin film transistor of the precharge circuit is reduced.

Further, unlike the case where the precharge signal is written to all the data lines at once, deterioration of the precharge signal does not occur, so that the period for writing the precharge signal can be shortened. Therefore, even when the high-speed display mode is adopted, sufficient precharge can be performed, and a sufficient period from the end of writing the precharge signal to the start of writing the image signal can be ensured. Allow writing.

Moreover, as described above, the first and second shift registers for outputting the first drive signal and the second drive signal are composed of the signal acquisition section, the signal propagation section and the feedback section, and are extremely Due to the simple structure, the first or second
The occupied area when formed on the substrate is reduced. Further, since the first and second shift registers are provided in positions close to each other and configured to share the clock signal supply line with each other, the clock signal supply line is provided on the first or second substrate. There is no need for complicated routing, and the area occupied by the first and second shift registers is further reduced.

As described above, according to the drive circuit of the electro-optical device according to the fourth aspect, it is possible to support the high-speed display mode by shortening the writing period of the precharge signal.
And the first that shares the clock signal supply line with a simple configuration
With the second shift register, the occupied area on the first or second substrate is reduced, and the liquid crystal panel is downsized.

A drive circuit for an electro-optical device according to a fifth aspect is the drive circuit for an electro-optical device according to any one of the first to fourth aspects, in which the first and second shift registers are bidirectional. A shift register of the present invention,
And the transfer direction of the second shift register is controlled based on a direction control signal from a common direction control signal section.

According to the drive circuit of the electro-optical device described in claim 5, the transfer direction control section in the first and second shift registers as the bidirectional shift register is provided with a direction control signal supply line. When the control signal is supplied,
The transfer direction of the signal is limited to a predetermined one direction based on the direction control signal. Therefore, by switching the value of the direction control signal, it becomes possible to reverse the writing order of the image signals, that is, the pixel position where the image signals are written. Moreover, since the basic configuration of the shift register is a simple configuration as described above, it is possible to reduce the occupied area even if such a transfer direction control unit is added. The directional shift register is
Since the direction control signal supply lines are shared with each other, complicated routing of the direction control signal supply lines is unnecessary, and the occupied area can be further reduced.

A drive circuit for an electro-optical device according to a sixth aspect is the drive circuit for an electro-optical device according to any one of the first to fifth aspects, wherein the sampling circuit and the precharge circuit are the data lines. Is provided in parallel with respect to.

According to the drive circuit of the electro-optical device described in claim 6, since the sampling circuit and the precharge circuit are provided in parallel with the data line, they are provided close to each other as described above. From the first and second shift registers, it becomes easy to route the supply lines for the first drive signal and the second drive signal connected to the sampling circuit and the precharge circuit, and the first and second shift registers are included. The area occupied by a peripheral circuit including a data line driving unit, a sampling circuit, and a precharge circuit is reduced, and a liquid crystal panel is downsized.

A drive circuit for an electro-optical device according to a seventh aspect is the drive circuit for an electro-optical device according to any one of the first to sixth aspects, in which the transfer start signal control means is the first 2 output completion timing of transfer start signal,
The output start timing and the pulse width of the second transfer start signal are controlled so as to have a predetermined time interval with the output start timing of the first transfer start signal.

According to the drive circuit of the electro-optical device described in claim 7, the transfer start signal control means outputs the first transfer start signal after outputting the second transfer start signal as described above. As a result, it becomes possible to write the precharge signal prior to the writing of the image signal.
The output start timing and pulse width of the second transfer start signal are controlled so that there is a predetermined time interval between the output completion timing of the second transfer start signal and the output start timing of the first transfer start signal. To do. As a result, the writing of the precharge signal to the data line is completed, and the image signal is written after the elapse of a predetermined time, so that the image signal is not adversely affected by the precharge signal and is appropriately written to the data line. Be done. Further, the pulse width of the second transfer start signal can be freely set in one horizontal blanking period. Accordingly, since the setting of the precharge period can be controlled by adjusting the external display information processing circuit, it is possible to remedy even an electro-optical device that cannot perform sufficient precharge due to insufficient characteristics of the TFT.
The yield is not reduced.

An electro-optical device according to an eighth aspect is characterized by including the electro-optical device according to any one of the first to seventh aspects.

According to the electro-optical device described in claim 8,
Even when the high-speed display mode is adopted, the contrast ratio is improved by performing sufficient precharge, and a good image without line unevenness on the display screen can be displayed, and a small electro-optical device is provided. It

According to a ninth aspect of the present invention, there is provided an electronic apparatus including the electro-optical device according to the eighth aspect.

According to the electronic apparatus of the ninth aspect, the electronic apparatus includes the electro-optical device of the present invention described above, and by performing sufficient precharge even when the high-speed display mode is adopted, the contrast ratio is increased. Is improved and a high quality image can be displayed by the electro-optical device capable of displaying a good image without line unevenness on the display screen. In addition, since the electro-optical device can be downsized, the electronic device can be downsized.

The operation and other advantages of the present invention will be apparent from the embodiments described below.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Structure of Liquid Crystal Device) First, the entire structure of the liquid crystal device as an example of the electro-optical device will be described with reference to FIGS.
Will be described with reference to. FIG. 1 is a block diagram showing the configuration of various wirings and peripheral circuits provided on a TFT array substrate in an embodiment of a liquid crystal device, and FIG. 2 is a TFT.
FIG. 4 is a plan view of the array substrate together with the components formed thereon as viewed from the counter substrate side, and FIG. 3 is a sectional view taken along the line HH ′ of FIG. 2 showing the counter substrate.

In FIG. 1, a liquid crystal device 200 includes a TFT array substrate 1 made of, for example, a quartz substrate or hard glass.
Is equipped with. On the TFT array substrate 1, a plurality of pixel electrodes 11 arranged in a matrix and a plurality of data lines 35 arranged in the X direction and extending in the Y direction.
A plurality of scanning lines 31 arranged in the Y direction, each of which extends along the X direction; A plurality of TFTs 30 are formed as an example of switching elements that are controlled according to scanning signals respectively supplied via the scanning lines 31. Although not shown, a capacitance line, which is a wiring for a storage capacitance, may be arranged substantially parallel to the scanning line 31 on the TFT array substrate 1, or the scanning line of the previous stage may be arranged. The lower part may be used to form the storage capacitor.

Further, on the TFT array substrate 1, a precharge circuit 201 for supplying a precharge signal of a predetermined voltage level to the plurality of data lines 35 prior to the image signal, respectively.
And a sampling circuit 301 for sampling an image signal and supplying it to each of the plurality of data lines 35, a data line driving circuit 101, and a scanning line driving circuit 104.

The scanning line driving circuit 104 has a power source supplied from an external control circuit (not shown) via the mounting terminal 102 shown in FIG. 2, a reference clock signal CLY, and an inverted signal CL.
Based on Y _INV , the start signal SPY, etc., the scanning signal is applied to the scanning line 31 in a pulse-wise line-sequential manner at a predetermined timing.

The data line drive circuit 101 comprises a precharge signal drive circuit 401 and an image signal drive circuit 501, of which the image signal drive circuit 501 is provided.
Is a power supply and a reference clock signal C supplied from an external control circuit (not shown) via the mounting terminal 102 shown in FIG.
The scanning line drive circuit 104 based on the LX and the inverted signal CLX _INV , the start signal SPX, the image signal VID, and the like.
Supplies a sampling circuit drive signal to the sampling circuit 301 via the sampling circuit drive signal line 306 for each data line 35 in order to sample the image signal VID as an image signal at the timing when the scanning signal is applied.

On the other hand, precharge signal drive circuit 401
Is a power source supplied from an external control circuit (not shown) via the mounting terminal 102 shown in FIG. 2, a reference clock signal CLX and an inverted signal CLX _INV common to the image signal driving circuit 501, and a precharge period setting pulse. Based on the signal NRG or the like, the scanning line driving circuit 104 completes the supply of the scanning signal to the scanning line 31 in one horizontal scanning period, and the polarity of the image signal is inverted (inversion of the signal phase of the image signal) in one horizontal blanking period. ) Is completed, the precharge signal N
In order to sample RS, a precharge circuit drive signal is supplied to the precharge circuit 201 for each data line 35 via the precharge circuit drive signal line 206.

The precharge circuit 201 includes switching elements NR1 to NRn formed of TFTs for each data line 35. Switching elements NR1 to NRn
The precharge signal line 204 is connected to the source electrode of the above, and the precharge circuit drive signal line 206 is connected to the gate electrodes of the switching elements NR1 to NRn. Then, a precharge signal of a predetermined voltage is supplied from an external control circuit (not shown) via the precharge signal line 204, at a timing preceding the writing of an image signal as described below for each data line 35, By supplying the precharge circuit drive signal from the precharge signal drive circuit 401 via the precharge circuit drive signal line 206, the switching elements NR1 to NR
n becomes conductive, and the precharge signal is written to each data line 35. The precharge signal supplied to the precharge circuit 201 is a signal (image auxiliary signal) having the same polarity (inversion of the same signal phase) as that of the image signal and corresponding to pixel data of an intermediate gradation level. preferable.

The sampling circuit 301 includes switching elements SH1 to SHn formed of TFTs for each data line 35. Switching elements SH1 to SHn
The image signal line 304 is connected to the source electrode of the above, and the sampling circuit drive signal line 306 is connected to the gate electrodes of the switching elements SH1 to SHn. Therefore, when the sampling circuit drive signal is input from the image signal drive circuit 501 via the sampling circuit drive signal line 306, the image signal VID supplied from the external control circuit (not shown) via the image signal line 304. Are sampled and sequentially supplied to the data line 35.

Although only one image signal line 304 is shown in FIG. 1 for simplification, when the dot frequency of the image signal is high, the image signal VID is reduced in order to reduce the frequency. You may develop one after another. There is no restriction on the number of phase expansions of image signals, but R is used when displaying video.
Since a signal line is required for each GB, the external control circuit can be configured relatively easily if it is configured by a multiple of 3. Needless to say, the image signal lines 304 are required at least for the number of phase expansions of the image signal.

The switching elements NR1 to NRn of the precharge circuit 201 and the drain electrodes of the switching elements SH1 to SHn of the sampling circuit 301 are both connected in parallel to the data line 35, and are connected to the precharge signal drive circuit 401. By the image signal drive circuit 501,
Switching elements NR1 to NRn and switching element S
The conduction state of H1 to SHn is switched at a predetermined timing, and the precharge signal is supplied to the data line 35 prior to the image signal.

In this embodiment, as shown in FIGS. 2 and 3, the precharge circuit 201 and the sampling circuit 301 are provided in the TFT array substrate at a position facing the light shielding peripheral parting 53 formed on the counter substrate 2. It is configured to provide a part or all of the above. With such a configuration, the data line driving circuit 101 and the scanning line driving circuit 104 are provided on a narrow and narrow peripheral portion of the TFT array substrate 1 which does not face the liquid crystal layer 50.
Further, the light-blocking peripheral partition 53 may be provided on the TFT array substrate 1. With such a configuration, the bonding accuracy between the TFT array substrate 1 and the counter substrate 2 can be ignored, so that the light transmittance of the liquid crystal panel does not vary. It goes without saying that the precharge circuit 201 and the sampling circuit may be provided in the data line driving circuit 101.

2 and 3, on the TFT array substrate 1, a screen display area defined by a plurality of pixel electrodes 11 (that is, a liquid crystal on which an image is actually displayed by changing the alignment state of the liquid crystal layer 50). A sealing material 52 made of a photo-curable resin, which is an example of a sealing member that encloses the liquid crystal layer 50 by bonding both substrates around a panel area),
It is provided along the screen display area. A light-blocking peripheral partition 53 is provided between the screen display area on the counter substrate 2 and the sealing material 52.

When the TFT array substrate 1 is put in a light-shielding case in which an opening is provided correspondingly to the screen display area, the peripheral parting 53 is formed in the screen display area due to manufacturing error or the like. A band-shaped light shield having a width of at least 500 μm or more around the screen display area so as not to be hidden by the edge of the opening, that is, to allow a shift of, for example, several hundred μm with respect to the case of the TFT array substrate 1. It is formed from a conductive material. Such a light-blocking peripheral partition 53 is formed on the counter substrate 2 by sputtering, photolithography, and etching using a metal material such as Cr (chrome) or Ni (nickel), for example. Alternatively, it is formed from a material such as resin black in which carbon or Ti (titanium) is dispersed in a photoresist.

In a region outside the seal material 52, a data line driving circuit 101 and mounting terminals 102 are provided along the lower side of the screen display region, and scanning line driving is performed along the left and right sides of the screen display region. Circuits 104 are provided on both sides of the screen display area. Here, if the wiring delay of the scanning line 31 does not pose a problem, the scanning line driving circuit 104 may be formed on only one side of the scanning line 31. Further, a plurality of wirings 105 are provided on the upper side of the screen display area. Further, a silver dot 106 made of a conductive material for electrically connecting the TFT array substrate 1 and the counter substrate 2 is provided at least at one corner of the counter substrate 2. The counter substrate 2 having substantially the same contour as the sealing material 52 is fixed to the TFT array substrate 1 by the sealing material 52.

(First Embodiment of Precharge Circuit and Sampling Circuit) Next, a specific circuit configuration of the switching elements NR1 to NRn and the switching elements SH1 to SHn that constitute the precharge circuit 201 and the sampling circuit 301 will be described. Each will be described with reference to FIGS. 4 and 5. FIG. 4 is a circuit diagram showing various TFTs constituting the switching elements NR1 to NRn of the precharge circuit 201, and FIG. 5 is various TFTs constituting the switching elements SH1 to SHn of the sampling circuit 301.
It is a circuit diagram showing.

As shown in FIG. 4A, the switching elements NR1 to NRn of the precharge circuit 201 (see FIG. 1).
May be composed of an N-channel type TFT 202a, or as shown in FIG.
b, or N as shown in FIG.
It may be composed of a complementary TFT 202c in which a channel type TFT and a P channel type TFT are connected in parallel. still,
4 (1) to 4 (3), the precharge circuit drive signals 206a and 206b input via the precharge circuit drive signal line 206 shown in FIG. 1 are input to the TFTs 202a to 202c as gate voltages. The precharge signal NRS, which is also input via the precharge signal line 204 shown in FIG. 1, is input to each of the TFTs 202a to 202c as a source voltage.

Precharge circuit drive signal 206a applied as a gate voltage to the N-channel TFT 202a.
And the precharge circuit drive signal 202b applied as a gate voltage to the P-channel TFT 202b are mutually inverted signals. Therefore, when the precharge circuit 201 is composed of the complementary TFT 202c, at least two precharge circuit drive signal lines 206 are required. In this case, for example, the precharge circuit drive signal 206a may be inverted by an inverter immediately before the TFT 202c, and the inverted signal 206b may be waveform-formed.

As shown in FIG. 5A, the switching elements SH1 to SHn of the sampling circuit 301 (see FIG. 1).
May be composed of an N-channel TFT 302a, or as shown in FIG.
b, or a complementary TFT 302c as shown in FIG. 5C. Incidentally, FIG.
5A to 5C, the image signal VID input through the image signal line 304 illustrated in FIG. 1 is input as a source voltage to each of the TFTs 302a to 302c, and the data line illustrated in FIG. Sampling circuit drive signals 306a and 306b input from the drive circuit 101 via the sampling circuit drive signal line 306 are input to the TFTs 302a to 302c as gate voltages.

Also in the sampling circuit 301, as in the case of the precharge circuit 201 described above, N
The sampling circuit drive signal 306a applied as a gate voltage to the channel TFT 302a and the sampling circuit drive signal 306b applied as a gate voltage to the P channel TFT 302b are mutually inverted signals. Therefore, the sampling circuit 301 is connected to the complementary TFT 3
02c, the sampling circuit drive signal line 3 for the sampling circuit drive signals 306a and 306b.
At least two 06 are required. Also in the case of the sampling circuit 301, for example, the complementary TFT 302
Immediately before c, the sampling circuit drive signal 306a may be inverted by an inverter to form a waveform of the inverted signal 306b.

(First Embodiment of Drive Circuit) Next, a first embodiment of the drive circuit will be described with reference to FIGS. 6 to 11. 6 is a diagram showing the data line drive circuit in the first embodiment, FIG. 7 is a circuit diagram showing the configuration of each stage of the shift register that constitutes the data line drive circuit, and FIG. FIG. 8 is a diagram showing a circuit symbol of a clocked inverter in the data line driving circuit of the present embodiment.
8B is a diagram showing the circuit configuration of the clocked inverter of FIG. 8A, FIG. 9 is a timing chart of various signals in the data line driving circuit of FIG. 6, and FIG. 10 is precharge in the data line driving circuit of FIG. 11 is a timing chart showing the timing of FIG. 11, and FIG. 11 is a diagram showing one horizontal blanking period and precharge period in each display mode.

First, the data line drive circuit will be described.

As shown in FIG. 6, the data line driving circuit 10
The image signal drive circuit 501 and the precharge signal drive circuit 401 that form part 1 include a shift register 502 as a first shift register and a buffer circuit 503 including a waveform control circuit such as an AND circuit, and the shift register 402. A shift register 402 as a second shift register and a buffer circuit 403 having the same configuration as the above are included.

In the present embodiment, the image signal drive circuit 501 and the precharge signal drive circuit 40 forming the data line drive circuit 101 as an example of the data line drive means.
1 is the X direction (P1, P2, P3, ..., Pn shown in FIG.
And X1, X2, X3, ..., Xn in the scanning direction)
In the transfer direction corresponding to
The sampling circuit drive signal as the first drive signal and the precharge circuit drive signal as the second drive signal are sequentially output from each of the stages, and the sampling circuit 301 and the precharge circuit 2 are supplied via the buffer circuits 503 and 403.
Supply to 01.

In the image signal drive circuit 501, the buffer circuit 503 including a waveform control circuit such as an AND circuit controls the odd-numbered column and even-numbered column buffer circuits 503 by an enable signal from the outside, so that each sampling circuit is controlled. The waveform is selected so that the on-state periods of the drive signal do not overlap, and the sampling circuit drive signal is generated and sequentially supplied to the sampling circuit 301. Thereby, the sampling circuit 30 before and after
Since the signal to be written in 1 is not taken in, it is possible to prevent the deterioration of display quality due to a ghost or the like.

A start signal SPX as a first transfer start signal for starting the transfer of the sampling circuit drive signal is input to the shift register 502 of the image signal drive circuit 501 from the direction A. Then, at the timing shown in the timing chart of FIG. 9, the start signal S
PX, clock signal CLX and its inverted signal CLX _INV
Is input, the image signal drive circuit 501 sequentially delays the sampling circuit drive signal SH having a width narrower than the pulse width of the start signal SPX by a half cycle of the clock signal CLX and supplies it to the sampling circuit 301. Is configured.

On the other hand, precharge signal drive circuit 401
The shift register 402 is configured so that the precharge period setting pulse signal NRG as the second transfer start signal for setting the precharge period is input from the A direction. The precharge period setting pulse signal NRG is always set to be input earlier than the start signal SPX of the image signal drive circuit 501 within the same horizontal retrace period. When the precharge period setting pulse signal NRG, the clock signal CLX and its inverted signal CLX _INV are input at the timing shown in the timing chart of FIG. 9, the precharge signal drive circuit 401 causes the precharge period setting pulse The precharge circuit drive signal having a width equal to the pulse width of the signal NRG is sequentially delayed by a half cycle of the clock signal, and the precharge circuit 2
The buffer circuit 403 is configured to connect the inverters in a multi-stage cascade so as to supply signal No. 01 to perform signal amplification and waveform shaping. Here, the buffer circuit 40
3 is a buffer circuit 503 of the image signal drive circuit 501
Similarly, a waveform control circuit such as an AND circuit may be provided. With such a configuration, the pulse width of the precharge circuit drive signal is freely set in the pulse width period of the precharge period setting pulse signal NRG by the enable signal from the display information processing circuit or the like connected to the outside of the liquid crystal panel. There is an advantage that can be controlled.

Although not shown, the scanning line drive circuit 104 is provided with a shift register and a buffer circuit similar to the image signal drive circuit 501.

Next, the shift registers 402 and 502 will be described in detail.

As shown in FIG. 6, the shift register 40
Each stage of 2,502 is configured to include a clocked inverter and an inverter. More specifically, as shown in FIG. 7, a signal receiving section 150 including a clocked inverter 130, a signal propagating section 151 including an inverter 132, and a clock connected to the inverter 132 for feedback. It is composed of a feedback section 152 composed of a de-inverter 131 and constitutes a static type latch circuit. The feedback unit 152 may be omitted and a capacitance may be added to the output unit of the inverter 132 to provide a dynamic latch circuit. Further, even if the clocked inverters 130 and 131 are composed of transmission gates described later, the same function is achieved. Needless to say, when the transmission gate is used as described above, the inverters of the signal propagating unit 151 need to be cascade-connected in two stages.

The clocked inverter is represented by the symbol shown in FIG. 8A, and has a gate terminal in addition to the input terminal and the output terminal. The circuit configuration is as shown in FIG. 8B, in which the signal input to the gate terminal of the N-channel TFT is at high level and the signal input to the gate terminal of the P-channel TFT is at low level. In the case of the level, it operates as a normal inverter circuit. Also,
When the signal input to the gate terminal of the N-channel TFT is low level and the signal input to the gate terminal of the P-channel TFT is high level, the output is in a high impedance state. In the drawings of the present application, when the clocked inverter is shown, only the signal connected to the gate terminal of the N-channel TFT is shown as shown in FIG. Also, this convention is
The same applies not only to the clocked inverter but also to a circuit having a gate terminal.

In this embodiment, the shift register 402,
Since each stage of 502 is configured by the above circuits, for example, the clocked inverter 1 of the signal acquisition unit 150
In the case where the clock signal CLX is input to 30, and the inverted signal CLX _INV of the clock signal is input to the clocked inverter 131 of the feedback unit 152, the precharge period setting pulse signal that rises to a high level as shown in FIG. When NRG is input to the input signal line IN of the circuit shown in FIG. 7, the following operation is performed. First, at the rising edge of the clock signal CLX, the clocked inverter 1
The pulse signal NRG is taken in by 30 and a high level signal is output via the inverter 132 to the output signal line O.
It is output from the UT. Then, this output state is maintained while the clock signal CLX is at the high level. next,
When the clock signal CLX falls, the output of the clocked inverter 130 becomes a high impedance state,
Since the level of the output signal line OUT is fed back to the input side of the inverter 132 by the clocked inverter circuit 131 in which the inverted signal CLX _INV of the clock signal CLX is input to the gate terminal, the level of the clock signal CLX falls, that is, Feedback is performed from the rising of the inverted signal CLX _INV , and the level of the output signal line OUT is maintained at the high level. Then, the inverted signal CLX
_At the falling edge of _INV , that is, the rising edge of the clock signal CLX, the signal input to the input signal line IN is taken in. At this timing, the signal NRG is at the low level as shown in FIG. OU
The level of T also becomes low level. In this way, the pulse signal having the same width as the input pulse signal NRG is output from the output signal line OUT.

The circuit as described above is provided with the shift register 40.
Prepared for each stage of 2,502, clocked inverter 130
By alternately exchanging the clock signal CLX and the inversion signal CLX _INV input to the gate terminal of the clocked inverter 131 for each stage, as shown in FIG. 9, pulse signals shifted by half a cycle of the clock signal CLX are generated. As the precharge circuit drive signal, the precharge circuits NR1 to NR1
Will be supplied to NRn. Also, the start signal S
The signal output from the shift register 502 of the image signal drive circuit 501 that transfers PX is also the start signal SPX.
The pulse signal has the same width as that of the buffer signal 503 of the image signal drive circuit 501.
A waveform control circuit such as an AND circuit provided in each stage enables the enable signal ENB1 or E as shown in FIG. 9 for each stage.
A logical product is taken with NB2. The pulse width of the enable signal ENB1 or ENB2 is the clock signal C
Since the pulse width is the same as or narrower than the half cycle of LX, a pulse signal as shown in FIG. 9 in which high-level periods do not overlap is supplied to the sampling circuits SH1 to SHn as a sampling circuit drive signal. It will be.
As described above, when the image signal is sampled, the image signal is simultaneously transmitted between the data lines 35 in the TFT 3 in the pixel region.
It is configured so that it will not be supplied to 0 to prevent the occurrence of ghosts and the like.

Further, as shown in FIG. 9, since the precharge period setting pulse signal NRG is configured to be output earlier than the start signal SPX by the predetermined period tm, the image signal is sampled at the timing. Prior to this, the precharge circuit 201 is turned on, and the precharge signal NRS supplied via the precharge signal line 204 is supplied to each data line 35. The precharge signal is a signal set to an appropriate potential level, and such a precharge signal is written to the data line 35 prior to the supply of the image signal to the data line 35, so that the image signal is The amount of charge required when writing to the data line 35 can be significantly reduced. Further, even when the image signal is supplied to the data lines 35 at a high rate, it is possible to stabilize the potential level of each data line 35, reduce line unevenness on the display screen, and improve the contrast ratio.

Further, in the present embodiment, in order to drive the liquid crystal by an alternating current, a predetermined period such as one horizontal scanning period (one frame) or one field (for example, two frames) is set.
Although the voltage polarity of the image signal is inverted, as described above, each data line 3 is supplied before each image signal is supplied to the TFT 30.
5 preferably corresponds to an image signal of an intermediate gradation level and is supplied with a precharge signal having the same polarity as that of the image signal. Therefore, the load when writing the image signal is reduced, and the data line 35 is provided. The potential level of is stable regardless of the previously applied potential level. Therefore, the current image signal can be supplied to each data line 35 with a stable potential.

Particularly, in the present embodiment, since the precharge signal is written line-sequentially to the data line 35 as described above, it is effective when the liquid crystal panel is driven in the high speed display mode. FIG. 10 is a timing chart showing the timing of precharge according to the present embodiment. In the case of the configuration in which the polarity of the image signal is performed every horizontal scanning period, the precharge is performed within the horizontal retrace line period during the period t from the completion of the inversion of the polarity of the image signal to the rise of the start signal SPX. It is necessary to output the period setting pulse signal NRG. This one horizontal blanking period varies depending on the display mode as shown in FIG. 11, and is, for example, VGA or SVG.
In a display mode such as A, one horizontal retrace line period is about 6.4 μsec if it is about 60 HZ, although it depends on the frequency in the vertical direction. When one horizontal blanking period is sufficiently long as described above, for example, a precharge period of about 3.9 μsec can be secured, and the precharge period setting pulse signal NRG is at a high level (that is, tNR in FIG. 9). Even in the method in which all the data lines are collectively precharged in (), sufficient precharge could be performed. However, in a display mode such as XGA or EWS, the horizontal blanking period is as short as 4.1 μsec or 3.8 μsec, and the precharge period is about 1.
6 μsec, about 1.3 μsec in EWS mode
It was extremely short, and it was not possible to perform sufficient precharge by the conventional batch precharge method.
Especially in the EWS mode, the number of horizontal pixels is 1.
Since it is 280, it is necessary to collectively perform at least 1280 stages of precharge. However, considering the drive capability of the TFT of the precharge circuit and the time constant of the data line, a precharge period of 1.0 μsec or more. It was necessary and could not fully precharge.

On the other hand, in the present embodiment, since the data lines are precharged line-sequentially as described above, the load at the time of precharging is one data line. Even if the precharge is performed by the precharge, the capacity of the data line as the load is significantly smaller than that of the conventional one. For example, the capacity of several data lines is about 20 pF, and the on-resistance of the TFT of the precharge circuit is 1 kΩ.
If so, the precharge period tNR shown in FIG.
About μsec is sufficient. Therefore, in this embodiment, sufficient precharge can be performed even when a high-speed display mode such as the EWS mode is adopted as the display mode.

In this embodiment, as shown in FIG. 10, a period tm is provided from the end of the precharge period to the rising of the start signal SPX. This period tm is
It can be freely set by externally controlling the NRG or SPX signal in consideration of a problem such as signal delay.

The present invention is extremely effective in that
This is because the shift register has a simple configuration as described above. Since the structure of the shift register is simple, the area occupied by the shift register can be reduced, and the area for arranging the precharge circuit can be sufficiently secured. As a result, it is not necessary to extremely reduce the size of the TFT. Disappear. Since the load during precharge is small as described above, sufficient precharge can be performed in a precharge period of about 1 μsec even when the display mode is a high-speed display mode such as the EWS mode. Furthermore, since the period tm from the completion of the precharge period to the rising of the start signal for the image signal can be sufficiently secured, the image signal can be appropriately written.

In this embodiment, as shown in FIG. 1, the image signal drive circuit 50 is provided in the data drive circuit 101.
1, the precharge drive circuit 401 is provided, and the image signal drive circuit 501 and the precharge drive circuit have a common signal line pattern for the clock signal CLX and the inverted signal CLX _INV. Even when the size of the device is reduced, it is possible to provide a driving device including a shift register for precharging.

Further, according to the present embodiment, since the shift register having the simple structure as shown in FIG. 6 is adopted, the shift register for precharge and the shift register for image signal are provided in a small area. Further, by _arranging the signal line patterns of the clock signal CLX and the inverted signal CLX _INV in the intermediate portion of both shift registers, it is possible to keep the occupied area of the data line drive circuit small. .

In the present embodiment as well, there is a limit in increasing the TFT size of the precharge circuit, but as described above, the capacitance of the data line at the time of precharging is required to perform precharging in line sequential. The load is small,
As shown in 0, even if one horizontal blanking period is short, it is possible to perform sufficient precharge in a short precharge period. That is, the precharge period setting pulse signal NRG can be output at any time within the period t1 shown in FIG. Therefore, even if the TFT size cannot be increased, the precharge period setting pulse signal NRG is advanced to advance the output start timing to sufficiently secure the period tm until the rising of the start signal SPX and set the precharge period. Pulse signal N
Since the pulse width tNR of the RG can be lengthened to some extent, it is possible to achieve both sufficient precharge, proper image signal writing, and size reduction of the liquid crystal device even when the on-resistance cannot be reduced sufficiently. Is.

(Second Embodiment of Drive Circuit) Next, a second embodiment of the drive circuit of the present invention will be described with reference to FIGS.
It will be described based on. The same parts as those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, as a shift register of the precharge signal drive circuit 401 and the image signal drive circuit 501 shown in FIG. 12, a bidirectional shift register is used as shown in FIG. Different from the embodiment. Although shift registers 402 and 502 are shown in FIG. 13, these shift registers function as a shift register that shifts in the A to B direction and in a case that they function as a shift register that shifts in the B to A direction. It is a so-called bidirectional shift register that can be switched to.

In the bidirectional shift register, as shown in FIG. 13, the shift register is entirely composed of clocked inverters, and the transfer direction control is performed in series with the clocked inverters of the signal capturing section and the feedback section. It is connected to a clocked inverter for. The transfer direction control signal DX and its inverted signal DX _INV are input to the gate terminal of this transfer direction control clocked inverter.
Is high level, the signal is transferred in the direction from A to B in FIG. 13, and when the inverted signal DX _INV is high level, the signal is transferred in the direction from B to A.

The basic operation of the bidirectional shift register is similar to that of the shift register of the first embodiment, and when signals are transferred in the direction A to B in FIG. 13, FIG. As shown, the precharge circuit 201
The drive signals are sequentially supplied in the direction from the switching element NR1 to NRn of the above, or in the direction from the switching element SH1 to SHn of the sampling circuit 301.

On the other hand, when signals are transferred from B to A in FIG. 13, switching elements NRn to N of precharge circuit 201 are transferred as shown in FIG.
The drive signal is sequentially supplied in the direction of R1 or in the direction of the switching element SHn of the sampling circuit 301 to SH1.

When the bidirectional shift register is provided, the pattern of the transfer direction control signal DX and the inversion signal DX _INV needs to be further routed as compared with the case of the first embodiment. In the mode, the transfer direction control signal DX and the inverted signal DX _INV are configured to be shared by both bidirectional shift registers, so that the area occupied by the data line driving circuit 101 can be suppressed small. Further, since the configuration of the bidirectional shift register itself is simple as shown in FIG. 13 as in the first embodiment, the liquid crystal device can be downsized as well as in the first embodiment while being sufficiently small. Pre-charge and proper image signal writing are possible.

By using the bidirectional shift register as described above also in the scanning line driving circuit 104, when a liquid crystal panel is used as a light valve of a liquid crystal projector, there is no color (that is, a color filter is used). It is possible to employ a multi-plate system in which three (not formed) liquid crystal panels are used for each of RGB, and the display screen is brightened to obtain high-quality image. According to this multi-plate system, the three color lights, which are separately modulated by the three liquid crystal panels, are combined into one projection light by the prism or dichroic mirror and then projected on the screen. Thus, when combined with a prism or the like, as shown in FIG. 16, as compared with the R light and the B light reflected by the prism 502 after being modulated by the three RGB light valves 500R, 500G and 500B, the G light is compared. Are not reflected by the prism 5002. That is, the number of times of light inversion decreases only once for G light.
This phenomenon is of course the same even if the optical system is configured so that the R light or the B light is not reflected by the prism instead of the G light, and the same applies when the three color lights are combined using a dichroic mirror or the like. Happen to. Therefore, in such a case, it becomes necessary to turn the image signal for the G light right and left in some form.

Therefore, by using the liquid crystal panel provided with the bidirectional shift register as in this embodiment, the image signal can be flipped over to the left and right, and the above-mentioned multi-panel liquid crystal projector can be constructed. it can.

In the liquid crystal projector having the light valve, there is a single plate system that uses only one colored liquid crystal panel (that is, a color filter is formed on the counter substrate). If you use a panel, you can flip the image signal up and down, left and right, and even if you install such a single plate type liquid crystal projector or the above-mentioned multiple plate type liquid crystal projector on the floor as a floor type, It can also be configured so that it can be used as a ceiling mount type that is installed upside down. Also,
It is also possible to turn a liquid crystal monitor, which is a single-panel liquid crystal device, like the liquid crystal monitor of a portable video camera, so that it can be turned upside down with a flexible joint as a fulcrum, depending on the user's shooting posture. Is.

(Third Embodiment of Driving Circuit) Next, a third embodiment of the driving circuit of the present invention will be described with reference to FIGS.
It will be described based on. The same parts as those of the first embodiment or the second embodiment are designated by the same reference numerals and the description thereof will be omitted.

This embodiment is different from the second embodiment in that, as shown in FIG. 17, the transfer direction control unit of the bidirectional shift register is composed of the transmission gate 160 instead of the clocked inverter.

The bidirectional shift register shown in FIG.
The transfer direction control unit, in which the transfer direction is fixed according to the transfer direction control signal DX and the inverted signal DX _INV , is composed of the transmission gate 160 and includes the clock signal CL.
The signal capturing unit and the feedback unit that capture the signal based on the X and the inverted signal CLX _INV are clocked inverters 130, 1.
It is composed of 31.

The transmission gate 160 is shown in FIG.
It is represented by the symbol shown in FIG. 9 (a) and has the circuit configuration of FIG. 19 (b). The transmission gate 160 includes an N-channel TFT and a P-channel according to a potential difference between the direction control signal DX or the clock signal CLX applied to the gate electrode and the transfer signal applied to the input side electrode or the output side electrode of the transfer signal. Since the type TFTs are simultaneously turned on, it is not necessary to supply the positive power supply VDD and the negative power supply VSS unlike the clocked inverter. Therefore, it is not necessary to circulate these power supply patterns, the interval between adjacent stages of the bidirectional shift register can be made narrower than in the case of the second embodiment, and the liquid crystal device can be further miniaturized. It is possible.

Further, as shown in FIG. 18, the transfer gate 160 and the feedback section of the bidirectional shift register may be wholly or partially configured by the transmission gate 160. With this configuration, the liquid crystal device can be further downsized. It should be noted that instead of the transmission gate, a single-channel TFT such as a P-channel TFT or an N-channel TFT may be used to configure all or part of the transfer direction control signal acquisition unit and the feedback unit of the bidirectional shift register. . By adopting such a configuration, the peripheral circuits can be further integrated, and a smaller liquid crystal panel can be realized.

(Fourth Embodiment of Drive Circuit) Next, a fourth embodiment of the drive circuit of the present invention will be described with reference to FIGS.
It will be described based on. The same parts as those of the first embodiment or the second embodiment are designated by the same reference numerals and the description thereof will be omitted.

The present embodiment differs from the above-described embodiments in that a plurality of switching elements of the precharge circuit and the sampling circuit are configured to be driven by one drive signal line.

In this embodiment, as shown in FIG. 20, a plurality of switching elements are connected to one precharge circuit drive signal line 206 and one sampling circuit drive signal line 306, and as shown in FIG. , The write timing of the precharge signal for several data lines is set at the same time. Therefore, although several data lines are precharged at one time, the load at one precharge is small and sufficient precharge can be performed in a short precharge period.

Further, since the number of drive signal lines can be reduced, the area of each stage of the shift register of the precharge signal drive circuit 401 and the image signal drive circuit 501 can be made larger than that in each of the above-described embodiments. Therefore, the pattern design can be facilitated.

In addition, according to the embodiment, for example, S
If the switch elements NR1 to NR3 of the precharge circuit 201 and the switch elements SH1 to SH3 of the sampling circuit 301 connected to the data lines 35 of 1 to S3 are configured to be simultaneously driven, the precharge signal drive circuit 4
01 and the frequency of the shift register forming the image signal drive circuit 501 can be reduced to 1/3,
The load on the external control circuit is reduced. Further, if the drive frequency of the shift register is reduced, not only the current consumption can be reduced, but also T which constitutes the shift register can be reduced.
The life of the FT can be extended and a highly reliable liquid crystal panel can be provided.

Although the embodiments of the drive circuits have been described above, the precharge signal drive circuit and the image signal drive circuit of the data line drive circuit, the precharge circuit, the sampling circuit, or the scanning line drive circuit are respectively pixel-based. Complementary TF in the same thin film formation process as the TFT 30 in the area
T can be formed, which is advantageous in manufacturing.

In each of the above-described embodiments, the case where an external control circuit for outputting a clock signal or an image signal to the data line driving circuit and the scanning line driving circuit is provided outside the liquid crystal device will be described. However, the present invention is not limited to this, and the control circuit may be provided in the liquid crystal device.

In each of the embodiments described above, the precharge circuit 201 is replaced by the data line drive circuit 101.
Since it is provided on the side, the area A on the opposite side across the data line 35 is provided.
Alternatively, as shown in FIG. 2, an inspection circuit may be provided.

The side of the counter substrate 2 of the liquid crystal device of each of the above-described embodiments on which the projection light is incident and the TFT array substrate 1 are also included.
On the side from which the projected light is emitted, for example, TN (twisted nematic) mode, STN (super T
N) mode, D-STN (double-STN) mode and other operation modes, and normally white mode / normally black mode, a polarizing film, a retardation film, a polarizing plate, etc. are arranged in a predetermined direction. It

Since the liquid crystal panel 10 described above is applied to a color liquid crystal projector, it has three liquid crystal panels 1.
0 is used as a light valve for RGB, and the light of each color separated through the dichroic mirror for RGB color separation is incident on each panel as incident light. Therefore, in each embodiment, the counter substrate 2
In addition, no color filter is provided. However, also in the liquid crystal panel 10, a RGB color filter may be formed on the counter substrate 2 together with its protective film in a predetermined region facing the pixel electrode 11 where the light shielding layer 23 is not formed. By doing so, the liquid crystal panel of the present embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflection type color liquid crystal television other than the liquid crystal projector.

The switching element of the liquid crystal panel 10 is a positive stagger type or coplanar type polysilicon TFT.
However, the present embodiment is effective for the inverted stagger type TFT and the other type TFT such as amorphous silicon.

Further, in the liquid crystal panel 10, the liquid crystal layer 50 is made of a nematic liquid crystal as an example, but if a polymer dispersed liquid crystal in which the liquid crystal is dispersed as fine particles in a polymer is used, the alignment film and The polarizing film, polarizing plate, etc. are not required, and the advantages of higher brightness and lower power consumption of the liquid crystal panel due to the increased light utilization efficiency can be obtained.
Further, when the liquid crystal panel 10 is applied to a reflection type liquid crystal device by forming the pixel electrode 11 from a metal film having a high reflectance such as Al, the SH in which liquid crystal molecules are substantially vertically aligned in the state where no voltage is applied is used. A (super homeotropic) type liquid crystal or the like may be used. Furthermore, in the liquid crystal panel 10, the common electrode 21 is provided on the counter substrate 2 side so as to apply an electric field (vertical electric field) perpendicular to the liquid crystal layer 50. Each pixel electrode 11 is composed of a pair of electrodes for horizontal electric field generation so as to apply an electric field (that is, without providing electrodes for vertical electric field generation on the counter substrate 2 side, the TFT array substrate 1 side). It is also possible to provide an electrode for generating a lateral electric field). The use of the horizontal electric field in this manner is advantageous in widening the viewing angle as compared with the case of using the vertical electric field. In addition, the present embodiment can be applied to various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignments, driving methods, and the like.

The data line driving circuit 101 and the scanning line driving circuit 104 are provided on the driving LSI mounted on, for example, a TAB (tape automated bonding substrate) instead of being provided on the TFT array substrate 1. You may make it electrically and mechanically connect via the anisotropic conductive film provided in the peripheral part of the board | substrate 1. FIG.

Furthermore, in the above-described embodiments, JP-A-9-127497, JP-B-3-52611, JP-A-3-125123, and JP-A-8-17.
As disclosed in Japanese Laid-Open Patent Publication No. 1101 and the like, a position facing the TFT 30 on the TFT array substrate 1 (that is,
A light shielding layer made of, for example, a high melting point metal may be provided also on the lower side of the TFT 30. By thus providing the light shielding layer also on the lower side of the TFT 30, it is possible to prevent the return light or the like from the TFT array substrate 1 side from entering the TFT 30.

(Electronic Device) Next, an embodiment of an electronic device including the liquid crystal device 200 described in detail above will be described with reference to FIGS. 22 to 25.

First, FIG. 22 shows the liquid crystal device 200 as described above.
1 shows a schematic configuration of an electronic device equipped with.

In FIG. 22, the electronic device includes a display information output source 1000 and the external display information processing circuit 100 described above.
2, a display drive circuit 1004 including the scan line drive circuit 104 and the data line drive circuit 101, the liquid crystal panel 10,
The clock generation circuit 1008 and the power supply circuit 1010 are provided. The display information output source 1000 is RO
M (Read Only Memory), RAM (Random Access)
Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs a television signal, and the like, and displays display information such as an image signal of a predetermined format based on the clock signal from the clock generation circuit 1008. Output to the processing circuit 1002. Display information processing circuit 1002
The clock generator circuit 10 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit.
Digital signals are sequentially generated from the display information input based on the clock signal from 08 and output to the display drive circuit 1004 together with the clock signal CLK. Display drive circuit 10
Reference numeral 04 denotes the scanning line driving circuit 104 and the data line driving circuit 1
01 drives the liquid crystal panel 10 by the above-described driving method. The power supply circuit 1010 supplies a predetermined power supply to each of the above circuits. The display drive circuit 1004 may be mounted on the TFT array substrate forming the liquid crystal panel 10, or the display information processing circuit 1002 may be mounted in addition to this.

FIG. 23 shows an electronic device having such a configuration.
24, a multimedia-compatible personal computer (PC) and engineering workstation (EWS) shown in FIG. 24, or a mobile phone, a word processor, a television, a viewfinder type or monitor direct view type video table recorder, an electronic notebook,
Examples thereof include an electronic desk calculator, a car navigation device, a POS terminal, and a device equipped with a touch panel.

Next, FIG. 23 to FIG. 25 show specific examples of the electronic apparatus configured as described above. In FIG. 23,
A liquid crystal projector 1100, which is an example of an electronic device, is a projection type liquid crystal projector, and includes a light source 1110, dichroic mirrors 1113 and 1114, and a reflection mirror 11.
15, 1116, 1117, an entrance lens 1118, a relay lens 1119, an exit lens 1120, liquid crystal light valves 1122, 1123, 1124, a cross dichroic prism 1125, and a projection lens 1126. Liquid crystal light valve 1122
1123 and 1124 are the same as the above-mentioned drive circuit 1004.
Three liquid crystal modules including the liquid crystal panel 10 mounted on the FT array substrate were prepared and used as liquid crystal light valves. The light source 1110 includes a lamp 1111 such as a metal halide and a reflector 1112 that reflects the light from the lamp 1111.

In the liquid crystal projector 1100 configured as described above, the dichroic mirror 1113 for reflecting blue light and green light transmits red light of the white light flux from the light source 1110 and also transmits blue light and green light. To reflect. The transmitted red light is reflected by the reflection mirror 1117 and enters the red light liquid crystal light valve 1122. On the other hand, of the color light reflected by the dichroic mirror 1113, green light is reflected by the green light reflecting dichroic mirror 1114 and is incident on the green light liquid crystal light valve 1123. The blue light also passes through the second dichroic mirror 1114. For blue light, in order to prevent light loss due to a long optical path, the incident lens 11
18, a relay lens 1119 and a light guide means 1121 including a relay lens system including an emission lens 1120 are provided, and blue light is emitted through the light guide means 1121 through the liquid crystal light valve 1 for blue light.
It is incident on 124. The three color lights modulated by the respective light valves enter the cross dichroic prism 1125. This prism is formed by laminating four right-angled prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof.
Three color lights are combined by these dielectric multilayer films to form light representing a color image. The combined light is projected on the screen 1127 by the projection lens 1126 which is a projection optical system, and the image is enlarged and displayed.

In FIG. 24, a laptop personal computer 1200 which is another example of an electronic apparatus accommodates a liquid crystal display 1206 in which the liquid crystal panel 10 described above is provided in a top cover case, a CPU, a memory, a modem and the like. And a main body 1204 in which a keyboard 1202 is incorporated.

Further, as shown in FIG. 25, a liquid crystal device substrate 1304 in which liquid crystal is enclosed between two transparent substrates 1304a and 1304b and the above-mentioned drive circuit 1004 is mounted on a TFT array substrate is provided. Liquid crystal device substrate 13
Two transparent substrates 1304a and 1304b constituting 04.
On one side, a TCP (Tape Tape) in which an IC chip 1324 is mounted on a polyimide tape 1322 on which a metal conductive film is formed.
Carrier Package) 1320 can be connected to produce, sell and use as a liquid crystal device which is one component for electronic equipment.

As described above, in addition to the electronic devices described with reference to FIGS. 23 to 25, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, a work piece, and the like. Station, mobile phone, videophone, PO
An example of the electronic device shown in FIG. 21 is an S terminal, a device including a touch panel, or the like.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to the driving of the above-mentioned various liquid crystal panels, but can also be applied to electroluminescence and plasma display devices.

According to the present embodiment, various types of liquid crystal devices 200 that are small in size and have a sufficient precharge function to remarkably reduce the load on the signal source of the image signal and to enable stable image display are provided. Electronic devices can be realized.

[0125]

As described above, according to the driving device of the electro-optical device of the present invention, not only the driving signal for the sampling circuit but also the driving signal for the precharge circuit is provided by the shift register for each data line or a plurality of data lines. Is sequentially output to each adjacent data line group, and any shift register is provided in the data line drive circuit as a simple configuration. Further, since the clock signal is supplied from the common clock signal supply line to the shift register for the sampling circuit and the shift register for the precharge circuit, the writing period of the precharge signal can be shortened to achieve high-speed display. The mode can be supported, and the area occupied by the clock signal supply line on the substrate of the shift register can be reduced with a simple configuration, and the drive circuit of the electro-optical device can be downsized.

[Brief description of drawings]

FIG. 1 is a TFT in a first embodiment of a liquid crystal device.
It is a block diagram of various wirings, peripheral circuits, and the like formed on the array substrate.

FIG. 2 is a plan view showing the overall configuration of the liquid crystal device of FIG.

FIG. 3 is a cross-sectional view showing the overall configuration of the liquid crystal device of FIG.

FIG. 4 is a circuit diagram of a TFT included in a precharge circuit provided in a liquid crystal device.

FIG. 5 is a circuit diagram of a TFT included in a sampling circuit provided in a liquid crystal device.

6 is a circuit diagram of a data line drive circuit, a precharge circuit, and a sampling circuit in the liquid crystal device of FIG.

7 is a circuit diagram of a circuit of each stage of a shift register which constitutes the data line driving circuit of FIG.

8 is a diagram showing a circuit symbol of a clocked inverter forming the circuit of FIG. 7, and FIG. 8B is a circuit diagram showing a circuit configuration of the clocked inverter of FIG.

9 is a timing chart showing operations of a data line driving circuit, a precharge circuit, and a sampling circuit in the liquid crystal device of FIG.

10 is a timing chart showing the timing of precharge in the liquid crystal device of FIG.

FIG. 11 is a diagram showing a relationship between various display modes and one horizontal blanking period and a precharge period.

FIG. 12: TF in the second embodiment of the liquid crystal device
FIG. 6 is a block diagram of various wirings, peripheral circuits, etc. formed on a T array substrate.

13 is a circuit diagram of a data line drive circuit, a precharge circuit, and a sampling circuit in the liquid crystal device of FIG.

FIG. 14 is a timing chart showing the operations of the data line drive circuit, the precharge circuit, and the sampling circuit when the direction control signal is at a high level in the liquid crystal device of FIG.

15 is a timing chart showing operations of the data line driving circuit, the precharge circuit, and the sampling circuit when the inverted signal of the direction control signal is at the high level in the liquid crystal device of FIG.

16 is a conceptual diagram showing a prism optical system which combines RGB three-color lights of a liquid crystal projector using the liquid crystal device of FIG.

FIG. 17 is a circuit diagram showing a configuration of a shift register in a liquid crystal device according to a third embodiment.

FIG. 18 is a circuit diagram showing another configuration of the shift register in the third embodiment of the liquid crystal device.

19A is a diagram showing a circuit symbol of a transmission gate that constitutes the shift register of FIG. 17 or FIG. 18, and FIG. 19B is a circuit diagram showing a circuit configuration of the transmission gate of FIG.

FIG. 20: TF in the fourth embodiment of the liquid crystal device
FIG. 6 is a block diagram of various wirings, peripheral circuits, etc. formed on a T array substrate.

21 is a timing chart showing operations of the data line driving circuit, the precharge circuit, and the sampling circuit when the inverted signal of the direction control signal is at the high level in the liquid crystal device of FIG. 20.

FIG. 22 is a block diagram showing a schematic configuration of an embodiment of an electronic device according to the present invention.

FIG. 23 is a cross-sectional view showing a liquid crystal projector as an example of an electronic device.

FIG. 24 is a front view showing a personal computer as another example of the electronic apparatus.

FIG. 25 is a perspective view showing a liquid crystal device using TCP as an example of an electronic device.

[Explanation of symbols]

1 ... TFT array substrate 2 ... Counter substrate 10 ... Liquid crystal panel 11 ... Pixel electrode 21 ... Common electrode 23 ... Light-shielding layer 30 ... TFT 31 ... Scan line 35 ... Data line 50 ... Liquid crystal layer 52 ... Sealing material 53 ... Surrounding area 101 ... Data line drive circuit 102 ... Mounting terminal 130, 131 ... Clocked inverter 132 ... Inverter 150 ... Signal capturing unit 151 ... Signal Propagation Unit 152 ... Return section 160 ... Transmission gate 200 ... Liquid crystal device 201 ... Precharge circuit 204 ... Precharge signal supply line 206 ... Precharge circuit drive signal line 301 ... Sampling circuit 304 ... Image signal supply line 306 ... Sampling circuit drive signal line 401 ... Drive circuit for precharge signal 402 ... Shift register 403 ... Buffer circuit 501 ... Image signal drive circuit 502 ... Shift register 503 ... Buffer circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 550 G09G 3/36

Claims (9)

(57) [Claims] 1. A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, switching means connected to each of the data lines and each of the scanning lines, and the switching means. A driving circuit for an electro-optical device, comprising: a pixel electrode connected to the pixel electrode; a sampling circuit for sampling the image signal and supplying the image signal to the data line; and a sampling circuit for supplying a control signal to the sampling circuit. 1
A shift register; a precharge circuit for supplying a precharge signal to the data line prior to the sampling period for supplying the image signal to the data line; and a first for supplying a control signal to the precharge circuit. Two
A drive circuit for an electro-optical device, comprising: a shift register, wherein a clock signal is supplied to the first and second shift registers from a common clock signal supply line. 2. A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, switching means connected to each of the data lines and each of the scanning lines, and the switching means. A driving circuit for an electro-optical device, comprising: a pixel electrode connected to the pixel electrode; a sampling circuit for sampling the image signal and supplying the image signal to the data line; and a sampling circuit for supplying a control signal to the sampling circuit. 1
A shift register; a precharge circuit for supplying a precharge signal to the data line prior to the sampling period for supplying the image signal to the data line; and a first for supplying a control signal to the precharge circuit. Two
A shift register, and a common clock signal supply line for supplying a clock signal to the first and second shift registers is arranged between the first shift register and the second shift register. A drive circuit for an electro-optical device characterized by the above. 3. A transfer start signal control means for outputting a first transfer start signal to the first shift register after outputting a second transfer start signal to the second shift register. Item 3. A drive circuit for an electro-optical device according to any one of items 1 and 2. 4. A plurality of data lines to which an image signal is supplied, a plurality of scan lines to which a scan signal is sequentially supplied, a switching means connected to the plurality of data lines and the plurality of scan lines, and A driving circuit for an electro-optical device comprising a pixel electrode connected to a switching means, the driving circuit having a plurality of first thin film transistors respectively interposed between the data line and the image signal supply line, A sampling circuit for sampling the image signal by conduction of one thin film transistor and supplying the data signal to the data line; and a plurality of second thin film transistors interposed between the precharge signal supply line and the data line, respectively. A precharge circuit that supplies the precharge signal to the data line by conduction of the second thin film transistor, and an input signal in synchronization with a clock signal. A signal capturing section for capturing, a signal propagating section for propagating the captured signal as an output signal, and a feedback section for returning an output signal from the signal propagating section to a signal input side of the signal propagating section in synchronization with a clock signal. Is provided in each stage, and a clock signal is supplied to the first and second shift registers from a common clock signal supply line. In the transfer direction corresponding to the first direction, the first drive signal for electrically connecting the first thin film transistor is sequentially output from each stage of the first shift register, and the second drive signal is supplied to the precharge circuit in the transfer direction. Data line driving means for sequentially outputting a second driving signal for conducting the second thin film transistor from each stage of the shift register, After outputting the transfer start signal, the driving circuit of the electro-optical device characterized by comprising a, a transfer start signal controlling means for outputting a first transfer start signal to the first shift register. 5. The first and second shift registers are bidirectional shift registers, and a transfer direction of the first and second shift registers is a direction control signal from a common direction control signal unit. The drive circuit for an electro-optical device according to claim 1, wherein the drive circuit is controlled based on the above. 6. The drive circuit for an electro-optical device according to claim 1, wherein the sampling circuit and the precharge circuit are provided in parallel. 7. The transfer start signal control means includes the second
Controlling the output start timing and pulse width of the second transfer start signal so that a predetermined time interval is provided between the output completion timing of the transfer start signal and the output start timing of the first transfer start signal. Claim 1 characterized by
A driving circuit for the electro-optical device according to claim 6. 8. An electro-optical device comprising the drive circuit of the electro-optical device according to claim 1. Description: 9. An electronic apparatus comprising the electro-optical device according to claim 8.