JP3536657B2 - Driving circuit for electro-optical device, electro-optical device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrooptical device drive having a clock signal phase difference correcting circuit which does not increase the area for the layout of the drive circuit, while surely eliminating a phase difference between a clock signal and an opposite-phase clock signal. SOLUTION: A clock signal phase difference correcting circuit 500 comprises a first buffer circuit a bistable circuit and a second buffer circuit all of which consist of inverters etc., the second buffer circuit being connected to the output part of the bistable circuit. At least an external clock signal input part is connected to a data line drive circuit 101 or a scanning line drive circuit 104 via the clock signal phase difference correcting circuit 500.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of an active matrix driving type electro-optical device by driving a thin film transistor (hereinafter referred to as TFT), an electro-optical device provided with the driving circuit, and an electro-optical device. Belongs to the technical field of the electronic device used, and in particular, a clock signal supplied to a driving circuit of a data line or a scanning line and a phase difference correcting means of a clock signal having an opposite phase to the clock signal (hereinafter, referred to as an opposite phase clock signal) The present invention belongs to the technical field of a drive circuit of an electro-optical device, an electro-optical device, and an electronic apparatus having the same.

[0002]

2. Description of the Related Art FIG. 18 shows an example of a conventional active-matrix-driven liquid crystal device driven by a TFT. FIG.
8, a transistor 30 is formed corresponding to each of the intersections of the scanning lines 31 and the data lines 35, and the scanning lines 31 of Y1 to Ym and the data lines 35 of S1 to Sn arranged vertically and horizontally, respectively. Many connected pixel electrodes 11 are provided on a substrate for a liquid crystal device. And
In addition to these, various peripheral circuits including a TFT as a component, such as the scanning line driving circuit 104, the data line driving circuit 101, and the sampling circuit 301, are provided on such a liquid crystal device substrate.

The data line driving circuit 101 supplies a driving signal to a sampling circuit driving signal line 306 which controls a sampling circuit 301 for writing an image signal VID supplied via an image signal line 304 to a data line 35. The shift register is configured to transfer data sequentially. Further, a shift register is configured in the first scanning line driving circuit 104 so as to sequentially transfer the scanning signal to the first scanning line 31.

[0004]

In the liquid crystal device having the above configuration, a clock signal CL output from an external control circuit (a clock signal for controlling the data line driving circuit 101 described later is denoted by CLX). A clock signal for controlling the scanning line driving circuit 104 is denoted as CLY), and an inverted phase clock signal CL _INV inverted by an external control circuit (for controlling the data line driving circuit 101 described later). An anti-phase clock signal is expressed as CLX _INV and an anti-phase clock signal for controlling the scanning line driving circuit 104 is expressed as CLY _INV. However, conventionally, a circuit as shown in FIG. And supplied into the liquid crystal device substrate. Then, the clock signal CL and the antiphase clock signal CL _INV are first supplied to the supply lines P1, P
1 'through the inverters I1 and I3 in the substrate for the liquid crystal device.
And then to each drive circuit via inverters I2 and I4.

When such a circuit is used, FIG.
As shown in (b), a phase difference T occurs between the supply lines P1 and P1 ', which is caused by the inverters I1 and I1.
3, and even after passing through the inverters I2 and I4. That is, as shown in FIG. 19 (b), in the connection lines P2 and P2 ′ between the inverter I1 and the inverter I2 and between the inverter I3 and the inverter I4, the supply connected to the output of the inverters I2 and I4. In the lines P3 and P3 ′, the clock signal CL and the anti-phase clock signal CL _INV having the phase difference T with respect to the clock signal CL are to be propagated. Therefore, in a shift register included in the data line driving circuit 101 and the scanning line driving circuit 104,
Once the phase difference T occurs between the clock signal CL and the opposite-phase clock signal CL _INV , the signal waveform deteriorates, and the start signal SP (for controlling the data line driving circuit 101 to be described later) normally operates. Start signal SP
X, and a clock signal for controlling the scanning line driving circuit 104 is denoted by SPY) cannot be transferred to each stage, which causes a problem that a malfunction occurs.
Such a problem also occurs in the shift register of the scan line driver circuit 104.

Further, when a supply line for supplying the clock signal CL and the anti-phase clock signal CL _INV is routed on the substrate for the liquid crystal device, the clock signal CL and the anti-phase clock signal CL _INV deteriorate due to the capacity of the clock signal supply line. However, an appropriate waveform cannot be obtained, and as a result, the drive signal cannot be normally transferred to each stage, causing a problem that a malfunction occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is an object of the present invention to correct a phase difference between a clock signal and a clock signal having an opposite phase to the clock signal to improve a scanning line driving circuit and a data line driving circuit. It is an object to provide a driving circuit, an electro-optical device, and an electronic device of an electro-optical device which can be operated in a different manner.

[0008]

A drive circuit for an electro-optical device according to the present invention comprises a plurality of data lines to which an image signal is supplied;
Driving an electro-optical device including a plurality of scanning lines to which a scanning signal is supplied, switching means provided corresponding to intersections of the data lines and the scanning lines, and pixel electrodes connected to the switching means. A driving circuit having a shift register for transferring a predetermined signal based on a clock signal and a clock signal having an opposite phase to the clock signal, wherein the clock signal and the clock having the opposite phase are provided. The signal is supplied to the driving unit via a clock signal phase difference correcting unit, and the clock signal phase difference correcting unit includes a pair of first buffer circuits, a bistable circuit, and a pair of second buffer circuits. A clock signal is input to one of the first buffer circuits, and a signal output from the one first buffer circuit constitutes the bistable circuit. Is input to the first logic means, said first signal output from the logic means, said is input to second logic means constituting a bistable circuit, the first
And the clock signal having the opposite phase is input to the other first buffer circuit and output from the other first buffer circuit. The signal output from the second logic means constituting the bistable circuit is inputted to the second logic means constituting the bistable circuit, and the signal outputted from the second logic means is inputted to the first logic means constituting the bistable circuit. Is input to the other second buffer circuit connected to the output unit of the second logic means, and the second buffer circuit includes a plurality of inverter circuits connected in cascade, and Each of the pair of first buffer circuits is formed to be larger than the connected inverter circuit of the preceding stage, and the size of the inverter circuits forming the pair of first buffer circuits is different from that of the inverter circuit. While the magnitude of the inverter circuit constituting the circuit is the same, the inverter circuit constituting the second buffer circuit is formed to be larger than the inverter circuit constituting the bistable circuit, the first
Between the buffer circuit, the bistable circuit, and the second buffer circuit, a first portion formed of a polysilicon film among wirings for transmitting the clock signal and the clock signal having the opposite phase includes the clock signal. The line width and length of the wiring that propagates and the line width and length of the wiring that propagates the clock signal of the opposite phase are aligned with each other,
A second portion of the wiring for transmitting the clock signal and the clock signal having the opposite phase, the second portions having different lengths, is formed of an aluminum film.

According to the driving circuit of the electro-optical device, the clock signal and the clock signal having the opposite phase are supplied to the driving means through the supply line of the clock signal and the input portion of the clock signal having the opposite phase to the clock signal, respectively. However, clock signal phase difference correcting means is provided between these signal lines. Therefore, the clock signal phase difference correcting means is configured such that, for example, the input part of the clock signal input from the outside of the liquid crystal device is supplied to the driving means via the common clock signal phase difference correcting means. It is not necessary to provide each stage of the shift register of the means. Therefore, the size of the driving circuit of the electro-optical device can be reduced, and the size of the pixel can be reduced, so that a high-definition electro-optical device can be provided. Furthermore, the clock signal and the opposite-phase clock signal whose phase difference has been corrected are supplied to the driving means, and the transfer of the signal by the shift register is performed without malfunction.

According to the driving circuit of the electro-optical device, the clock signal supplied from the external clock signal supply unit is first corrected for the rounding of the waveform by the first buffer circuit and supplied to the bistable circuit. Is done. Next, in the bistable circuit, the phase difference between the clock signal and the opposite-phase clock signal is corrected by the positive feedback action. The clock signal and the opposite-phase clock signal output from the bistable circuit are supplied to the shift register of the driving means via the second buffer circuit, so that the capacity added after the output terminal of the second buffer circuit is reduced. Even if it increases, the driving capability of the bistable circuit does not decrease. Therefore, the clock signal whose phase difference has been corrected and the opposite phase clock signal are reliably supplied to the shift register, and malfunction of the shift register is reliably prevented.

According to the driving circuit of the electro-optical device, the clock signal is inputted to the first logic means, and the anti-phase clock signal is inputted to the second logic means via the supply line. The clock signal is output from the first logic means as a clock signal whose polarity is inverted by the first logic means, that is, an opposite phase clock signal. Similarly, the opposite phase clock signal is output by the second logic means. The clock signal having the inverted polarity is output from the second logic means. And the output unit of the first logic means,
The input of the second logic is connected to the input of the second logic, and the output of the second logic is connected to the input of the first logic. Therefore, the antiphase clock signal output from the first logic means is input to the second logic means together with the antiphase clock signal supplied from the input part of the antiphase clock signal. The clock signal output from the second logic means is input to the first logic means together with the clock signal supplied from the input part of the clock signal. That is, in the first and second logic means, positive feedback is applied to the clock signal and the opposite-phase clock signal, and the clock signal and the opposite-phase clock signal supplied from the respective supply lines are output. Correction is performed to eliminate the phase difference.

The clock signal and the opposite-phase clock signal having no phase difference therebetween as described above are input to a second buffer circuit connected to the first and second logic means, and The buffer circuit supplies the clock signal and the opposite-phase clock signal to the driving unit via a supply line. Therefore, the capacity added to the respective output sections of the first and second logic means depends on the connection paths between the first and second logic means and the second buffer circuit, and the first and second logic means. It becomes substantially equal to the path of the positive feedback of the second logic means, thereby preventing a change in the potential of the output section of the first and second logic means due to a capacitance difference. As a result, the signal drive capability for the positive feedback by the first and second logic means is maintained satisfactorily, the phase difference can be almost completely eliminated, and malfunction of the drive means is reliably prevented. be able to.

It is preferable that the size of the inverter circuit forming the pair of first buffer circuits is the same as the size of the inverter circuit forming the bistable circuit. Further, a wiring for supplying the clock signal and the clock signal of the opposite phase to each of the plurality of inverters constituting the clock signal phase difference correcting means is formed of a polysilicon film, and a wiring for connecting the plurality of inverters is provided. Is preferably formed of an aluminum film.

According to the driving circuit for the electro-optical device, the capacitance values of at least two wires of the clock signal phase difference correcting means are substantially constant. That is, from the clock signal supply line to the first logic means, further from the first logic means to the second buffer circuit without passing through the positive feedback path, and from the clock signal supply line to the second buffer circuit. The capacitance value of each wiring is substantially constant between the wiring path to the second buffer circuit connected to the second logic means through the wiring path for positive feedback. The same applies to the wiring route on the second logic means side. Therefore, the capacitance added to the branch point of each wiring is substantially constant at all points, and the potential of each branch point is reliably prevented from fluctuating, so that the clock signal phase difference correcting means operates stably. Become.

The second buffer circuit includes a plurality of inverter circuits cascaded, and each of the cascaded inverter circuits has a size two to four times as large as that of the preceding inverter circuit. May be used.

With the above configuration, it is possible to output a clock signal having no phase difference without reducing the driving capability of the inverter for the positive feedback action by the bistable circuit.

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

According to another aspect of the invention, an electro-optical device includes the above-described electro-optical device driving circuit.

According to the electro-optical device described above, since the driving circuit for the above-described electro-optical device is provided, the shift register of the driving means can be reliably operated without malfunction by the clock signal having the same phase and the opposite-phase clock signal. It can be operated, and a display of a liquid crystal device or the like which is an example of the electro-optical device can be favorably realized. Further, the clock signal phase difference correcting means for eliminating the phase difference is not provided at each stage of the shift register, but is provided between the supply unit of the clock signal or the opposite phase clock signal and the driving means. Therefore, the layout area of the shift register can be reduced, and as a result, high integration of peripheral circuits can be achieved. Therefore, a very small liquid crystal device having a high-definition electro-optical device is provided.

According to another aspect of the invention, there is provided an electronic apparatus including the above-described electro-optical device.

According to this electronic apparatus, the electronic apparatus includes the above-described electro-optical device according to the present invention, and can realize a favorable display based on the clock signal having the same phase and the opposite-phase clock signal. Further, in the electro-optical device, a clock signal phase difference correction unit for eliminating the phase difference is not provided at each stage of the shift register, but an input unit for the clock signal or the opposite phase clock signal, Since the liquid crystal device is provided between the light emitting device and the driving means, a miniaturized liquid crystal device having a high-definition electro-optical device can reduce the size of an electronic device.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

(Configuration of Liquid Crystal Device) The configuration and operation of an embodiment of a liquid crystal device as an example of the electro-optical device according to the present invention will be described with reference to FIG. FIG. 1 is an equivalent circuit diagram showing a plurality of pixels of the liquid crystal device.

First, as shown in FIG. 1, a plurality of pixels formed in a matrix and constituting a screen display area of the liquid crystal device according to the present embodiment have a plurality of TFTs 30 formed in a matrix as switching elements, for example. And
A data line 35 for supplying an image signal is electrically connected to the source of the TFT 30. The image signals to be written to the data lines 35 are S1 and S
2,..., Sn may be supplied line-sequentially, or may be supplied to a plurality of adjacent data lines 35 for each group. A scanning line 31 for supplying a scanning signal is electrically connected to the gate of the TFT 30, and each of the scanning lines Y1, Y2,
, Ym are configured so that a scanning signal is applied in a pulsed manner at a predetermined timing in the order of the scanning lines Y1, Y2,..., Ym. The pixel electrode 11 is electrically connected to the drain of the TFT 30. By turning on the TFT 30 serving as a switching element for a predetermined period, a pixel signal supplied from the data line 35 is output at a predetermined timing. The data is written to the pixel electrode 11. An image signal of a predetermined level written in the liquid crystal via the pixel electrode 11 is held for a certain period between the image signal and a counter electrode (described later) formed on a counter substrate (described later). The liquid crystal modulates light by changing the orientation and order of a molecular group according to the applied voltage level, thereby enabling gray scale display.

Such a liquid crystal device substrate may be provided with various peripheral circuits including TFTs such as a scanning line driving circuit, a data line driving circuit, and a sampling circuit in addition to the above-described components.

For example, in the example shown in FIG. 1, a scanning line driving circuit 104 for supplying a scanning signal to the scanning line 31, a data line driving circuit 101 for supplying a driving signal to the sampling circuit 301, and an image in an ON state. Signal to data line 3
5 is provided on the substrate for the liquid crystal device.

The data line driving circuit 101 and the scanning line driving circuit 104 each include a shift register. The data line drive circuit 101 is configured so that a drive signal for writing an image signal to the data line 35 is sequentially output from each output stage of the shift register. In addition, the scanning line driving circuit 104
Are sequentially output from each output stage of the shift register.

As described later, these shift registers are provided with gate means such as a clocked inverter or a transmission gate at each stage, and a clock signal or a clock signal having a phase opposite to that of the clock signal is alternately provided for each stage. By inputting an anti-phase clock signal), the drive signal for the data line or the scanning line is sequentially transferred at a timing synchronized with a half cycle of the clock signal.

As shown in FIG. 1, the liquid crystal device according to the present embodiment further comprises a driving circuit having an input section CLX and CLX _INV for supplying a clock signal and an antiphase clock signal, and a shift register of the data line driving circuit 101. A clock phase difference correction circuit 500 is provided between the
A clock signal CLX supplied from the external control circuit
The phase of the anti-phase clock signal CLX _INV is adjusted by the clock phase difference correction circuit 500, and then the data is supplied to the data line driving circuit 101.

Similarly, in the scanning line driving circuit 104, a clock phase difference correction circuit 500 is provided between CLY and CLY _INV and driving means having a shift register of the scanning line driving circuit 104. The clock signal CLY and the anti-phase clock signal CLY _INV supplied from the control circuit are adjusted by the clock phase difference correction circuit 500 and then supplied to the scanning line driving circuit 104.

Accordingly, a favorable operation of writing an image signal to each pixel can be performed without causing a malfunction of the data line driving circuit 101 and the scanning line driving circuit 104. Hereinafter, the configuration and operation of the clock signal phase difference correction circuit of the present embodiment will be described in more detail.

(Configuration of Clock Phase Difference Correction Circuit) In this embodiment, as shown in FIG. 1, a clock signal phase difference correction circuit 500 having a bistable circuit is provided on a liquid crystal device substrate, and a clock signal CL Anti-phase clock signal CL _INV
Are configured to match the phases.

As shown in FIG. 2A, the basic configuration of the clock signal phase difference correction circuit 500 according to this embodiment is the first configuration.
The circuit includes a buffer circuit 501, a bistable circuit 502, and a second buffer circuit 503. Each circuit includes an inverter 501a, 501b, 502a, 502b, 5
03a and 503b.

As shown in FIG. 2B, the clock signal C
L is R1 and R1 with _respect to the antiphase clock signal CL _INV.
Even if a phase difference occurs for the period T at the point ', the phase difference is corrected by the bistable circuit 502 in the present embodiment, and a phase difference occurs at the points R3 and R3' output from the bistable circuit 502. do not do.

In the clock signal phase difference correction circuit 500, the transistors in the circuit that supplies the clock signal CL and the inverted clock signal CL _INV in the buffer circuit 501 composed of the inverters 501a and 501b complement the driving capability of the circuit. , The output of one inverter 502 a of the bistable circuit 502 is connected to the other inverter 5.
02b and the output of the other inverter 502b are supplied to the input of the one inverter 502a, respectively, so that the input signals of the inverters 502a and 502b are subjected to positive feedback to eliminate the phase difference. ing.

In the clock signal phase difference correction circuit 500 of the present embodiment, after the bistable circuit 502,
A second buffer circuit 503 is provided, and the function of the second buffer circuit 503 prevents the driving capability of the bistable circuit 502 from being reduced. That is, the bistable circuit 50
In the case where the clock signal CL and the anti-phase clock signal CL _INV are supplied to each drive circuit by drawing the clock signal line from 2, the clock signal CL and the anti-phase clock signal CL _INV deteriorate due to the capacity of the clock signal line. It is possible. However, in the present embodiment, the lowering of the driving capability of the bistable circuit 502 is prevented by the second buffer circuit 503, and the clock signal CL and the opposite-phase clock signal _CLINV are satisfactorily supplied to each driving circuit. Become.

To prevent signal deterioration due to the capacity of the clock signal line, a clock signal phase difference correction circuit may be provided at each stage of the shift register. After the ballast circuit 502, the second
By providing the buffer circuit 503, even if a clock signal phase difference correction circuit is not provided for each of the latch circuits constituting the shift register, the clock signal and the opposite phase clock signal whose phase difference is well corrected can be driven. Can be supplied to Therefore, the size of the liquid crystal device can be reduced without increasing the layout area of the driving circuit.

A modification of the configuration of the clock phase difference correction circuit will be described with reference to FIGS. 3 (a) and 3 (b).

Each of the bistable circuits 5 shown in FIGS.
02 is the NAND circuit 502c, 502d, or NOR
2 except that the circuit is composed of circuits 502e and 502f.
The configuration is the same as that of the present embodiment shown in FIG.

The NAND circuit 502c shown in FIG.
In the case of using the signal 502d, even if there is a period in which both are high level signals or a period in which both are low level signals due to the phase difference between the clock signal CL and the opposite phase clock signal CL _INV , the clock signal CL or by reverse-phase clock signal CL the timing at which the polarity of the _INV is changed, NAND circuit 502c, the output of 502d change simultaneously. For example, when the input signal d1 of the NAND circuit 502c is at a high level and d3 is at a low level, N
The output signal d2 of the AND circuit 502c goes to a high level, which causes the input signal d4 of the NAND circuit 502d to go high.
Becomes high level and the other input signal d6 is a high level signal, the output signal d5 of the NAND circuit 502d becomes a low level signal. In such a case,
Assuming that the output signal of the NAND circuits 502c and 502d changes from the initial state of each of these signals to the low-level input signal d6, the output signal d5 of the NAND circuit 502d changes to the high level. Accompanying NA
The input signal d3 of the ND circuit 502c also changes to a high level. Therefore, the output signal d2 of the NAND circuit 502c changes to low level, and the states of all signals are stabilized. Thus, the clock signal CL and the antiphase clock signal CL
Due to the phase difference of _INV, the period when both become high level signal,
Or even if there is a period during which both signals are low level,
Then, at the timing when the polarity of any signal is inverted, N
AND circuit 502c, can be changed at the same time the output signal d2, d5 of 502d, eliminating the phase difference between the clock signal CL and the opposite-phase clock signal CL _{IN V} was present in the input stage.

Also, as shown in FIG. 3B, even when the bistable circuit is constituted by NOR circuits 502e and 502f, the operation is the same as that of the NAND circuits 502c and 502d.

As described above, the bistable circuit 502 is connected to the NAND
Circuit or a NOR circuit, the data line driving circuit 101 or the scanning line driving circuit 10 is driven by the clock signal CL having no phase difference and the inverse phase clock signal CL _INV.
4 can be driven and a malfunction-free liquid crystal device can be provided.

(Detailed Configuration of Clock Signal Phase Difference Correction Circuit 500) When the configuration as in the above-described embodiment is adopted, the on-resistance of the inverter circuits 503a and 503b of the second buffer circuit 503 shown in FIG. Is preferably set as low as possible. This is because if the on-resistance of the final-stage inverter circuits 503a and 503b is high,
This is because the output signal becomes dull, the voltage of the signal applied to the clocked inverter of the shift register 401 decreases, and the shift register 401 cannot be driven. Therefore, it is necessary to design the inverter circuits 503a and 503b to have a sufficient driving capability with respect to the load and the driving frequency of the clock signal line electrically connected to the second buffer circuit 503.

The capacitive load of the signal transmission path constituted by the inverters A, B, C or A ', B', C 'shown in FIG. 4 and the inverter A, C' or A ', C It is preferable to design so that the capacity load of the signal transmission path is the same. Therefore, inverters A,
It is preferable that the sizes of A ', B and B' are designed to be substantially the same. This is to ensure that the potential of one of the paths does not become dominant, and that the phase difference can be corrected reliably.

The clock signal phase difference correction circuit 500
In the second buffer circuit 503, the inverter circuits 503a and 503b may be provided in a single stage. When the capacity added to the clock signal line and the antiphase clock signal line is large, for example, as shown in FIG. After the stages or the inverter circuits are cascaded, they may be connected to the clock signal line and the antiphase clock signal line. At this time, the cascade-connected inverter circuits are designed to be about 2 to 4 times as large as the size of the preceding inverter circuit. In the case of a CMOS cascade, if the size of the next-stage inverter circuit electrically connected to the own-stage inverter circuit is set to be approximately e (2.72) times, the total size of the second buffer circuit 503 is increased. The delay time can be minimized (e times theorem). For example, FIG.
, The inverter D (D ′) is connected to the inverter C
It is preferable to form it in (C ′) × e (2.72) times the size. Inverter E (E ') is connected to inverter D
It is preferable to form it in (D ′) × e (2.72) times the size. Further, at this time, it is preferable that the on-resistance of the final-stage inverter E (E ′) is formed so as to be as small as possible.

(Configuration of Driving Circuit) FIGS. 6 and 7 show an example of the configuration of the clock signal phase difference correction circuit of the above embodiment and a data line driving circuit connected to the clock signal phase difference correction circuit. It will be described with reference to FIG.

As shown in FIG. 6, the data line driving circuit 10
1 is a shift register 401 and a buffer circuit 402
And a sampling circuit drive signal selection circuit 403.

In this embodiment, the shift register 401
In the transfer direction corresponding to the direction from A to B shown in FIG. 6, sequentially outputs the sampling circuit drive signal from each stage of the shift register 401 and supplies the signal to the sampling circuit 301 via the selection circuit 403 or the buffer circuit 402. It has the function to do.

Although the scanning line driving circuit 104 is not shown in the drawing, the scanning line driving circuit 104 includes a shift register, a selection circuit, a buffer circuit and the like similar to the data line driving circuit 101.

The shift register 401 includes, for example, clocked inverters 130 and 132 as shown in FIG.
And an inverter 131.

The clocked inverter 130 has a function of taking in the start signal SPX supplied to the input signal line 107 in synchronization with the clock signal CLX. Further, the inverter 131 has a function of transmitting the received signal as an output signal from the output signal line 108. Further, the clocked inverter 132 synchronizes the clock signal CLX and the inverted clock signal CLX _INV with the output signal from the inverter 131. Is fed back to the signal input side of the inverter 131.

Each stage of the latch circuit constituting the shift register 401 is composed of a circuit obtained by combining the above-described clocked inverter and inverter, and
Since the clock signal input to the clocked inverter of the adjacent stage is a clock signal having an opposite phase to the clock signal of the previous stage, the clock signal is taken in at the first stage at the timing t0 shown in FIG. Is captured at a timing t1 which is shifted by a half cycle of the clock signal CLX, and an output signal having the same width as the start signal SPX is obtained at the second stage. Hereinafter, in each stage, a signal is sequentially fetched at a timing shifted by a half cycle of the clock signal CLX and a signal having the same width as one cycle of the clock signal CLX is output. The transfer is performed at a timing shifted by a half cycle of CLX.

A pulse signal shifted by a half cycle of the clock signal CLX output from each stage as described above is
The waveform is shaped as a sampling circuit drive signal via the selection circuit 403 and the buffer circuit 402. Selection circuit 4
03 is provided with a NAND circuit as shown in FIG.
The output signal of the next output stage together with the output signal from the output stage of the corresponding shift register 401 is input to the NAND circuit. Therefore, for the TFT 302 of the sampling circuit 301, as shown in FIG. 7, during the period in which the output signals of the adjacent output stages are both at the high level, the pulse-shaped drive signals that are at the high level are in the order of Q1 to Qm. They will be output sequentially.

In this embodiment, since the data line driving circuit 101 as described above is provided, even if the dot frequency is very high, the clock signal CLX and the opposite phase clock signal CLX supplied to the shift register 401 are provided.
Sampling circuit 301 while reducing the frequency of _INV
Each TFT 302 can be provided with a necessary and sufficient sampling period, and reliable writing of the image signals VID1 to VID6 to the data line 35 can be realized. Further, also in the scanning line driving circuit 104 configured in the same manner as the data line driving circuit 101, the scanning signal can be surely written to the scanning line 31, and as a result, a favorable display operation can be performed.

(Configuration of Liquid Crystal Device) Next, a specific configuration example of a liquid crystal device having the above-described clock signal phase difference correction 500 will be described in detail with reference to FIGS. FIG.
9 is a block diagram showing the configuration of various wirings, peripheral circuits, and the like provided on the liquid crystal device substrate in the embodiment of the liquid crystal device.

In FIG. 8, the liquid crystal device 10 includes a liquid crystal device substrate 1 made of, for example, a quartz substrate, hard glass, a silicon substrate, or the like. On the liquid crystal device substrate 1, a plurality of pixel electrodes 11 arranged in a matrix, a plurality of data lines 35 arranged in the X direction, each extending in the Y direction, and a plurality of data electrodes 35 arranged in the Y direction. The scanning lines 31 each extending along the X direction, the intervening state between each data line 35 and the pixel electrode 11, and the conductive state and the non-conductive state therebetween are supplied via the scanning line 31. And a plurality of TFTs 30 as an example of a pixel driving unit that controls each according to a scanning signal. Further, on the liquid crystal device substrate 1, a capacitance line 31 'which is a wiring for a storage capacitor is formed substantially in parallel along the scanning line 31 or by using a lower part of the preceding scanning line.

On the liquid crystal device substrate 1, a precharge circuit 201 for supplying a precharge signal of a predetermined voltage level to the plurality of data lines 35 in advance of the image signal, respectively;
A sampling circuit 301 which samples an image signal and supplies each to the plurality of data lines 35, a data line driving circuit 101, and a scanning line driving circuit 104 are formed.

The scanning line driving circuit 104 is provided with a shift register, and has a positive power supply VDDY and a negative power supply VSSY supplied from an external control circuit (not shown), a start signal SPY, a reference clock signal CLY, and a reverse power supply. Based on the phase clock signal CLY _{INV and the} like, a scanning signal is applied to the scanning line 31 line by line at a predetermined timing.

Similarly, the data line driving circuit 101
The shift register is provided with a positive power supply VDDX and a negative power supply VSSX supplied from an external control circuit (not shown), a reference clock signal CLX, a clock signal CLX _{INV having} an opposite phase, a start signal SPX, and the like. ,
In order to sample the image signals VID1 to VID6, a sampling circuit drive signal is applied in a pulse-wise line-sequential manner for each data line 35. The sampling circuit drive signal is supplied to the sampling circuit drive signal line 306 in synchronization with the timing at which the scan line drive circuit 104 applies the scan signal.
Is supplied via

As will be described later, the common electrode potential signal LCCOM is supplied to the upper and lower conductive members 106 and is applied to the common electrode (not shown) formed on the opposite substrate (not shown) via the upper and lower conductive members 106. Applied.

Next, the precharge circuit 201 includes a TFT
A precharge signal line 204 is connected to the source electrode of the TFT 202, and a precharge circuit drive signal line 206 is connected to the TFT 20.
2 gate electrodes. Then, power of a predetermined voltage required for writing the precharge signal NRS is supplied from an external power supply via a precharge signal line 204, and an image signal is supplied to each data line 35 via a precharge circuit drive signal line 206. The precharge circuit drive signal NRG is supplied from an external control circuit so that the precharge signal NRS is written at a timing preceding the precharge circuit drive signal NRS.
The precharge circuit 201 preferably supplies a precharge signal (image auxiliary signal) corresponding to an image signal of an intermediate gradation level.

The sampling circuit 301 includes a TFT 302
Is provided for each data line 35, and the image signal line 304 is connected to the source electrode of the TFT 302. A sampling circuit drive signal line 306 is connected to a gate electrode of the TFT 302. Therefore, the data line drive circuit 101 switches the sampling circuit drive signal line 306
TFT to which sampling circuit drive signal is input via
Reference numeral 302 denotes a conductive state, and an image signal VID supplied via an image signal line 304 from an external control circuit (not shown)
1 to VID 6 are written to each data line 35.

In the present embodiment, the sampling circuit drive signal is simultaneously applied to the gate electrodes of the six adjacent TFTs 302, and a plurality of data lines 35 are sequentially selected for each group. Further, the image signal is input to the external control circuit as a serial signal having a predetermined dot frequency, and is expanded into six-phase parallel signals by the external control circuit.
ＶVID6 are supplied to the data line 35 via the TFT 302.

The reason why the image signal is phase-expanded using the plurality of image signal lines 304 is to reduce the drive frequency of the shift register even when the dot frequency of the image signal is high. If the drive frequency of the shift register can be reduced, the load on an external control circuit that supplies a clock signal to the shift register can be reduced, and the current consumption of the shift register can be reduced. Further, the life of the TFT constituting the shift register can be extended.

The number of phase expansions of the image signal is determined by the writing capability of the TFT 302 constituting the sampling circuit 301. Although the number of phase expansions of the image signal is not limited, there is an advantage that a smaller number of phase expansions of the image signal can reduce the cost of the external control circuit. Also, the TF to be selected at the same time
The number of T302s does not necessarily have to be equal to the number of phase expansions of the image signal, and may be smaller than the number of phase expansions.

Further, the number of phase expansions of the image signal is set to 3, 6, 1
If the number is set to a multiple of 3, such as 2, 18, 24,..., The image signal line 304 can be formed in a multiple of 3, which is advantageous for video display. This is because the color image signal is a multiple of 3 because of the fact that the color image signal is composed of signals related to three colors (red, green, and blue) when controlling video display such as NTSC display and PAL display. This is because it is preferable for simplifying the circuit. Needless to say, the image signal lines 304 are required at least for the number of phase expansions of the image signal.

Then, in the liquid crystal device 10 of the present embodiment configured as described above, the clock signal phase difference correction circuit 500 having the above-described configuration, as shown in FIG. It is provided between the input part of the phase clock signal CL _INV and the data line driving circuit 101 and the scanning line driving circuit 104. The location of the clock signal phase difference correction circuit 500 is not limited to the example shown in FIG. FIG. 9 shows another configuration example of the liquid crystal device. 9 has almost the same configuration as that of FIG. 8, except that the scanning line driving circuit 104 is provided on both sides of the scanning line 31, and the scanning line driving circuit 104 on one side and the clock signal CLY have opposite phases. A clock signal phase difference correction circuit 500a is provided between the input portion of the clock signal CLY _INV , and a clock signal is provided between the scanning line driving circuit 104 on the other side and the input portion of the clock signal CLY and the opposite phase clock signal CLY _INV. Each of the signal phase difference correction circuits 500b is provided. With this configuration, the left and right scanning line drive circuits 10
4 can be more reliably prevented from shifting the timing of the scanning signal supplied to the scanning line 31.

As described above, one point between the input part of the clock signal CLX and its inverse phase clock signal CLX _INV and the data line driving circuit 101, and the clock signal CLY and its inverse phase clock signal CLY _INV and the scanning line driving circuit 104
The clock signal phase difference correction circuit 500 is provided at one location between
00 and the data line driving circuit 101 and the scanning line driving circuit 10
In the case where the clock signal line is extended between the clock signal line 4 and the signal line 4, the signal may be deteriorated due to the capacity of the clock signal line.

However, as described above, the clock signal phase difference correction circuit 500 according to the present embodiment includes the bistable circuit 5
Since the second buffer circuit 503 is provided at the subsequent stage of the second buffer circuit 02 and the second buffer circuit is formed with an appropriate size, even when the clock signal phase difference correction circuit 500 is arranged as in the present embodiment. In addition, the driving capability of the clock signal phase difference correction circuit 500 does not decrease, and the phase of the clock signal can be reliably adjusted. Less than,
A detailed configuration of the clock signal phase difference correction circuit 500 according to the present embodiment will be described. The clock signal phase difference correction circuits 500a and 500b shown in FIG. 9 have the same configuration as the clock signal phase difference correction circuit 500.

Further, as an example of pattern layout, when the routing resistance of a clock signal having a phase opposite to that of a clock signal changes, a phase difference occurs between the signals. Therefore, a polysilicon film having a high resistance (the same film as the scanning line is used). The wiring routed during formation) has the same line width and length so that the clock signal and the opposite phase clock signal have substantially the same resistance, and the part where the wiring length changes is a low-resistance aluminum film (the same film as the data line). It is preferable that the wire is drawn around in (Forming).
Accordingly, since there is no resistance difference between the wirings, the phase difference between the clock signal input from the outside and the opposite phase clock signal can be substantially equalized, and a liquid crystal device free from malfunction can be provided.

For example, FIG. 10 is a diagram showing an example of a pattern layout of the clock signal phase difference correction circuit 500 shown in FIG. 11, in which the clock signal CL and the inverted phase clock signal CL _INV are converted into the inverters A, A ', B , B ', C,
Wirings a, a ', b, b', c, c ', d, and d that are routed by a polysilicon film having a high resistance (for example, formed of the same film as the scanning line) for supplying to C', D, and D ''Has the same line width and length for each inverter, and is configured not to change the routing resistance of the clock signal CL and the antiphase clock signal _CLINV . Further, the portions e1 to e8 where the length of the wiring is changed are configured to be routed by a low-resistance aluminum film (for example, formed of the same film as the data line) or the like, so that a resistance difference in the wiring does not occur.

Further, regarding the size of each inverter,
As shown in FIG. 10, the inverters A, A ', B, and B' are formed to have the size of the width w1 and the length h1, whereas the inverters C and C 'at the next stage have the width w1 and the length h2 (>). h1) and the inverters A, A ', B, B'. Further, the next-stage inverters D and D7 'have a width w2 (>
w1), a length h2, and a size larger than the inverters C and C ′. In this way, the inverter circuits connected in cascade are designed to be approximately two to four times as large as the inverter circuit of the preceding stage.

With the above configuration, even when the clock signal phase difference correction circuit 500 is provided between the data line driving circuit 101 or the scanning line driving circuit 104 and the input section of the clock signal and the opposite phase clock signal, the positive and negative clock signal phase correction circuits can be used. Without reducing the drive capability of the inverter for the feedback action, FIG.
A clock signal CL having a phase difference T as shown in FIG.
Even when the inverted clock signal CL _INV is supplied, the supply lines R3 and R3 ′ on the second buffer circuit 503 side are provided.
, A clock signal and an opposite-phase clock signal having no phase difference can be output.

Further, the clock signal phase difference correction circuit 50
0 can be installed in a corner portion of the liquid crystal device 10 or the like, and the data line driving circuit 101 and the scanning line driving circuit 104
Without increasing the layout area of the liquid crystal device 10.
Can be reduced in size. In particular, in the case of a configuration in which feedback is performed by a bistable circuit as in the clock signal phase difference correction circuit of the present embodiment, an inverter circuit having a complementary TFT structure is required, and the inverter circuit having a complementary TFT structure is required to have a positive polarity. Power supply and negative power supply need to be routed. However, in the present embodiment, such a circuit requiring a relatively large occupation area on the liquid crystal device substrate 1 is placed in a corner portion of the liquid crystal device 10 which does not affect the arrangement of the peripheral circuits. It can be installed and does not hinder high integration of peripheral circuits. Therefore, according to the present embodiment, it is possible to provide a small liquid crystal device which does not malfunction and incorporates a highly integrated peripheral circuit.

As shown in FIG. 9, a clock signal phase difference correction circuit 50 is connected to each of the two scanning line driving circuits 104.
0a, 500b, any clock signal phase difference correction circuit 500a, 50b.
Since 0b can be provided at a position that does not affect the arrangement of the scanning line driving circuit 104, high integration of the scanning line driving circuit 104 is not hindered.

When a clock signal is supplied not only to the scanning line driving circuit 104 but also to a plurality of driving circuits, the clock signal phase difference correction of the present invention is performed so that the phase can be corrected before each driving circuit. A circuit may be provided. Accordingly, it is possible to prevent a shift of a signal output from each drive circuit.

In the present embodiment, the shift registers in each drive circuit are of one series. However, when a plurality of series of shift registers are used, the number of clock signal positions corresponding to the number of series is determined. It is necessary to provide a phase difference correction circuit. That is, when using N (N = 1, 2,...) Series shift registers, N clock signal phase difference correction circuits may be provided. With such a configuration, malfunctions can be prevented in all the series of shift registers.

The present invention also relates to a data line driving circuit 101.
Alternatively, not only the shift register operation of the scan line driving circuit but also a wide range of effects can be exerted for a circuit which is driven by using an inverted signal of a certain signal.

The clock signal phase difference correction circuit, the data line driving circuit, the sampling circuit, or the scanning line driving circuit as described above is provided for each of the TFTs 30 in the pixel region.
It can be formed in the same thin film forming step as above, which is advantageous in manufacturing.

(Structure of Liquid Crystal Device) FIGS. 12 and 13 show an example of a liquid crystal device 10 in which the above-described substrate for a liquid crystal device and a counter substrate are attached to each other. FIG. 12 is a plan view of the entire liquid crystal device, and FIG. 13 is a sectional view taken along line HH ′ of FIG.
As shown in FIGS. 12 and 13, the precharge circuit 201 and the sampling circuit 301 are provided on the liquid crystal device substrate 1 at positions facing the light-shielding peripheral partition 53 formed on the counter substrate 2. The data line driving circuit 101 and the scanning line driving circuit 104 are provided on a narrow and elongated peripheral portion of the liquid crystal device substrate 1 which does not face the liquid crystal layer 50.

12 and 13, on the liquid crystal device substrate 1, a screen display area defined by a plurality of pixel electrodes 11 (ie, an image is actually displayed by a change in the orientation of the liquid crystal layer 50). A sealing material 52 made of a photocurable resin and surrounding the liquid crystal layer 50 by bonding the two substrates around the liquid crystal device region) is provided along the screen display region. A light-shielding peripheral partition 53 is provided between the screen display area on the counter substrate 2 and the sealing material 52.
Is provided.

When the liquid crystal device substrate 1 is later placed in a light-shielding case provided with an opening corresponding to the screen display area, the peripheral parting 53 may cause the screen display area to be out of the case due to a manufacturing error or the like. A band-shaped light shield having a width of at least 500 μm or more around the screen display area so as not to be hidden by the edge of the opening, that is, to allow a displacement of about several hundred μm with respect to the case of the liquid crystal device substrate 1, for example. It is formed from a conductive material. Such a light-shielding peripheral partition 53 is formed on the counter substrate 2 by, for example, sputtering, photolithography, and etching using a metal material such as Cr (chromium) or Ni (nickel). Alternatively, it is formed from a material such as resin black in which carbon or Ti (titanium) is dispersed in a photoresist. Further, the light-shielding peripheral partition 53 or the light-shielding layer 23 may be formed on the liquid crystal device substrate 1. With such a configuration, the bonding accuracy between the liquid crystal device substrate 1 and the counter substrate 2 can be neglected, and there is an advantage that the transmittance of the liquid crystal device does not vary.

A data line drive circuit 101 and mounting terminals 102 for inputting signals from the outside are provided along the lower side of the screen display area in the area outside the seal material 52. The scanning line driving circuits 104 are provided on both sides of the screen display area along two sides. Here, when the driving delay of the scanning line 31 does not cause a problem, the scanning line driving circuit 104 may be formed only on one side with respect to the scanning line 31, or the data driving circuit 101 may be formed above and below the screen display area. It may be provided on both sides along two sides. At this time, for example, an odd-numbered column data line is electrically connected to one data line driving circuit 101, and an even-numbered column data line is electrically connected to the other data line driving circuit 101. May be driven in a comb shape. Further, a plurality of wirings 105 for supplying power and driving signals to the scanning line driving circuit 104 are provided on the upper side of the screen display area. At least one corner of the opposing substrate 2 is provided with a vertical conducting material 106 for establishing electric conduction between the liquid crystal device substrate 1 and the opposing substrate 2. The opposite substrate 2 having substantially the same contour as the sealing material 52 is fixed to the liquid crystal device substrate 1 by the sealing material 52.

In each of the above embodiments,
Although the case where an external control circuit for outputting a clock signal, an image signal, or the like to the data line driving circuit 101 and the scanning line driving circuit 104 is provided outside the liquid crystal device has been described, the present invention is not limited to this. Instead, the control circuit may be provided in the liquid crystal device.

In particular, with respect to the clock signal, only the clock signal may be supplied from an external control circuit, and a circuit for generating an antiphase clock signal on the liquid crystal device substrate may be provided.

The liquid crystal device 10 described above can be applied to a color liquid crystal projector or the like. In this case, three liquid crystal devices 10 are used as RGB light valves, respectively, and each panel has an RGB light valve. The light of each color separated via the dichroic mirror for color separation is respectively incident as incident light. Therefore, in each embodiment, the counter substrate 2 is not provided with a color filter. However, in the liquid crystal device 10 as well, an RGB color filter may be formed on the opposing substrate 2 together with its protective film in a predetermined region facing the pixel electrode 11 where the light-shielding layer 23 is not formed. In this way, the liquid crystal device of the present embodiment can be applied to a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector.

The switching element used in the liquid crystal device is a positive stagger type or coplanar type polysilicon TFT.
However, the present embodiment is also effective for other types of TFTs such as an inverted stagger type TFT and an amorphous silicon TFT.

Further, in the liquid crystal device, for example, the liquid crystal layer 50 is composed of a nematic liquid crystal. However, if a polymer dispersed liquid crystal in which the liquid crystal is dispersed as fine particles in a polymer is used, an alignment film and the above-described liquid crystal layer can be obtained. Since a polarizing film, a polarizing plate, and the like are not required, the advantage of higher brightness and lower power consumption of the liquid crystal device due to an increase in light use efficiency can be obtained.

The data line driving circuit 101 and the scanning line driving circuit 104 are provided on the driving LSI mounted on, for example, a TAB (tape automated bonding substrate) instead of being provided on the liquid crystal device substrate 1. The connection may be made electrically and mechanically via an anisotropic conductive film provided on the peripheral portion of the device substrate 1.

In the above-described embodiment, the configuration of the scanning line driving circuit 104 is not described in detail, but a configuration similar to that of the data line driving circuit 101 can be employed particularly for a shift register portion.

(Electronic Equipment) Next, an embodiment of an electronic equipment having the liquid crystal device 10 described in detail above will be described with reference to FIG.
This will be described with reference to FIGS.

First, FIG. 14 shows a schematic configuration of an electronic apparatus including the liquid crystal device 10 as described above.

In FIG. 14, the electronic device includes a display information output source 1000 and the above-described external display information processing circuit 100.
2, a display drive circuit 1004 including the above-described scan line drive circuit 104 and data line drive circuit 101, a liquid crystal device 10, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 is a ROM
(Read Only Memory), RAM (Random Access Me)
mory), a memory such as an optical disk device, a tuning circuit for tuning and outputting a television signal, and the like. Based on a clock signal from a clock generation circuit 1008, display information such as an image signal in a predetermined format is displayed. Output to the processing circuit 1002. Display information processing circuit 1002
The clock generation circuit 10 includes well-known various processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit.
A digital signal is sequentially generated from the input display information based on the clock signal from 08 and output to the display drive circuit 1004 together with the clock signal CLK. Display drive circuit 1
In step 004, the liquid crystal device 10 is driven by the scanning line driving circuit 104 and the data line driving circuit 101 by the above-described driving method. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. Note that the display driving circuit 1004 may be mounted on a liquid crystal device substrate included in the liquid crystal device 10, and in addition, a display information processing circuit 1002 may be mounted.

As an electronic device having such a configuration, FIG.
, A personal computer (PC) and an engineering workstation (EWS) for multimedia shown in FIG.
Examples include an electronic desk calculator, a car navigation device, a POS terminal, and a device having a touch panel.

Next, FIGS. 15 to 17 show specific examples of the electronic apparatus configured as described above.

In FIG. 15, a liquid crystal projector 1100, which is an example of electronic equipment, is a projection type liquid crystal projector, and includes a light source 1110 and a dichroic mirror 111.
3, 1114 and reflection mirrors 1115, 1116, 11
17, an entrance lens 1118, a relay lens 1119,
Exit lens 1120, liquid crystal light valve 1122,1
123, 1124 and cross dichroic prism 1
125 and a projection lens 1126. Liquid crystal light valves 1122, 1123, 1124
In this example, three liquid crystal display modules each including the liquid crystal device 10 in which the above-described drive circuit 1004 is mounted on a liquid crystal device substrate are prepared, and each is used as a liquid crystal light valve. The light source 1110 is a lamp 1 such as a metal halide.
Reflector 11 for reflecting light of 111 and lamp 1111
It consists of 12.

In the liquid crystal projector 1100 configured as described above, the dichroic mirror 1113 that reflects blue light and green light transmits the red light of the white light flux from the light source 1110, and transmits the blue light and the green light. Is reflected. The transmitted red light is reflected by the reflection mirror 1117 and is incident on the liquid crystal light valve 1122 for red light. On the other hand, among the color lights reflected by the dichroic mirror 1113, green light is reflected by the dichroic mirror 1114 that reflects green light, and is incident on the liquid crystal light valve 1123 for green light. The blue light also passes through the second dichroic mirror 1114. For blue light, the incident lens 11 is used to prevent light loss due to a long optical path.
18, a light guiding means 1121 comprising a relay lens system including a relay lens 1119 and an exit lens 1120, through which blue light is supplied to the liquid crystal light valve 1 for blue light.
It is incident on the reference numeral 124. The three color lights modulated by the respective light valves enter the cross dichroic prism 1125. This prism has four right-angle prisms bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface.
The three color lights are combined by these dielectric multilayer films to form light representing a color image. The combined light is projected on a screen 1127 by a projection lens 1126 which is a projection optical system, and an image is enlarged and displayed.

In FIG. 16, a laptop personal computer 1200, which is another example of electronic equipment, houses a liquid crystal display 1206 in which the above-described liquid crystal device 10 is provided in a top cover case, a CPU, a memory, a modem, and the like. And a main body 1204 having a keyboard 1202 incorporated therein.

Further, as shown in FIG. 17, two transparent substrates 1304a and 1304a constituting the liquid crystal device substrate 1304 are provided.
TCP that mounts an IC chip 1324 on a polyimide tape 1322 on which a conductive film of metal is formed
(Tape Carrier Package) 1320 can be connected to produce, sell, and use a liquid crystal device as one component of electronic equipment.

As described above, in addition to the electronic devices described with reference to FIGS. 15 to 17, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor,
A workstation, a mobile phone, a video phone, a POS terminal, a device having a touch panel, and the like are examples of the electronic apparatus shown in FIG.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the various liquid crystal devices described above, but is also applicable to electroluminescence and plasma display devices.

As described above, according to the present embodiment, it is possible to prevent the layout area of the drive circuit from increasing while correcting so as to surely eliminate the phase difference between the clock signal and the opposite-phase clock signal. it can. Therefore, it is possible to realize an ultra-small liquid crystal device in which the peripheral driving circuit is built in the same substrate as the pixel TFT and in which the pixels are fine and high definition, and various electronic devices including the liquid crystal device.

[0111]

As described above, according to the electro-optical device driving circuit of the present invention, the clock signal phase difference correcting means is provided at least between the clock signal supply line and the data line or scanning line driving means. Since the clock signal phase difference correcting means is provided in the second embodiment, the phase difference between the clock signal and the opposite-phase clock signal can be eliminated, thereby preventing malfunction of the driving means. Further, the clock signal phase difference correcting means includes:
Rather than being provided for each stage of the shift register of the driving means, it is provided at least between the supply line of the clock signal and the driving means. A drive circuit for the device can be provided.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a plurality of pixels of a liquid crystal device according to an embodiment of the present invention.

2A is a circuit diagram showing a configuration of a clock signal phase difference correction circuit in the liquid crystal device of FIG. 1, and FIG. 2B is a diagram showing a signal waveform at each position in the circuit of FIG.

FIGS. 3A and 3B are circuit diagrams showing a configuration of a clock signal phase difference correction circuit in the liquid crystal device of FIG. 1; FIG.
FIG. 3C is a circuit diagram when a circuit is used, and FIG.

FIG. 4 is a circuit diagram for explaining the load capacitance of each signal path in the clock signal phase difference correction circuit.

FIG. 5 is a circuit diagram of a clock signal phase difference correction circuit according to a second embodiment;
FIG. 3 is a circuit diagram in a case where a buffer circuit is configured by a multi-stage inverter circuit.

6 is a circuit diagram showing a configuration of a data line driving circuit in the liquid crystal device of FIG.

7 is a timing chart showing the operation of the data line driving circuit and the sampling circuit of FIG.

FIG. 8 is a block diagram of various wirings, peripheral circuits, and the like in an example of the liquid crystal device substrate of the present invention.

FIG. 9 is a block diagram of various wirings, peripheral circuits, and the like in another example of the liquid crystal device substrate of the present invention.

FIG. 10 is a diagram illustrating an example of a pattern layout of a clock signal phase difference correction circuit of the liquid crystal device in FIG. 8;

11 is a circuit diagram showing a clock signal phase difference correction circuit configured by the pattern layout of FIG. 9;

FIG. 12 is a plan view showing the overall configuration of the liquid crystal device of FIG.

FIG. 13 is a cross-sectional view illustrating the entire configuration of the liquid crystal device of FIG.

FIG. 14 is a block diagram illustrating a schematic configuration of an embodiment of an electronic device according to the present invention.

FIG. 15 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus.

FIG. 16 is a front view illustrating a personal computer as another example of the electronic apparatus.

FIG. 17 is a perspective view illustrating a liquid crystal display device using TCP as an example of an electronic apparatus.

18A is a circuit diagram illustrating a configuration of a conventional clock signal phase difference correction circuit, and FIG. 18B is a diagram illustrating signal waveforms at respective positions in the circuit of FIG.

FIG. 19 is an equivalent circuit diagram showing a plurality of pixels of a conventional liquid crystal device.

[Explanation of symbols]

1: substrate for liquid crystal device 2: Counter substrate 10. Liquid crystal device 11 ... pixel electrode 21 ... Common electrode 23 ... Shading layer 30 ... TFT 31 ... scanning line 35 ... data line 50 ... Liquid crystal layer 52 ... Seal material 53 ... Close-up 101: Data line drive circuit 102 mounting terminals 130, 132 ... clocked inverter 201: Precharge circuit 204: precharge signal supply line 206: precharge circuit drive signal line 301 ... Sampling circuit 304: image signal line 306 ... Sampling circuit drive signal line 401 shift register 402 ... Buffer circuit 403 ... Selection circuit 500: Clock signal phase difference correction circuit 501: first buffer circuit 502 ... Bistable circuit 503: second buffer circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI G09G 3/36 G09G 3/36 H04N 5/66 H04N 5/66 B

Claims (3)

(57) [Claims] A plurality of data lines to which an image signal is supplied; a plurality of scanning lines to which a scanning signal is supplied; switching means provided corresponding to an intersection of the data line and the scanning line; What is claimed is: 1. A drive circuit for an electro-optical device, comprising: a pixel electrode connected to a switching unit; and a shift register that transfers a predetermined signal based on a clock signal and a clock signal having an opposite phase to the clock signal. Wherein the clock signal and the clock signal having the opposite phase are supplied to the driving unit via a clock signal phase difference correction unit, and the clock signal phase difference correction unit includes a pair of first buffers. A clock signal is input to one of the first buffer circuits, and the one of the first buffer circuits is connected to the first buffer circuit. A signal output from the fur circuit is input to first logic means forming the bistable circuit, and a signal output from the first logic means is output to second logic means forming the bistable circuit. While being inputted, it is inputted to one of the second buffer circuits connected to the output section of the first logic means, and the clock signal of the opposite phase is inputted to the other first buffer circuit, and The signal output from the first buffer circuit is input to the second logic means forming the bistable circuit, and the signal output from the second logic means is output to the first logic circuit forming the bistable circuit. Is input to the other second buffer circuit connected to the output section of the second logic means, and the second buffer circuit includes a plurality of inverter circuits connected in cascade. Each of the inverter circuits connected in cascade is formed larger than the connected inverter circuit of the preceding stage, and the size of the inverter circuits forming the pair of first buffer circuits and the size of the bistable circuit The inverter circuit forming the second buffer circuit is formed to be larger than the inverter circuit forming the bistable circuit, while the inverter circuit forming the second buffer circuit has the same size. Between the stabilizing circuit and the second buffer circuit, a first portion formed of a polysilicon film among wirings for transmitting the clock signal and the clock signal having the opposite phase is a wiring of the wiring for transmitting the clock signal. The line width and length are aligned with the line width and length of the wiring for transmitting the clock signal having the opposite phase. And a second portion of the wiring for transmitting the clock signal and the clock signal having the opposite phase, the second portions having different lengths are formed of an aluminum film. 2. An electro-optical device comprising a drive circuit for the electro-optical device according to claim 1. 3. An electronic apparatus comprising the electro-optical device according to claim 2.