JP2001215928A - Driving circuit for electrooptical device, electrooptical device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent differential noises caused by enable signals ENB1, ENB2 from being superposed on a picture signal line 122. SOLUTION: Two lines of inverted enable signal lines 125 to which inverted enable signals ENBinv, ENBinv are supplied are provided so that time constants of them become the same as those of enable signal lines 124 apart from two lines of the enable signal lines 124 to which enable signals ENB1, ENB2 are supplied. As a result, since differential noises due to the enable signals ENB1, ENB2 are canceled by differential noised due to the inverted enable signals ENBinv, ENBinv, the potential of a picture signal VIDi supplied to the picture signal line 122 becomes a value closed to an original value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device capable of suppressing the occurrence of display defects such as line unevenness and providing a high-quality display, and an electronic apparatus using the electro-optical device for a display unit. About.

[0002]

2. Description of the Related Art A circuit for driving a conventional electro-optical device such as a liquid crystal device supplies an image signal or a scanning signal to a data line or a scanning line provided in an image display area at a predetermined timing. , A scanning line driving circuit, a sampling circuit, and the like.

The data line driving circuit generally includes a plurality of latch circuits, sequentially shifts a pulse signal supplied at the beginning of a horizontal scanning period in accordance with a clock signal, and outputs this as a sampling signal. Similarly, the scanning line driving circuit includes a plurality of latch circuits, sequentially shifts a pulse signal supplied at the beginning of the vertical scanning period in accordance with a clock signal, and outputs the shifted signal as a scanning signal. Things. The sampling circuit includes a sampling switch provided for each data line, and samples an image signal supplied from the outside via an image signal line according to the sampling signal.
This is supplied to each data line.

Here, if the sampling signals that are to be mutually exclusive are output overlapping for some reason, the image signal that should be sampled on a certain data line is also sampled on the adjacent data line. Will be done. As a result, there arises a problem that a so-called ghost or crosstalk occurs, and the display quality is reduced.

In particular, recently, in order to cope with an increase in the frequency of the dot clock, one image signal is serial-parallel converted (phase expanded) to a plurality of m systems, and is expanded m times on the time axis. A technique has been developed in which these m image signals are simultaneously sampled in accordance with the sampling signal and supplied to m data lines. In such a technique, the sampling signals are overlapped and output for some reason. Then, ghosts, crosstalk, and the like occur in units of m data lines, and the deterioration of display quality becomes a more serious problem.

In order to solve such a problem, in recent years, a pulse width limiting circuit has been provided at the next stage of the latch circuit in the data line driving circuit, and sampling which is output successively in time is provided. To prevent the signals from overlapping each other, set the pulse width of the sampling signal to
Limiting is performed according to a control signal (enable signal) supplied via an enable signal line.

[0007]

However, in the configuration provided with such a pulse width limiting circuit, the occurrence of the above-mentioned ghost and crosstalk can be suppressed, but this time, a vertical line along the data line is required. There is a problem that line unevenness occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to suppress the occurrence of ghosts, crosstalk, and the like, and further suppress the occurrence of line unevenness to achieve high-quality display. It is an object of the present invention to provide a drive circuit for an electro-optical device, an electro-optical device, and an electronic apparatus using the electro-optical device for a display unit.

[0009]

First, before describing the means for solving the problem, the present inventor of the present invention has investigated the mechanism of occurrence of the above-mentioned line unevenness. As a result, the following points are the main causes. ,It was considered. That is, since the above-described enable signal lines and image signal lines are generally formed by patterning a thin-film metal on a substrate such as glass or semiconductor, they have some resistance. Further, since the enable signal line and the image signal line are close to each other, they are easily coupled capacitively. Therefore, since a kind of differentiating circuit is formed across both signal lines, differential noise accompanying the level transition of the enable signal is superimposed on the image signal line in addition to the image signal. As a result,
Since the differential noise is added to the original image signal to the data line, the applied voltage is further applied to each data line or when serial-parallel conversion is performed.
It is considered that the unevenness caused by the data lines is generated along the data lines and degrades the display quality because the data lines are different every m lines.

Therefore, according to a first aspect of the present invention, there is provided a drive circuit for an electro-optical device for outputting an image signal to a plurality of data lines, comprising a plurality of latch circuits, wherein each latch circuit outputs an input signal. A shift register circuit for sequentially shifting and outputting, a pulse width limiting circuit for limiting a pulse width of an output signal from the latch circuit according to an enable signal supplied to an enable signal line, and a logic level of the enable signal inverted. An inversion enable signal line that supplies an inversion enable signal, and an image signal that is provided corresponding to each of the data lines and that is supplied to an image signal line, based on a signal whose pulse width is limited by the pulse width limitation circuit. And a sampling switch for sampling and supplying the data to a corresponding data line.

According to the present invention, in the image signal line, the differential noise superimposed with the level transition of the enable signal is canceled by the differential noise with the level transition of the inverted enable signal. Only the components will be supplied. Therefore, high-quality display in which line unevenness is suppressed can be achieved.

In the present invention, it is preferable that the inversion enable signal line is disposed substantially in parallel with the enable signal line. In this configuration, the degree of capacitive coupling from the viewpoint of the image signal line is substantially equal between the enable signal line and the inverted enable signal line, so that the differential noise caused by the enable signal can be almost completely canceled.

Similarly, in the present invention, it is preferable that the inverted enable signal line has substantially the same capacity as the enable signal line. This is because even with this configuration, the differential noise caused by the enable signal can be almost completely canceled.

Similarly, in the present invention, it is preferable that the inverted enable signal line has substantially the same time constant as the enable signal line. This is because even with this configuration, the differential noise caused by the enable signal can be almost completely canceled.

On the other hand, the present invention has a configuration in which the differential noise caused by the enable signal is canceled by the differential noise caused by the inverted enable signal.
The smaller the degree of capacitive coupling to the enable signal line and the inverted enable signal line, the better. To this end, in the present invention, the enable signal line and the inverted enable signal line are provided so as to wrap around from one side of the formation region of the pulse width limiting circuit, while the image signal line is It is desirable that the pulse width limiting circuit be provided so as to extend from the other side of the formation region. According to this configuration, since the enable signal line and the inverted enable signal line are once separated from the image signal line, it is possible to reduce the degree of capacitive coupling by that much.

Further, in the present invention, it is preferable that a constant potential line having a constant potential is disposed between the enable signal line and the inversion enable signal line and the image signal line. According to this configuration, since the constant potential line functions as a kind of shield line between the enable signal line and the inversion enable signal line and the image signal line, it is possible to reduce the capacitive coupling between the two. It becomes possible. Note that, as such a constant potential line, a high-level wiring of a power supply line, a low-level wiring, a wiring connected to a common electrode, and the like can be considered.

In addition, it is desirable that a configuration is provided that includes a level shifter that expands the logical amplitude of the sampling signal by the pulse width limiting circuit and supplies it to the corresponding sampling switch. According to this configuration, the enable signal supplied to the enable signal line and the inverted enable signal supplied to the inverted enable signal line are low logic amplitude signals before the logic amplitude is expanded by the level shifter. It is possible to reduce the influence inherently.

As a specific configuration of the pulse width limiting circuit in the present invention, a NAND circuit for outputting a NAND signal of an output signal from the latch circuit and the enable signal, or the latch circuit Is assumed to be a configuration of a NOR circuit for outputting a NOR signal of a signal having a level inversion relationship with the output signal of the above and an inversion enable signal.

In the present invention, the image signal is:
The data line is expanded into a time axis and converted into m (m is an integer of 2 or more) lines, and the data lines are divided into m lines, and the m lines of data are divided into blocks. It is desirable that the switches corresponding to the lines are driven simultaneously. According to this configuration, it is possible to cope with an increase in the frequency of the dot clock without increasing the performance of a switch for sampling an image signal and the like, and it is possible to achieve a high display contrast.

On the other hand, in the present invention, the sampling switch is a complementary type, and the pulse width limiting circuit generates a non-inverted signal whose pulse width is limited by an output signal from the latch circuit and the enable signal. A first gate circuit, and a second gate circuit for generating an inverted signal whose pulse width is limited by the signal having a level inversion relationship with an output signal from the latch circuit and the inversion enable signal. It is preferable that the complementary sampling switch performs sampling based on the normal signal and the inverted signal. According to this configuration, the input impedance of the sampling switch is increased, so that the pulse width limiting circuit does not need to have a high driving capability, and the image signal is compared with the case where the sampling switch is configured using only one channel type. Can be reduced by the push-down when sampling is performed on the data line. For this reason, higher-quality display can be performed.

In such a configuration, it is desirable that the loads of the first and second gate circuits are substantially the same. This makes it possible to make the positive / negative characteristics of the complementary sampling switches more uniform.

In order to achieve the above object, an electro-optical device according to a second aspect of the present invention is characterized in that the electro-optical device is driven by a driving circuit of the electro-optical device. According to this, high-quality display without ghost or crosstalk can be performed.

According to the second aspect of the present invention, the data line includes a plurality of scanning lines, a plurality of data lines, and switching elements and pixel electrodes provided corresponding to intersections of the scanning lines and the data lines. Wherein the pixel electrodes are arranged in a matrix, while the switching elements are interposed between the pixel electrodes and the data lines, and are supplied to the scanning lines. It is desirable to have a configuration that opens and closes according to a scanning signal. According to this configuration, the ON pixel and the OFF pixel can be electrically separated by the switching element, so that the contrast and the response are good, and a high-definition display is possible.

Further, in order to achieve the above-mentioned object, the electric apparatus according to the present invention is characterized by including the above-mentioned electro-optical device, so that high-quality display without ghost or crosstalk can be achieved. Become.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

<Schematic Configuration of Electro-Optical Device> First, an electro-optical device according to a first embodiment of the present invention will be described. This electro-optical device uses a liquid crystal as an electro-optical material and performs a predetermined display by an electro-optical change. FIG. 1A is a perspective view showing a configuration of a liquid crystal panel 100 excluding an external circuit in the electro-optical device, and FIG. 1B is a sectional view taken along line AA ′ in FIG. It is sectional drawing.

As shown in these figures, in the liquid crystal panel 100, an element substrate 101 on which various elements and pixel electrodes 118 and the like are formed, and a counter substrate 102 on which a common electrode 108 and the like are formed form a spacer 103. The electrodes are bonded so that the electrode forming surfaces face each other with a certain gap maintained by the sealing material 104 including the sealing material 104, and a liquid crystal 105 of, for example, a TN (Twisted Nematic) type is sealed as an electro-optical material in this gap. ing. Here, since the element substrate 101 does not require transparency, the element substrate 101 is made of glass, a semiconductor, quartz or the like, but the opposing substrate 102 is made of glass or the like because transparency is required.
Note that the sealant 104 is formed along the periphery of the opposing substrate 102, but has a partly opened opening for enclosing the liquid crystal 105. Therefore, after the liquid crystal 105 is sealed, the opening is sealed by the sealing material 106.

Next, on the opposing surface of the element substrate 101,
In a region 140a on one outer side of the sealing material 104,
A data line driving circuit and a sampling circuit, which will be described later, are formed to drive the data lines. Further, a plurality of connection terminals 107 are formed outside this one side, and are configured to input various signals from an external circuit. Further, two scanning line driving circuits are formed in the side region 130a adjacent to the one side as described later, and the scanning lines are driven from both sides. If the delay of the scanning signal supplied to the scanning line does not matter, a configuration in which the scanning line driving circuit is formed only on one side may be employed.

On the other hand, the common electrode 108 of the opposite substrate 102
As will be described later, among the four corners of the bonding portion with the element substrate 101, the electrical connection with the connection terminal 107 formed on the element substrate 101 is achieved by the conductive material provided at two corners close to the region 140a. The continuity is achieved. Although the conductive material is provided at two locations here, it is sufficient that the common electrode 108 is electrically connected to the connection terminal 107. Therefore, it is sufficient that at least one conductive material is provided. In addition, the opposing substrate 102 has a pixel electrode 1
A colored layer (color filter) is provided in a region opposed to 18, and a light-shielding layer for preventing a decrease in contrast due to light leak and defining a non-display region is provided in a region other than the colored layer. Is provided. However, when the present invention is applied to color light modulation as in a projector described later, it is not necessary to form a coloring layer, a light shielding layer, and the like on the counter substrate 102.

Regardless of whether or not the counter substrate 102 is provided with a coloring layer, the element substrate 101 is provided with a light-shielding layer (not shown) for preventing a deterioration in element characteristics due to light leakage. On the opposing surfaces of the element substrate 101 and the opposing substrate 102, an alignment film (not shown) rubbed is provided so that the major axis direction of the molecules of the liquid crystal 105 is continuously twisted by about 90 degrees between the two substrates. On the other hand, a polarizer (not shown) corresponding to the alignment direction is provided on each back side.

<Electrical Configuration> Next, the electrical configuration of the electro-optical device according to the present embodiment will be described. FIG.
FIG. 3 is a block diagram showing this configuration. As shown in this figure, the electro-optical device includes the liquid crystal panel 100 described above,
An external circuit 200 for supplying a signal necessary for this is provided.

The external circuit 200 is further roughly divided into a timing generator 202 and an S / P (serial / parallel) conversion circuit 204. Based on the vertical scanning signal Vs, horizontal scanning signal Hs, and dot clock signal DCLK supplied from a higher-level device (not shown), the former timing generator 202 generates a clock signal, a control signal, and the like used in each unit (as necessary). (To be described later).

As shown in FIG. 6, the S / P conversion circuit 204 distributes one image signal VID, which is supplied in synchronization with the dot clock DCLK, to six systems, and applies the same to the time axis. The image signal VID is expanded by 6 times.
1 to VID6. Here, one system of image signal VID is replaced with six systems of image signals VID1 to VID.
The reason for conversion to D6 is that a sampling circuit 15 described later is used.
0, a thin film transistor (hereinafter, simply referred to as “T”) constituting the sampling switch 151.
FT ”. This is because the application time of the image signal to the source region in (1) is made longer to sufficiently secure the sampling time and the charge / discharge time.

The output stage of the S / P conversion circuit 204 is provided with an inverting / amplifying circuit (not shown) for inverting the serial-parallel-converted image signals which need to be inverted. After that, it is configured to amplify appropriately. Here, as to whether or not to invert the polarity,
In general, the method of applying an image signal to a data line is determined according to whether polarity inversion in scanning line units, polarity inversion in data line units, or polarity inversion in pixel units. Is set to one horizontal scanning period or dot clock cycle. However, in the present embodiment, for convenience of explanation, a case where the polarity is inverted in units of scanning lines will be described as an example, but the present invention is not limited to this.

The polarity inversion in the present embodiment is as follows.
The potential LCcom of the common electrode 108 (that is, the image signal V
This means that the voltage level is alternately inverted between positive polarity and negative polarity based on the amplitude center potential of ID1 to VID6. Further, the timing of supplying the six-system image signals VID1 to VID6 to the liquid crystal panel 100 is simultaneous in the present embodiment, but in the present invention, the dot clock DCL is used in the present invention.
The shift may be sequentially performed in synchronization with K.

Now, in the display area of the element substrate 101 of the liquid crystal panel 100, a plurality of scanning lines 112 are formed in parallel in the horizontal direction in FIG.
Further, a plurality of data lines 114 are formed in parallel along the vertical direction. In a portion where the scanning line 112 and the data line 114 intersect, the gate electrode of the TFT 116 which is a switching element for controlling a pixel is connected to the scanning line 112, while the source electrode of the TFT 116 is connected to the data line 114. And TF
The drain electrode of T116 is a rectangular transparent pixel electrode 11
8 is connected.

As described above, in the liquid crystal panel 100,
Since the liquid crystal 105 is sandwiched between the electrode forming surfaces of the element substrate 101 and the counter substrate 102, each pixel is constituted by the pixel electrode 118, the common electrode 108, and the liquid crystal 105 sandwiched between these two electrodes. Will be composed. Here, for convenience of explanation, if the total number of the scanning lines 112 is “m” and the total number of the data lines 114 is “6n” (where m and n are integers), the pixels are Corresponding to each intersection with the data line 114, they are arranged in a matrix of m rows × 6n columns. Also,
In addition, in a display area composed of pixels in a matrix, a storage capacitor for preventing leakage of liquid crystal capacitance is formed for each pixel, but is not shown.

On the other hand, in the non-display area of the element substrate 101,
A peripheral circuit 120 is formed. This peripheral circuit 120
Are the scanning line driving circuit 130 and the data line driving circuit 14
0, it is conceptualized as a circuit including an inspection circuit for determining the presence or absence of a defect after manufacturing in addition to the sampling circuit 150. However, since the inspection circuit is not directly related to the present invention, its description is omitted. It is omitted.

The constituent elements of the peripheral circuit 120 are composed of a combination of a TFT 116 for driving a pixel and a P-channel TFT and an N-channel TFT formed by a common manufacturing process. Reduction of manufacturing cost, uniformization of element characteristics, and the like are being attempted.

In the peripheral circuit 120, the scanning line driving circuit 130 outputs scanning signals G1, G2,..., Gm which sequentially become active levels in each horizontal scanning period during the vertical scanning period. Also, the data line driving circuit 14
0 is a sampling signal S which sequentially becomes active level
1, S2,..., Sn are output within the horizontal scanning period. The details of the scanning line driving circuit 130 and the data line driving circuit 140 will be described later.

Next, the sampling circuit 150 includes a sampling switch 151 provided for each data line 114. Here, the data lines 114 are divided into blocks every six lines, and j is counted from the left in FIG.
(J is the first, second,..., N) -th data line 1 among the six data lines 114 belonging to the block.
Sampling switch 151 connected to one end of 14
Has a configuration in which the image signal VID1 is sampled during a period in which the sampling signal Sj is active and supplied to the data line 114. The sampling switch 151 connected to one end of the data line 114 located second among the six data lines 114 also belonging to the j-th block outputs the image signal VID2.
Is sampled during a period in which the sampling signal Sj is active, and is supplied to the data line 114. Hereinafter, similarly, among the six data lines 114 belonging to the j-th block, each of the sampling switches 151 connected to one end of the third, fourth, fifth, and sixth data lines 114 respectively receives image signals. VI
D3, VID4, VID5, and VID6 are sampled during a period in which the sampling signal Sj is active and supplied to the corresponding data line 114.

Since the TFT constituting the sampling switch 151 is of an N-channel type in this embodiment, it becomes an active level when the sampling signals S1, S2,... The sampling switch 151 is closed. The TFT constituting the sampling switch 151 may be a P-channel type or a complementary type combining both channels as in a third embodiment described later.

In addition, in the non-display area of the element substrate 101, the image signals VID1 to VID6 are
In order to reduce the load at the time of sampling, a precharge circuit for precharging each data line 114 to a predetermined potential at a timing prior to the sampling may be formed. It is omitted.

In FIG. 2 and FIG. 3, which will be described later, only one scanning line driving circuit 130 is provided only at one end of the scanning line 112. However, this is for the purpose of describing the electrical configuration. This is a measure for convenience. Actually, as shown in FIG. 1 and FIG. 8 to be described later, two are arranged at both ends of the scanning line 112. In addition, the data line driving circuit 140
5 and FIG. 5 described later, it is located above the display area, but this is also a measure for the convenience of explaining the electrical configuration, and in fact, FIG. As shown in FIG. 8, it is located below the display area.

<Structure of Data Line Driving Circuit> Next, for convenience of description, the data line driving circuit 140 will be described. FIG.
3 is a block diagram illustrating a configuration of a data line driving circuit 140. FIG. In this figure, a clock signal CLX, its inverted clock signal CLXinv, a transfer start pulse DX, an enable signal ENB1, and its inverted enable signal ENB1in.
v, the enable signal ENB2, and its inverted enable signal ENB2inv are all output by the timing generator 202 in FIG.
It is supplied in synchronization with VID6.

Now, the data line drive circuit 140 has one more stage (n +) than the total number “n” of blocks of the data line 114.
1) A shift register 1440 including a latch circuit 1450 connected in stages is provided. In this figure, it is assumed that “n” is an odd number.

Here, of the shift register 1440,
The odd-numbered latch circuit 1450 has the following configuration. That is, the odd-numbered stage latch circuit 1450
First, a clocked inverter 1452 that inverts the input level at the rise of the clock signal CLX (fall of the inverted clock signal CLXinv), and the second
Third, an inverter 1454 that inverts the output level of the clocked inverter 1452, and third, inverts the output level of the inverter 1454 at the rising edge of the inverted clock signal CLXinv (falling edge of the clock signal CLX), And a clocked inverter 1456 that feeds back. For this reason,
When the inverted clock signal CLXinv rises in the odd-numbered stage latch circuit 1450, the output of the inverter 1454 is taken into the clocked inverter 1456 and is inverted and fed back to the input of the inverter 1454. The signal captured by the clock inverter 1452 at the rising edge of the signal CLX is the clock signal CLX (the inverted clock signal CLX).
inv) for one cycle.

On the other hand, in the latch circuit 1450 of the even-numbered stage of the shift register 1440, the correspondence relationship between the clock signal CLY and the inverted clock signal CLYinv is interchanged with that of the odd-numbered stage. Therefore, when the clock signal CLX rises in the even-numbered-stage latch circuit 1450, the output of the inverter 1454 is taken into the clocked inverter 1456 and is inverted and fed back to the input of the inverter 1454. The signal captured by the clock inverter 1452 at the rising edge of the inverted clock signal CLXinv is held for one cycle of the clock signal CLX, as in the case of the even-numbered stage.

Therefore, in the shift register 1440, the first-stage latch circuit 1450 captures and outputs the transfer start pulse DX at the rising edge of the clock signal CLX, and outputs this output signal to the second-stage latch circuit. 145
0 is fetched and output at the next falling edge of the clock signal CLX (the inverted clock signal CLXinv rises), and the same operation is performed by the third to n-th latch circuits 1450 by the clock signal CLX. It is executed every time the level of (inverted clock signal CLXinv) changes.

Therefore, when a transfer start pulse DX having a width corresponding to one cycle of the clock signal CLX is input to the shift register 1440 at the beginning of the horizontal scanning period,
As shown in FIG. 6, signals S1 ′, S2 ′,..., Sn ′ output from the latch circuits of the respective stages in the shift register 1440 correspond to the clock signal CLX (inverted clock signal CLXinv) in response to the transfer start pulse DX. ) Is sequentially delayed by a half cycle.

Subsequently, a pulse width limiting circuit 1460 is provided at the next stage of the shift register 1440. The pulse width limiting circuit 1460 includes a NAND circuit 146 corresponding to the first to n-th latch circuits 1450.
2 is comprised. Among them, the NAND circuit 1462 corresponding to the odd-numbered stage latch circuit 1450 is connected to the output signal of the latch circuit 1450 and the enable signal line 12.
The NAND circuit 1462 corresponding to the latch circuit 1450 of the even-numbered stage outputs a NAND signal with the enable signal ENB1 supplied through
It outputs a NAND signal of the output signal of the latch circuit 1450 and the enable signal ENB2 supplied via the enable signal line 124.

The inversion enable signal line 125 has
Inversion enable signals ENB1inv and ENB2inv obtained by inverting the polarities of the enable signals ENB1 and ENB2 are supplied. However, in the present embodiment, the configuration is such that the inversion enable signals ENB1inv and ENB2inv are not actively used.

Subsequently, a buffer circuit 1480 is provided next to the pulse width limiting circuit 1460. This buffer circuit 1480 is composed of inverter circuits 1482 for inverting the level of the NAND signal of the NAND circuit 1462, and the inverted signals of these inverter circuits 1482 are used as sampling signals S1, S2,. It is configured to be output as Sn.

Although the inverter circuit 1482 has one stage in FIG. 5, a plurality of stages such as three stages, five stages,... The configuration may be such that the impedance is increased stepwise.

<Scanning Line Driving Circuit> Next, details of the scanning line driving circuit 130 will be described. This scanning line driving circuit 1
The configuration of 30 is basically the same as the configuration of the data line driving circuit 140, except that the output signal drawing direction and the input signal are different as shown in FIG. That is, the scanning line driving circuit 130 is
Are rotated by 90 degrees. As shown in FIG. 3, the transfer start pulse DY supplied at the beginning of the vertical scanning period is replaced with the transfer start pulse DY supplied at the beginning of the horizontal scanning period. And the clock signal C
Instead of LX and its inverted clock signal CLXinv, a clock signal CLY having a period corresponding to two horizontal scanning periods and its inverted clock signal CLYinv are input.

However, in the scanning line driving circuit 130, the next stage of the shift register 1350 is different from the data line driving circuit 140 as follows. That is, in the data line driving circuit 140, the NAND circuit 1462 obtains the NAND signal of the signal output from each latch circuit 1450 of the shift register 1440 and the enable signal, and inverts this signal by the inverter 1468 to invert the sampling signal S.
1, S2,..., Sn, the scanning line drive circuit 130 outputs the NAND signal of the signals output from the adjacent latch circuits 1350 to N
It is obtained by an AND circuit 1362, and this is
68 and output as scanning signals G1, G2,..., Gm. Therefore, signals corresponding to the enable signals ENB1 and ENB2 in the data line drive circuit 140 are not input to the scan line drive circuit 130.

Now, in such a configuration, the signals G1 ', G2',..., Gm 'output from each latch circuit 1350 of the shift register 1340 are the signals S1', S2 ',. , Sn, the transfer start pulse DY supplied at the beginning of the vertical scanning period is sequentially delayed by a half cycle of the clock signal CLY (inverted clock signal CLYinv), as shown in FIG. It will be. Therefore, NAND
The active period of the scanning signals G1, G2,..., Gm output by each set of the circuit 1462 and the inverter circuit 1468 is, as shown in FIG.
Are sequentially shifted and output by a half cycle. Therefore, a half cycle of the clock signal CLY becomes one horizontal scanning period, and the scanning lines 112 are sequentially selected one by one.

In FIG. 4 for explaining the operation of the scanning line driving circuit 130 and FIG. 6 for explaining the operation of the data line driving circuit 140, the scale of the time axis is actually the latter. Should be noted that it is much more detailed than the former. That is, the scanning signals G1, G2,.
In a period in which Gm is an active period, that is, in one horizontal scanning period, the sampling signals S1 and S1 in FIG.
2,..., Sn are in an active period in order.

<Outline of Wiring on Element Substrate>
Actual wiring on the element substrate 101, particularly, wiring near the data line driving circuit 140 and the sampling circuit 150 will be described. FIG. 8 is a plan view schematically showing the wiring.

In this figure, VssY and VssX
Is the lower potential (ground potential) of the power supply in the scanning line driving circuit 130 and the data line driving circuit 140, respectively. VddY and VddX are the higher potentials of the power supplies in the scanning line driving circuit 130 and the data line driving circuit 140, respectively. Among these, the signal line to which the lower potential VssY of the power supply is applied is a common line of the storage capacitor, and therefore is also provided for each pixel.

The two electrodes 109 to which the potential LCcom is applied are provided at points corresponding to corners of the sealing material 104 (see FIG. 1). Therefore, when the electrode 109 and the common electrode 108 are bonded to each other through a conductive material when they are bonded to the opposite substrate 102, the common electrode 108
Is applied to the potential LCcom. Here, the potential LCcom is constant with respect to the time axis.
om as a reference, the S / P conversion circuit 204
ID1 to VID6 are assigned to the high order side and the low order side every one horizontal scanning period, and the AC drive is performed.

The clock signal line to which the clock signal CLX (and its inverted clock signal CLXinv) is supplied is shielded in the vicinity of the shift register 1440 by a signal line to which the higher potential VddX is applied. Enable signal line 124 and inverted enable line 1
25 is also shielded between the pulse width limiting circuit 1460 and the buffer circuit 1480 by a signal line to which the higher potential VddX is applied. For this reason, the clock signal, the enable signal, and the inverted signal thereof are configured to be hardly affected by noise.

Further, a region where the clock signal line, the enable signal line 124 and the inversion enable line 125 are provided is shielded by a signal line to which the lower potential VssX is applied. Therefore, the configuration is such that the clock signal CLX and the enable signals ENB1 and ENB2 do not adversely affect the image signal line 122.

In addition, the six image signal lines 122 wrap around the pulse width limiting circuit 1460 and the buffer circuit 1480 from the left side in the figure, and finally extend in the X direction at a stage preceding the sampling circuit 150. , Clock signal line, enable signal line 124 and inverted enable line 1
Reference numeral 25 wraps around the pulse width limiting circuit 1460 from the right side and finally extends in the X direction. For this reason, the image signal line 122 is once separated from the enable signal line 124 and the inversion enable line 125, and then faces the buffer circuit 1480, so that the noise received from the enable signal ENB and the inversion enable signal is reduced. Care is taken to minimize the effects inherently.

The four enable signal lines 124 and the inversion enable lines 125 are formed by patterning the same thin metal layer with substantially the same width. As shown in FIG. 8, these four are alternately formed at equal intervals, and are disposed substantially parallel to and substantially the same length from the terminal 107. Therefore, the resistances of the four enable signal lines 124 and the inversion enable lines 125 are substantially the same, and the capacitances thereof are also the same. Therefore, the time constants thereof are substantially the same.

However, strictly speaking, in this embodiment, the enable signal line 124 is connected to the pulse width limiting circuit 146.
0 is connected to the input terminal of a NAND circuit 1462,
The inversion enable signal line 125 has a configuration in which nothing is connected. Therefore, the capacitance of the enable signal line 124 and the capacitance of the inversion enable line 125 are different from each other. Further, in the present embodiment, the enable signal ENB1 is supplied to the input terminal of the NAND circuit 1462 by one more than the enable signal ENB2 because “n” indicating the total number of blocks is an odd number. Has become. Therefore, the capacity of the enable signal line 124 to which the enable signal ENB1 is supplied and the enable signal E
The capacitance of the enable signal line 124 to which NB2 is supplied also differs from each other.

Therefore, actually, enable signal line 1
In order to make the four time constants of the signal line 24 and the inversion enable line 125 substantially the same, the width, length, material, interval, and the like of the signal line are designed in consideration of these points, and the dummy gate circuit is used. It is necessary to take measures such as inserting Further, a configuration in which the total number “n” of blocks is an even number can be said to be an effective measure as long as the time constants of the two enable signal lines 124 are the same.

<Operation of Electro-Optical Device> Next, the operation of the electro-optical device according to the above configuration will be described.

First, a transfer start pulse DY is supplied to the scanning line driving circuit 130 at the beginning of the vertical scanning period. The transfer start pulse DY is sequentially shifted by the clock signal CLY (and its inverted clock signal CLYinv), and as a result, as shown in FIG. 4, the scanning signals G1, G2,. …,
Gm is output to the corresponding scanning line 112.

On the other hand, the one-system image signal VID input to the external circuit 200 is
As shown in FIG. 6, the image signals are distributed to the image signals VID1 to VID6 and are expanded six times with respect to the time axis. As shown in the figure, the data line drive circuit 140 is supplied with a transfer start pulse DX at the beginning of the horizontal scanning period. The transfer start pulse DX is output by the shift register 1440 as signals S1 ′, S2 ′,..., Sn ′ sequentially shifted each time the level of the clock signal CLX (and its inverted clock signal CLXinv) changes. Then, the signals S1 ′, S2 ′,.
Sn ′ is limited to a period SMPa during which the enable signals ENB1 and ENB2 are at the active level, and as shown in FIG. 6, the sampling signals S1, S2,.
.., Sn are sequentially output.

Here, when the sampling signal S1 goes to the active level during the period in which the scanning signal G1 is active, that is, in the first horizontal scanning period, the six data lines 114 belonging to the first block from the left are connected to the six data lines 114. ,
Each of the image signals VID1 to VID6 is sampled. Then, these image signals VID1 to VID6
Are the TFTs 11 of pixels intersecting the first scanning line 112 and the six data lines 114 counted from the top in FIG.
6 will be written respectively. After this,
When the sampling signal S2 becomes active level, the six data lines 114 belonging to the second block
The image signals VID1 to VID6 are sampled, and these image signals VID1 to VID6 are
The data is written by the TFTs 116 of the pixels intersecting with the sixth scanning line 112 and the six data lines 114, respectively.

Similarly, the sampling signals S3,
When S4,..., And Sn sequentially become active levels, 6 belonging to the third, fourth,.
Image signals VID1 to VI
D6 is sampled, and these image signals VID1 to
The VID 6 is written by the first scanning line 112 and the TFT 116 of the pixel intersecting the six data lines 114, respectively. Thus, writing to all the pixels in the first row is completed.

Subsequently, during the period when the scanning signal G2 is active, that is, during the second horizontal scanning period,
Similarly, writing is performed on all the pixels in the second row, and similarly, scanning signals G3, G4,.
Gm becomes active, and the third line, the fourth line,
Writing is performed on the pixels in the row. Thus, writing is completed for all of the pixels in the first to m-th rows.

Here, when an image signal is written to a pixel, light passing between the pixel electrode 118 and the common electrode 108 has a twist of liquid crystal molecules if the voltage difference applied to both electrodes is zero. The liquid crystal molecules tilt in the direction of the electric field according to the magnitude of the voltage difference while rotating about 90 degrees along.
Optical rotation disappears. For this reason, if the liquid crystal panel 100 is, for example, a transmission type, polarizers whose polarization axes are orthogonal (parallel) to each other are arranged on the incident side and the rear side, respectively, so that the voltage difference applied to both electrodes is zero. In this case, light is transmitted (blocked), while light is blocked (transmitted) in accordance with the voltage difference applied to both electrodes. Therefore, by controlling the voltage to be written for each pixel by the image signal,
A predetermined display is possible.

In such driving, the data line 114 is set to 1
Compared with the method of driving each unit, the time for sampling the image signal by each sampling switch 151 is six times, so that the charging and discharging time in each pixel is sufficiently ensured. Therefore, high contrast can be achieved. Furthermore, since the number of stages of the latch circuit 1450 and the frequency of the clock signal CLX and its inverted clock signal CLXinv in the data line driving circuit 140 are each reduced to 1/6, the power consumption is reduced along with the reduction in the number of stages. Will also be planned.

Further, the sampling signals S1, S2,
.., During the active period of Sn, the enable signal ENB
1. Since the period is limited to SMPa, which is the active level of ENB2, overlap between adjacent sampling signals is prevented in advance. For this reason, it is prevented that the image signals VID1 to VID6 to be sampled on the six data lines 114 belonging to a certain block are simultaneously sampled on the six data lines 114 belonging to the block adjacent thereto. As a result of suppressing so-called ghost, high-quality display can be performed.

By the way, as shown in FIG. 8, the enable signal line 124 is arranged so as to be opposed to the six image signal lines 122 in the X direction with the buffer circuit 1480 interposed therebetween. Therefore, the image signal line 122 and the enable signal line 124 are capacitively coupled to each other, although a signal line to which the lower potential VssX is supplied is provided therebetween. Here, in the conventional configuration in which only the enable signal line 124 is provided, the enable signals ENB1,
Differential noise accompanying the level transition of ENB2 is
As described above, the information is superimposed on ID1 to VID6, which is considered to be a factor that degrades the display quality.

On the other hand, in the present embodiment, two inverted enable signal lines 125 are provided separately from the two enable signal lines 124. In this configuration, one image signal line 122 is capacitively coupled to the enable signal line 124 and the inverted enable signal line 125 as shown in FIG.
In FIG. 7A, VIDi is the image signal VI.
In order to generalize and describe D1 to VID6, they show image signals supplied to one image signal line 122 (i is 1, 2,..., 6).

Here, in this embodiment, the signals supplied to the two inversion enable signal lines 125 are the inversion enable signals ENB1inv and ENB2inv obtained by inverting the enable signals ENB1 and ENB2, respectively. As described above, the inversion enable signal line 125 is configured to have substantially the same time constant as the enable signal line 124.

For this reason, as shown in FIG.
Differential noise a due to the enable signal ENB1, and
Differential noises b due to the inverted enable signal ENB1inv cancel each other, and similarly, the enable signal ENB1
The differential noise c due to B2 and the differential noise d due to the inversion enable signal ENB2inv also cancel each other. Therefore, according to the present embodiment, the noise is not superimposed on the image signal VIDi supplied to an arbitrary image signal line 122, and the level of the original image signal is maintained. Is prevented.

<Second Embodiment> In the first embodiment described above, the logic signal from the data line drive circuit 140 is directly supplied to the sampling circuit 150. However, in order to drive the liquid crystal 105, In practice, a relatively high voltage of about 20 volts is required as an instantaneous value. When such a high voltage is directly input to the liquid crystal panel 100, the amplitude of the differential noise increases. In this case, the enable signal line 124 and the inverted enable signal line 1
In 25, if there is any difference in the degree of capacitive coupling to the image signal line 122, the differential noise will not be canceled out and will likely remain.

In order to solve such a problem, a level shifter for converting a logic amplitude is provided in the data line driving circuit 140, and a low voltage is applied to the liquid crystal panel 100.
It is considered that a configuration in which signal processing is performed while the noise amplitude is kept small as a configuration for inputting the signal to the.

More specifically, like a data line drive circuit 142 shown in FIG. 9, a level shifter 1472 for converting a low-amplitude logic signal into a high-amplitude logic signal is provided between a NAND circuit 1462 and an inverter circuit 1482. Interpolating,
It is considered that a configuration in which n level shifter groups 1470 are provided is desirable. It should be noted that such a level shifter is also used in the NAND
It is preferable that a configuration be provided between the circuit 1362 and the inverter circuit 1382.

<Third Embodiment> In the first and second embodiments, the inversion enable signal line 12
5, the inversion enable signal ENB1inv, EN
The configuration does not actively use B2inv, and it can be said that this configuration is a redundant configuration.

Therefore, the inversion enable signal ENB1in
A third embodiment in which v and ENB2inv are actively used and the sampling circuit 150 is improved will be described. FIG. 10 is a block diagram showing a configuration of the data line driving circuit 144 according to the third embodiment.

In this figure, sampling circuit 150
Is a complementary type combining a P-channel type TFT and an N-channel type TFT. Therefore, as a sampling signal to the switch 151,
It is necessary to supply two signals having mutually exclusive levels. Among them, one of the signals N1, N2,..., Nn is the sampling signal S in the first embodiment.
1, S2,..., Sn, but the other signal P1,
P2,..., Pn are configured to be output as follows.

That is, in the odd-numbered stage latch circuit 1450, the clocked inverter 1452 (1456)
, And a NOR signal of the inverted enable signal ENB1inv and the latch circuit 14 of the even-numbered stage
50, the clocked inverter 1452 (14
56) and the inverted enable signal ENB2inv
, A NOR circuit 1461 for outputting a NOR signal, and inverting the NOR signal by an inverter circuit 1481 to output the other signals P1, P2,.
It is configured to output as n. Here, since the output signal of clocked inverter 1452 (1456) is a signal before being inverted by inverter 1454,
A signal P1 ′ output from the latch circuit 1450 of each stage,
, Pn 'are signals N1', N2 ', ..., N
n ′ has a level-inverted relationship.

The inverter circuits 1491 and 1492
Are the signals P1, P2,..., Pn and the signals N1, N2,.
Nn and the output terminal of the NAND circuit 1461 so that the delay and the load with respect to Nn are equal to each other.
It is interposed between the output terminals 62.

In such a configuration, signals P 1 ′, P 2 ′,.
n ′ is an inverted enable signal ENB1inv, ENB2inv
Is at the L level during the period SMPa, which is, as shown in FIG. 11, one sampling signal P1,
, Pn are sequentially output. The signal N output from the latch circuit 1450 of each stage
, Nn 'are the enable signals ENB.
1, is limited to the period SMPa in which the ENB2 is at the H level, and this is sequentially output as the other sampling signals N1, N2,..., Nn as shown in FIG.

According to the data line driving circuit 144 according to the third embodiment, when the image signals VID1 to VID6 are sampled on the data line 114, the threshold voltages of the TFTs are the same and complementary. As a result of being canceled by the sampling switch 151, so-called push-down in AC driving is reduced, and higher quality display is possible.

Further, the inversion enable signal line 125
Since the signal is supplied to the input terminal of the NOR circuit 1461 of the pulse width limiting circuit 1460, the design for making the capacitance substantially equal to that of the enable signal line 124 becomes easier.

<Relationship Between Number of Conversions and Number of Data Lines Constituting One Block> In the above-described embodiment, six of the data lines 115 are regarded as one block, while six of the data lines 114 belonging to the same block. For the book, the image signals VID1 to VID6 converted into six systems are simultaneously sampled, and the application of the image signals VID1 to VID6 is sequentially performed for each block. (That is, the number of data lines constituting one block) is not limited to “6”.

For example, if the response speed of the sampling switch 151 in the sampling circuit 150 is sufficiently high, the image signal is transmitted serially to one image signal line without converting it into parallel, The sampling may be performed sequentially. Also,
The number of conversions and the number of data lines to be applied simultaneously are "3",
As for "12", "24", etc., three-system conversion, twelve-system conversion,
It is also possible to adopt a configuration in which image signals supplied in parallel by 24 system conversion or the like are simultaneously supplied.

The number of conversions and the number of data lines to be applied at the same time are multiples of 3 in view of the fact that a color image signal is composed of signals for three primary colors, which simplifies control and circuits. It is preferable in doing. However, there are cases where only grayscale display from white to black is performed,
When applied to a light valve of a plate-type projector, it is not necessary to make the number of conversions and the number of data lines applied simultaneously a multiple of three.

Now, when the number of conversions and the number of data lines to be applied simultaneously are, for example, "12", the wiring on the element substrate 101, in particular, the twelve image signal lines 122 should be as shown in FIG. good. That is,
Odd-numbered image signals VID1, VID3,..., VID1
1 is supplied to the terminal 10
7, the image signal lines 122 to which the even-numbered image signals VID2, VID4,..., VID12 are supplied from the right side in FIG. What is necessary is just to extend in the X direction like the opposing comb teeth. In such a wiring, the image signal line 122 to which an odd-numbered image signal is supplied goes around from the same side as the enable signal line 124 and the inversion enable line 125. It is slightly disadvantageous in comparison. However, in the wiring shown in FIG. 12, the clock signal line and the enable signal line 124
And the inversion enable line 125 are connected to the lower potential V
The point shielded by ssX is common to the wiring in FIG. Therefore, even in the wiring shown in FIG. 12, the influence of noise on the image signal line 122 from the clock signal CLX and the enable signal ENB is considered to be small.

<Others> In the above-described embodiment, the scanning line 112 is selected from the top to the bottom, and the block is selected from the left to the right. However, the selection is performed in the opposite direction. The configuration may be such that one of the directions can be selected according to the application.

In the above-described embodiment, in the data line driving circuit 140, the NAND signal of the output signal of the latch circuit 1450 and the enable signal ENB1 or ENB2 is obtained by the NAND circuit 1462, which is inverted by the inverter circuit 1482. And the sampling signal S
, Sn are output, but the present invention is not limited to this, and any equivalent signal may be obtained as a result. For example, in the third embodiment, the signals P1 ′,
, Pn 'and the inversion enable signal ENB1inv
Or the NOR signal with ENB2inv is set to NO
The signals P1, P2,..., Pn obtained by the R circuit 1461 and inverted by the inverter circuit 1481, respectively.
May be supplied as a sampling signal of a switch composed of a P-channel TFT.

In addition, in the embodiment described above, the TFT 116 and the like are formed on the element substrate 101, but the present invention is not limited to this. For example, the element substrate 101 is a semiconductor substrate, and the TFT 1
Instead of 16, a complementary transistor may be formed. Further, by applying SOI (Silicon On Insulator) technology, a silicon single crystal film is formed on an insulating substrate such as sapphire, and various elements are formed therein to form an element substrate 101.
It is good. However, when the element substrate 101 does not have transparency, it is necessary to use the liquid crystal panel 100 as a reflective type by forming the pixel electrode 118 with aluminum or separately forming a reflective layer.

Further, in the above-described embodiment, a TN type liquid crystal is used, but a BTN (Bi-stable Twisted Nema
tic) type, ferroelectric type and other bistable types having memory properties, polymer dispersed types, and dyes having anisotropy in visible light absorption in the major axis direction and minor axis direction (guests) ) Is dissolved in a liquid crystal (host) having a fixed molecular arrangement, and a guest-host type liquid crystal in which dye molecules are arranged in parallel with the liquid crystal molecules may be used.

The liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned horizontally with respect to both substrates when voltage is applied. It may be configured,
When a voltage is not applied, the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates, while when a voltage is applied, the liquid crystal molecules are arranged in a direction perpendicular to both substrates. good. Further, instead of arranging the common electrode 108 on the opposing substrate 102, the pixel electrode and the opposing electrode may be arranged on the element substrate 101 in a comb-tooth shape at intervals. In this configuration, the liquid crystal molecules are horizontally aligned, and the orientation direction of the liquid crystal molecules changes according to the horizontal electric field between the electrodes.
As described above, as long as the liquid crystal and the alignment method are compatible with the driving method of the present invention, various types can be used.

In addition, as an electro-optical device, in addition to a liquid crystal device, electroluminescence (EL), a digital micromirror device (DMD), plasma light emission or fluorescence by electron emission are used, and the electro-optical effect is obtained. The present invention is applicable to various electro-optical devices that perform display. In this case, the electro-optical material is an EL, a mirror device, a gas, a phosphor, or the like. When EL is used as the electro-optical material, the EL substrate 101
Is interposed between the pixel electrode 118 and the counter electrode of the transparent conductive film, so that the counter substrate 102 becomes unnecessary. As described above, the present invention is applicable to all the driving circuits of the electro-optical device having a configuration similar to the above-described configuration.

<Electronic Equipment> Next, some examples in which the above-described electro-optical device is used in electronic equipment will be described.

<Part 1: Projector> First, a projector using the above-described liquid crystal panel 100 as a light valve will be described. FIG. 13 is a plan view showing the configuration of this projector. As shown in this figure, inside the projector 2100, a lamp unit 2102 including a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 2102 is separated into three primary colors of RGB by three mirrors 2106 and two dichroic mirrors 2108 disposed inside, and the light valve 100 corresponding to each primary color is separated.
R, 100G and 100B respectively. Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal panel 100 according to the above-described embodiment, and R, G, and B supplied from an external circuit (not shown) for inputting image signals. , Respectively. In addition, since the light of B color has a longer optical path than other R and G colors, a relay lens system 2121 including an entrance lens 2122, a relay lens 2123, and an exit lens 2124 is used to prevent the loss.
Is guided through.

Now, the light valves 100R, 100G,
The lights modulated by 100B respectively enter dichroic prism 2112 from three directions. And
In the dichroic prism 2112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, after the images of each color are synthesized, a color image is projected on the screen 2120 by the projection lens 2114.

Since light corresponding to the primary colors of R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter as described above. The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmitted images of the light valve 100G are projected as they are.
Is required to be horizontally inverted with respect to the display image by the light valve 100G.

<Part 2: Mobile Computer> Next, an example in which the above-described liquid crystal panel 100 is applied to a mobile personal computer will be described. FIG.
FIG. 4 is a perspective view showing the configuration of the personal computer. In the figure, a computer 2200 includes a main body 2204 having a keyboard 2202 and a liquid crystal panel 100 used as a display. Note that a backlight for improving visibility is provided on the back surface of the liquid crystal panel 100.

<Part 3: Mobile Phone> Further, an example in which the above-described liquid crystal panel 100 is applied to a display unit of a mobile phone will be described. FIG. 15 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 2300 includes a plurality of operation buttons 2302, an earpiece 2304, a mouthpiece 2
The liquid crystal panel 100 described above is provided together with the liquid crystal panel 100 described above. Note that a backlight for improving visibility is also provided on the back surface of the liquid crystal panel 100.

Note that the electronic devices are shown in FIGS.
In addition to those described with reference to, a liquid crystal television, a viewfinder type / monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a PO
Examples include an S terminal, a digital still camera, a device equipped with a touch panel, and the like. It goes without saying that the electro-optical device according to the embodiment and the applied form can be applied to these various electronic devices.

[0109]

As described above, according to the present invention, in the image signal line, the differential noise superimposed on the level of the enable signal with the inversion is canceled by the differential noise with the level inversion of the inverted enable signal. So
As a result of supplying only the components of the original image signal, high-quality display with reduced line unevenness can be achieved.

[Brief description of the drawings]

FIG. 1A is a perspective view illustrating a configuration of an electro-optical device according to a first embodiment of the invention, and FIG.
It is sectional drawing of the AA 'line of (a).

FIG. 2 is a block diagram illustrating an electrical configuration of the electro-optical device.

FIG. 3 is a block diagram showing a configuration of a scanning line driving circuit in the same electro-optical device.

FIG. 4 is a timing chart for explaining the operation of the scanning line driving circuit.

FIG. 5 is a block diagram showing a configuration of a data line driving circuit in the same electro-optical device.

FIG. 6 is a timing chart for explaining the operation of the data line drive circuit.

FIG. 7 is a timing chart for explaining an operation for canceling differential noise in the electro-optical device.

FIG. 8 is a plan view showing wiring of an element substrate in the same electro-optical device.

FIG. 9 is a block diagram illustrating a configuration of a data line driving circuit of an electro-optical device according to a second embodiment of the invention.

FIG. 10 is a block diagram illustrating a configuration of a data line driving circuit of an electro-optical device according to a third embodiment of the invention.

FIG. 11 is a timing chart for explaining the operation of the electro-optical device.

FIG. 12 is a plan view illustrating wiring of an element substrate when the number of serial-parallel conversion phases is large in the electro-optical device according to the embodiment.

FIG. 13 is a plan view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device according to the embodiment is applied.

FIG. 14 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 15 is a perspective view showing a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device is applied.

[Explanation of symbols]

 Reference Signs List 100 liquid crystal panel 101 element substrate 102 counter substrate 105 liquid crystal 108 counter substrate 112 scanning line 114 data line 116 TFT 118 pixel electrode 120 peripheral circuit 122 image signal line 124 enable signal line 125 Inversion enable signal line 130 scanning line driving circuit 140 data line driving circuit 150 sampling circuit 151 sampling switch 1440 shift register 1450 latch circuit 1460 pulse width limiting circuit 1461 NOR circuit 1462 NAND circuit 1472 level shifter 1480 ... Buffer circuit 2100 ... Projector 2200 ... Personal computer 2300 ... Mobile phone

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H093 NA16 NA42 NA53 NC12 NC21 NC22 NC34 ND05 ND09 ND15 ND35 ND36 ND40 5C006 AF42 BB16 BC03 BC12 BF03 BF04 BF11 BF25 BF26 BF27 BF46 EC01 EC08 EC11 FA22 FA31 5C05 DD10 FF11 JJ02 JJ03 JJ04 JJ06 KK07

Claims (14)

[Claims] 1. A drive circuit for an electro-optical device for outputting an image signal to a plurality of data lines, comprising: a plurality of latch circuits; a shift register circuit for sequentially shifting and outputting an input signal by each of the latch circuits; A pulse width limiting circuit that limits a pulse width of an output signal from the latch circuit according to an enable signal supplied to an enable signal line; and an inversion enable signal line that supplies an inversion enable signal obtained by inverting a logic level of the enable signal. An image signal provided to each of the data lines and supplied to an image signal line is sampled based on a signal of which pulse width is limited by the pulse width limiting circuit, and supplied to a corresponding data line; A driving circuit for an electro-optical device, comprising: a sampling switch. 2. The drive circuit according to claim 1, wherein the inversion enable signal line is disposed substantially in parallel with the enable signal line. 3. The driving circuit according to claim 1, wherein the inversion enable signal line has substantially the same capacity as the enable signal line. 4. The driving circuit according to claim 1, wherein the inversion enable signal line has substantially the same time constant as the enable signal line. 5. The pulse width limiting circuit according to claim 1, wherein the enable signal line and the inversion enable signal line are provided so as to extend from one side of a region where the pulse width limiting circuit is formed. The driving circuit for an electro-optical device according to claim 1, wherein the driving circuit is provided so as to extend from the other side of the formation region of the electro-optical device. 6. The constant potential line according to claim 1, wherein a constant potential line having a constant potential is provided between said enable signal line and said inverted enable signal line and said image signal line. Drive circuit for electro-optical device. 7. The electro-optical device according to claim 1, further comprising a level shifter for expanding a logical amplitude of a signal whose pulse width is limited by the pulse width limiting circuit and supplying the signal to a corresponding sampling switch. Drive circuit. 8. The NAND circuit according to claim 1, wherein said pulse width limiting circuit outputs a NAND signal of an output signal of said latch circuit and said enable signal, or an output signal of said latch circuit has a level inversion. 2. The driving circuit for an electro-optical device according to claim 1, wherein the driving circuit is a NOR circuit that outputs a NOR signal of a signal having a relationship and the inversion enable signal. 9. The image signal is expanded on a time axis to obtain m
(Where m is an integer of 2 or more). The data lines are divided into m lines, and the switches corresponding to the m divided data lines are simultaneously switched. The driving circuit according to claim 1, wherein the driving circuit is driven. 10. The sampling switch is of a complementary type, and the pulse width limiting circuit generates a non-inverted signal having a pulse width limited by an output signal from the latch circuit and the enable signal.
And a second gate circuit that generates an inverted signal whose pulse width is limited by a signal having a level inversion relationship with an output signal of the latch circuit and the inversion enable signal, 2. The driving circuit for an electro-optical device according to claim 1, wherein the complementary sampling switch performs sampling based on the forward signal and the inverted signal. 11. The load of the first and second gate circuits is substantially equal to each other.
A driving circuit for the electro-optical device according to claim 1. 12. An electro-optical device driven by the driving circuit of the electro-optical device according to claim 1. Description: 13. A plurality of scanning lines, a plurality of data lines,
An electro-optical device that includes a switching element and a pixel electrode provided corresponding to an intersection of the scanning line and the data line, and drives each of the data lines, wherein the pixel electrodes are arranged in a matrix. On the other hand, the switching element is interposed between the pixel electrode and the data line, and opens and closes according to a scanning signal supplied to the scanning line.
An electro-optical device according to claim 1. 14. An electronic apparatus comprising the electro-optical device according to claim 12.