JP3800912B2 - Electro-optical device and electronic apparatus - Google Patents

Description

ただし、上記項（数１）において、ζは定数であり、また、Ｖ_i-1,jは、（ｉ−１）番目のブロックの選択時に画像信号ＶＩＤｊ（ｊ＝１、２、３、…、ｈ）に対応するデータ線に供給された電圧である。
【０１０４】
同様に、「要因２」によって対向電極に発生する誤差電圧は、次（数２）のように示される。
【０１０５】
【数２】

ただし、上記項（数２）において、ξは定数であり、また、Ｖpreは、プリチャージ電圧である。
【０１０６】
したがって、対向電極１０８に発生する全誤差電圧は、次（数３）のように示される。
【０１０７】
【数３】

ここで、ｉ番目のブロックの選択終了直前では、一定の減衰係数ｋを乗じて、次式（数４）のように、画像信号を変数とした関数（以降、誤差関数ｆ_errと称する）で表すことができる。
【０１０８】
但し、Ｖ_{ε 0}は、ｉ−１番目のブロックの選択終了直前での全誤差電圧である。
【０１０９】
【数４】

次に、この誤差関数ｆ_errを用いて、図８に示される各ゴーストについて説明する。まず、前ゴーストについて考える。前ゴーストが発生するブロックにおいて黒窓の左側に位置する画素は総て中間調灰色である。そこで、このような中間調灰色画素に印加される電圧を、例えばプリチャージ電圧Ｖpreに等しい電圧であると考えると、直前ブロックである（ｉ−１）番目のブロックにおける電圧Ｖ_i-1,jは、Ｖpreとなり、ｉ番目のブロックにおける電圧Ｖ_i,jは、Ｖpreであるか、それ以上となる。このため、例えば正極側の書込において、上式（数４）で示される誤差関数ｆ_errの第２項および第３項は、ともに非負となる。そして、Ｖ_{i ,j}＞Ｖpreとなる画素が多くなるにつれて（すなわち黒窓がブロックに占める幅が広くなるにつれて）、第２項および第３項がともに増加し、誤差が正側に大きくなって、画素容量に印加される電圧実効値が小さくなる方向に作用する結果、明るいむらとなることが解る。この点は、図８を用いて説明した前ゴーストの様子と一致する。
【０１１０】
続いて、後ゴーストについても、黒窓がブロックに占める幅が広くなるにつれて、明るいむらとなる。ただし、誤差関数ｆ_errにおける第２項は、例えば正極側の書込において、非負であるが、黒窓の幅が狭いと第３項は負の値に転じ、狭くなるにつれて、その絶対値は、大きくなる。このため、黒窓がブロックに占める幅が狭くなるにつれて、第３項の影響が第２項よりも優勢となって、暗い表示むらとなる。この点についても、図８を用いて説明した後ゴーストの様子と一致する。
【０１１１】
そして、次ゴーストでは、誤差関数ｆ_errにおける第２項はゼロであり、第３項は、例えば正極側の書込において、正にはならない。しかも、黒窓が存在する（ｉ−１）番目のブロックにおいて黒窓が占める幅が広くなるにつれて、第３項の絶対値は大きくなって、暗い表示むらが生じることになる。
【０１１２】
このようにして、前ゴースト、後ゴーストおよび次ゴーストが発生する、と考えられる。なお、ｈ＝１の場合、言い換えれば、いわゆる点順次走査駆動の場合（シリアル／パラレル変換しない場合）でも、上記式（数４）から解るようにゴーストが発生することになる。
【０１１３】
結局、いずれにせよ、このようなゴーストが発生して、表示画像の品質が劣化してしまうといった問題があった。ここで、上述した第１実施形態にあっては、誤差関数ｆ_errにおける第３項については考慮したが、第１項、第２項については、考慮していない。また、第１実施形態の変形例で述べたように、補正信号線については、既存の配線を用いることができる。
【０１１４】
そこで以下、上記式（数４）における誤差関数ｆ_errの各項を考慮した第２〜第６実施形態について説明することとする。
【０１１５】
＜第２実施形態＞
まず、補正信号線としてプリチャージ信号線１７９を用いて、誤差関数ｆ_errの第３項の成分を打ち消す第２実施形態について説明することとする。
【０１１６】
この第２実施形態に係る電気光学装置が第１実施形態と相違する点は、図１０に示されるように素子基板１０１が若干変更されている点と、図３に示される処理回路２００から図１１に示される処理回路２０２に置換されている点とであり、他については第１実施形態と共通であるので、同一の符号を付与して、その説明を省略することとする。
【０１１７】
まず、第２実施形態における素子基板１０１にあっては、図１０に示されるように、第１実施形態における補正信号線１７３が廃されている点と、プリチャージ信号線１７９に供給される信号が、プリチャージ電圧信号・補正信号ＰＳである点との２点において、第１実施形態における素子基板（図２参照）と相違している。
【０１１８】
一方、第２実施形態における処理回路２０２にあっては、図１１に示されるように、反転回路２１６（図３参照）が廃された代わりに、新たに、補正回路２１８が設けられている点において、第１実施形態における処理回路２００と相違している。
【０１１９】
ここで、補正回路２１６は、反転加算回路２２０とスイッチＳＷ１とから構成されている。このうち、反転加算回路２２０は、Ｓ／Ｐ変換回路２１４により変換された画像信号ＶＩＤ１〜ＶＩＤ６の各電圧を加算するとともに、その加算値に適切な係数（負）を乗じて、補正信号Ｖcmp1として出力するものである。なお、反転加算回路２２０における反転の基準は、上述したように対向電極１０８に印加される電圧ＬＣcomである。
【０１２０】
また、スイッチＳＷ１は、プリチャージ制御信号ＰＧがアクティブレベルである場合には、プリチャージ電圧信号Ｖpreを選択する一方、プリチャージ制御信号ＰＧが非アクティブレベルである場合には、補正信号Ｖcmp1を選択して、それぞれプリチャージ電圧信号・補正信号ＰＳとして出力するものである。
【０１２１】
このような構成において、補正回路２１８は、１水平帰線期間ではプリチャージ電圧信号Ｖpreをプリチャージ電圧信号・補正信号ＰＳとして出力する。このため、各ブロックが選択される前の１水平帰線期間では、第１実施形態と同様に、各データ線１１４がプリチャージ電圧信号Ｖpreの電圧（Ｖgr＋またはＶgr−）にプリチャージされることとなる。
【０１２２】
一方、補正回路２１８は、各ブロックが選択される１水平有効表示期間では、各ブロックが選択される毎に、画像信号ＶＩＤ１〜ＶＩＤ６の電圧に応じて補正信号Ｖcmp1を出力することになる。ここで、選択ブロックが（ｉ−１）番目のブロックからｉ番目のブロックに移行する場合、補正信号Ｖcmp1は、（ｉ−１）番目のブロックに属する６本のデータ信号１１４に供給されていた画像信号ＶＩＤ１〜ＶＩＤ６の電圧の総和に負の係数を乗じた電圧から、ｉ番目のブロックに属する６本のデータ信号１１４に供給される画像信号ＶＩＤ１〜ＶＩＤ６の電圧の総和に負の係数を乗じた電圧まで変動することになる。そして、この電圧変動が、プリチャージ信号線１７９の寄生容量を介して対向電極１０８に供給される結果、上記式（数４）で示される誤差関数ｆ_errのうち、第３項の成分が打ち消されることとなる。
【０１２３】
したがって、この第２実施形態によれば、第１実施形態と同様に、誤差関数ｆ_errの第３項の成分に起因する表示むらを解消することが可能となる。さらに、この第２実施形態では、プリチャージ信号線１７９を補正信号線として兼用しているので、補正信号線１７３を別途有する第１実施形態と比較して、構成の簡易化を図ることも可能となる。ただし、別途、補正信号線を配設しても良いのはもちろんである。
【０１２４】
＜第２実施形態の変形例＞
上述した第２実施形態では、補正信号線をプリチャージ信号線１７９と兼用する構成としたが、このほかにも走査線１１２や、容量線１７５、プリチャージ信号線１７７についても対向電極１０８と容量的に結合するので、これを補正信号線と兼用する構成も可能である。
【０１２５】
例えば、走査線１１２を補正信号線と兼用する場合、図１２に示されるような構成とすれば良い。すなわち、第１に、反転加算回路２２０によって、画像信号線ＶＩＤ１〜ＶＩＤ６の電圧の総和を求めるとともに、適切な係数（負）を乗じた補正信号Ｖcmp1を求め、第２に、反転加算回路２３２によって、補正信号Ｖcmp1と、走査信号の非アクティブレベルＶＧoffとの電圧加算値を求めてレベル反転し、第３に、反転回路２３４によって、反転加算回路２３２の出力を再度レベル反転し、第４に、走査線駆動回路１３０において、走査線１１４の１本に対応するスイッチＳＷａによって、当該走査線１１２の走査信号Ｇｘをアクティブレベルとすべき場合にはアクティブレベルＶＧonを選択する一方、それ以外の場合には、反転回路２３４の出力信号を選択する構成とすれば良い。
【０１２６】
このような構成によれば、走査線１１２に供給される走査信号Ｇｙ（ｙは、１、２、３、…、ｍ）は、図１３に示されるように、当該水平走査線１１２が選択される１水平走査期間１Ｈにあっては、アクティブレベルＶＧonとなる一方、それ以外の期間にあっては、非アクティブレベルＶＧoffに補正信号Ｖcmp1が加算されたレベルとなって、各ブロックの選択に応じてレベル変動することになる。そして、このレベル変動が、寄生容量を介して対向電極１０８に供給される結果、上述した第２実施形態と同様に、上記式（数４）の誤差関数ｆ_errの第３項の成分が打ち消されることとなる。
【０１２７】
なお、このような構成では、非アクティブレベルＶＧoffに補正信号Ｖcmp1が加算されることになるが、この加算電圧は、図１３に示されるように、ＴＦＴ１１６のしきい値電圧ＶＧthから充分に離れ、かつ、オフマージン内に収まっている。したがって、このような加算によって、走査信号の本来の機能であるＴＦＴ１１６のオンオフ制御に支障を与えることはない。
【０１２８】
ところで、このような構成では、当該走査線１１２が選択される１水平走査期間１Ｈでは、スイッチＳＷａがアクティブレベルＶＧonを選択するので、補正信号Ｖcmp1を供給することができない。そこで、表示画面を上下に２分割して、上半分に属する走査線１１２が選択される期間では、下半分に属する走査線１１２に補正信号Ｖcmp1を加算して出力する一方、下半分に属する走査線１１２が選択される期間では、上半分に属する走査線１１２に補正信号Ｖcmp1を加算して出力する構成が望ましいと考える。
【０１２９】
なお、ここでは、走査線１１２を補正信号線と兼用する構成としたが、プリチャージ制御線１７７を補正信号線と兼用する構成も可能である。このようにプリチャージ制御線１７７を補正信号線と兼用する場合には、１水平帰線期間においてプリチャージを行うときにアクティブレベルとなり、それ以外のときに非アクティブレベルに上述した補正信号Ｖcmp1を加算したレベルを、プリチャージ制御線１７７に供給する構成とすれば良い。
【０１３０】
＜第３実施形態＞
次に、式（数４）における誤差関数ｆ_errの第２項の成分を打ち消す第３実施形態について説明する。
【０１３１】
この第２実施形態において、素子基板１０１自体は、第２実施形態と同様であるが、図１１に示される反転加算回路２２０を、図１４に示される回路に置換したものである。すなわち、この第３実施形態は、第２実施形態と同様に、補正信号線としてプリチャージ信号線１７９を用いたものである。なお、他については、第１および第２実施形態と共通であるので、同一の符号を付与して、その説明を省略することとする。
【０１３２】
さて、図１４に示される回路においては、スイッチＳＷ２、ＳＷ３、コンデンサＣ２１〜Ｃ２６、抵抗Ｒ１およびバッファ２２３からなる減算回路が備えられる。このうち、スイッチＳＷ２は、画像信号ＶＩＤ１〜ＶＩＤ６の各々に対応して設けられた６個の双投スイッチからなり、各双投スイッチにおける入力端の一方には、画像信号ＶＩＤ１〜ＶＩＤ６のうち対応する信号が供給され、入力の他端には、プリチャージ電圧信号Ｖpreが供給されている。ここで、各双投スイッチは、制御信号Ｓｇ２がＨレベルである場合に画像信号ＶＩＤ１〜ＶＩＤ６のうち対応するものを選択する一方、制御信号Ｓｇ２がＬレベルである場合にプリチャージ電圧信号Ｖpreを選択するものである。これら６個の双投スイッチの出力端には、それぞれコンデンサＣ２１〜Ｃ２６の一端が接続されている。
【０１３３】
次に、コンデンサＣ２１〜Ｃ２６の他端は、共通接続されて、この共通接続部分がバッファ２２３の入力端に接続されるとともに、抵抗Ｒ１を介して接地され、さらに単投スイッチＳＷ３の一端に接続されている。ここで、単投スイッチＳＷ３は、例えば制御信号Ｓｇ３がＨレベルの場合に閉じるものであり、その他端は接地されている。また、バッファ２２３は、その入力端に供給された電圧をバッファリングして信号Ｐａとして出力する電圧バッファである。
【０１３４】
続いて、バッファ２２３の出力端は、単投スイッチＳＷ４の一端に接続されている。この単投スイッチＳＷ４は、例えば制御信号Ｓｇ４がＨレベルの場合に閉じるものであり、その他端はバッファ２２５の入力端およびコンデンサＣ３２の一端にそれぞれ接続されている。ここで、バッファ２２５は、バッファ２２３と同様な電圧バッファであり、また、コンデンサＣ３２の他端は接地されている。したがって、バッファ２２３による出力信号Ｐａは、単投スイッチＳＷ４の開閉によってサンプリングされるとともに、コンデンサＣ３１によってホールドされて、そのホールド電圧がバッファ２２５から出力信号Ｐｂとして出力される構成となっている。
【０１３５】
そして、出力信号Ｐｂは、反転倍率回路２３５により適正な係数（負）が乗じられて補正信号Ｖcmp2として出力され、これが、図１１における補正信号Ｖcmp1に置換されて、スイッチＳＷ１に供給される構成となっている。
【０１３６】
ここで、制御信号Ｓｇ２〜Ｓｇ４は、クロック信号ＣＬＸに対して図１５に示されるようなレベル関係で変化する。まず、ブロックの選択が行われる直前では、制御信号Ｓｇ２はＬレベルであるので、単投スイッチの６個は、それぞれプリチャージ信号電圧Ｖpreを選択する。このため、コンデンサＣ２１〜Ｃ２６は、それぞれプリチャージ信号電圧Ｖpreの電圧に充電される。
【０１３７】
続いて、ブロック選択の境において、制御信号Ｓｇ２はＨレベルとなるので、単投スイッチの６個は、画像信号ＶＩＤ１〜ＶＩＤ６を選択する結果、バッファ２２３の入力端には、プリチャージ電圧信号Ｖpreと画像信号ＶＩＤ１〜ＶＩＤ６との差の総和に応じた波高の微分波形が発生する。
【０１３８】
一方、ブロック選択の境において、制御信号Ｓｇ４はＨレベルとなった後、直ちにＬレベルとなる。このため、プリチャージ電圧信号Ｖpreと画像信号ＶＩＤ１〜ＶＩＤ６との差の総和に応じた波高値がサンプル＆ホールドされて、バッファ２２５から信号Ｐｂとして出力されることとなる。そして、このサンプル＆ホールドされた信号Ｐｂは、反転倍率回路２３５により適正な係数が乗じられて、補正信号Ｖcmp2として出力される。
【０１３９】
したがって、このような構成では、ブロックが選択される毎に、プリチャージ電圧Ｖpreと該ブロックにおいて供給される画像信号ＶＩＤ１〜ＶＩＤ６との差の総和に応じた電圧が、補正信号Ｖcmp2として出力されることとなる。そして、この電圧変動が、プリチャージ信号線１７９の寄生容量を介して対向電極１０８に供給される結果、上記式（数４）の誤差関数ｆ_errの第２項の成分が打ち消されるので、第２項の成分に起因する表示むらを解消することが可能となる。
【０１４０】
なお、図１４におけるスイッチＳＷ３は、本来的には無くても構わないが、制御信号Ｓｂ２がＬレベルの期間に一瞬閉じる（図１５の制御信号Ｓｂ３参照）ことで、抵抗Ｒ１を短絡して、プリチャージ電圧ＶpreをコンデンサＣ２１〜Ｃ２６によって正確に充電するために設けられる。
【０１４１】
また、この第３実施形態では、補正信号Ｖcmp2を素子基板１０１におけるプリチャージ信号線１７９を介して対向基板１０８に供給する構成としたが、このほかにも、走査線１１２や、プリチャージ制御線１７７、容量線１７５、新規の配線を介して供給しても良いのは、第２実施形態と同様である。
【０１４２】
＜第４実施形態＞
次に、式（数４）における誤差関数ｆ_errの第２項および第３項を打ち消すための第４実施形態について説明する。
【０１４３】
この第４実施形態において、素子基板１０１自体は、第２および第３実施形態と同様であるが、図１１に示される反転加算回路２２０を、図１６に示される回路に置換したものである。すなわち、この第４実施形態も、第２および第３実施形態と同様に、補正信号線としてプリチャージ信号線１７９を用いたものである。
【０１４４】
ここで、図１６に示される回路は、反転加算回路２２８によって、図１４における信号Ｐｂと画像信号ＶＩＤ１〜ＶＩＤ６との総和を求めるとともに、この総和に適切な係数を乗じて、補正信号Ｖcmp3（＝Ｖcmp1＋Ｖcmp2）として出力する構成となっている。
【０１４５】
したがって、この第４実施形態によれば、式（数４）における誤差関数ｆ_errの第２項および第３項の成分を打ち消すことができるので、次ゴーストのほか、前ゴースト、さらには次ゴーストまでも解消することが可能となる。
【０１４６】
なお、この第４実施形態では、補正信号Ｖcmp2を素子基板１０１におけるプリチャージ信号線１７９を介して対向基板１０８に供給する構成としたが、このほかにも、走査線１１２や、プリチャージ制御線１７７、容量線１７５、新規の配線を介して供給しても良いのは、第２〜第４実施形態と同様である。
【０１４７】
＜第５実施形態＞
次に、式（数４）における誤差関数ｆ_errの第１項、第２項および第３項の全項を打ち消すための第５実施形態について説明する。
【０１４８】
この第５実施形態において、素子基板１０１自体は、第２〜第４実施形態と同様であるが、図１１に示される反転加算回路２２０を、図１７に示される回路に置換したものである。すなわち、この第５実施形態も、第２〜第４実施形態と同様に、補正信号線としてプリチャージ信号線１７９を用いたものである。
【０１４９】
ここで、図１７に示される回路は、反転加算回路２２９によって、図１４または図１６における信号Ｐｂと、画像信号ＶＩＤ１〜ＶＩＤ６と、さらに、信号Ｐｄの総和を求めるとともに、この総和に適切な係数を乗じてレベル反転して、補正信号Ｖcmp4として出力する構成となっている。
【０１５０】
このうち、信号Ｐｄは、次のような構成によって出力されるものである。すなわち、（ｉ−１）番目のブロックが選択されている場合に出力される補正信号Ｖcmp4をレベル反転する反転回路２３５と、この反転回路２３５の出力信号Ｐｃをサンプル＆ホールドして、ｉ番目のブロックが選択されている期間に出力するサンプル＆ホールド回路とによって、信号Ｐｂが出力される構成となっている。なお、このサンプル＆ホールド回路は、信号ＰｃをサンプリングするためのスイッチＳＷ５と、サンプルされた電圧をホールドするためのコンデンサＣ３２およびバッファ２２７とから構成されている。
【０１５１】
このような実施形態によれば、ｉ番目のブロックが選択される直前に対向電極１０８に残る誤差電圧Ｖ_{ε 0}たる第１項の成分についても、第２項および第３項の成分とともにに打ち消すことができるので、第４実施形態と比較して、さらに、高品位な表示が可能となる。
【０１５２】
＜第６実施形態＞
なお、式（数４）における誤差関数ｆ_errの第１項、第２項および第３項の各項の成分を打ち消す構成については、第５実施形態のように、補正信号線として用いるプリチャージ信号線１７９に、各項の成分を打ち消す補正信号Ｖcmp4を供給する構成のほか、ある項の成分を打ち消す補正信号については、アナログ信号である画像信号ＶＩＤ１〜ＶＩＤ６に重畳する一方、他の項の成分を打ち消す補正信号については、補正信号線として用いるプリチャージ信号線１７９等に供給する構成としても良い。
【０１５３】
例えば、誤差関数ｆ_errの第２項の成分を打ち消す補正信号については画像信号ＶＩＤ１〜ＶＩＤ６の各々に重畳する一方、第１項および第３項の成分を打ち消す補正信号については、補正信号線として用いるプリチャージ信号線１７９等に供給する構成としても良い。
【０１５４】
このような構成のうち、誤差関数ｆ_errの第２項の成分を打ち消す補正信号を、画像信号ＶＩＤ１〜ＶＩＤ６の各々に重畳する構成については、例えば次のようにすれば良い。すなわち、Ｓ／Ｐ変換回路２１４の次段に、図１８に示される回路を挿入し、この回路の出力である画像信号ＶＩＤ１’〜ＶＩＤ６’を、液晶パネル１００に供給する構成とすれば良い。なお、図１８に示される回路において、加算回路２４２は、画像信号ＶＩＤ１〜ＶＩＤ６の各々とプリチャージ電圧Ｖpreとの差をそれぞれ求めるとともに、この差の総和に適切な係数を乗じて補正信号を出力するものであり、また、加算回路２４４は、画像信号ＶＩＤ１〜ＶＩＤ６の各々に補正信号Ｖをそれぞれ加算するものである。
【０１５５】
一方、誤差関数ｆ_errの第１項および第３項の成分を打ち消す補正信号については、図１７において、信号Ｐｂを反転加算回路２２９に入力させない構成とすれば良い。
【０１５６】
このような第６実施形態によれば、上述した第５実施形態と同様に、ゴーストの発生を抑えた高品位な表示が可能となる。
【０１５７】
なお、本実施形態にあっては、誤差関数ｆ_errの第２項の成分を打ち消すための補正信号については画像信号ＶＩＤ１〜ＶＩＤ６の各々に重畳する一方、第１項および第３項の成分を打ち消すための補正信号については、補正信号線として用いるプリチャージ信号線１７９等に供給する構成としたが、このほかにも、種々の態様が可能である。要は、誤差関数ｆ_errのうち、ある項の成分を打ち消すための補正信号については、画像信号ＶＩＤ１〜ＶＩＤ６に重畳する一方、残りの項の一部あるいは全部の項の成分を打ち消すための補正信号については、補正信号線として用いるプリチャージ信号線１７９等に供給する構成とすれば良いのである。
【０１５８】
また、画像信号は、デジタルで供給されたものがアナログに変換されて最終的に液晶パネル１００に供給される構成が一般的である。このため、本実施形態のように、画像信号ＶＩＤ１〜ＶＩＤ６に補正信号を重畳する場合においては、デジタルの画像信号にデジタルの補正信号を加算した後、アナログ信号に変換して液晶パネル１００に供給する構成としても良い。
【０１５９】
＜その他＞
なお、上述した実施形態にあっては、６本のデータ線１１４が１ブロックにまとめられて、１ブロックに属する６本のデータ線１１４に対して、６系統に変換された画像信号ＶＩＤ１〜ＶＩＤ６を同時にサンプリングして供給する構成したが、変換数および同時に印加するデータ線数（すなわち、１ブロックを構成するデータ線数）は、「６」に限られるものではない。例えば、サンプリング回路１５０におけるサンプリングスイッチ１５１の応答速度が十分に高いのであれば、画像信号をパラレルに変換することなく１本の画像信号線にシリアル伝送して、データ線１１４毎に順次サンプリングするように構成しても良い。また、変換数および同時に印加するデータ線の数を「３」や、「１２」、「２４」等として、３本や、１２本、２４本等のデータ線に対して、３系統変換や、１２系統変換、２４系統変換等した画像信号を同時に供給する構成としても良い。なお、変換数および同時に印加するデータ線数としては、カラーの画像信号が３つの原色に係る信号からなることとの関係から、３の倍数であることが制御や回路などを簡易化する上で好ましい。ただし、後述するプロジェクタのように単なる光変調の用途の場合には、３の倍数である必要はない。
【０１６０】
また、上述した実施形態においては、上から下方向へ走査線１１２を走査する一方、左から右方向へブロックを選択する構成であったが、これとは逆方向で選択する構成でも良いし、用途に応じていずれかの方向を選択可能とする構成でも良い。
【０１６１】
さらに、上述した実施形態においては、素子基板１０１にＴＦＴ１１６等が形成された構成となっていたが、本発明は、これに限られない。例えば、素子基板１０１を半導体基板で構成するとともに、ここに、ＴＦＴ１１６に代えて相補型トランジスタを形成しても良い。さらに、ＳＯＩ（Silicon On Insulator）の技術を適用し、サファイヤ、石英、ガラスなどの絶縁性基板にシリコン単結晶膜を形成して、ここに各種素子を作り込んで素子基板１０１としても良い。ただし、素子基板１０１が透明性を有しない場合、画素電極１１８をアルミニウムで形成したり、別途反射層を形成したりするなどして、液晶パネル１００を反射型として用いる必要がある。
【０１６２】
くわえて、上述した実施形態では、液晶としてＴＮ型を用いたが、ＢＴＮ（Bi-stable Twisted Nematic）型・強誘電型などのメモリ性を有する双安定型や、高分子分散型、さらには、分子の長軸方向と短軸方向とで可視光の吸収に異方性を有する染料（ゲスト）を一定の分子配列の液晶（ホスト）に溶解して、染料分子を液晶分子と平行に配列させたゲストホスト型などの液晶を用いても良い。
【０１６３】
また、電圧無印加時には液晶分子が両基板に対して垂直方向に配列する一方、電圧印加時には液晶分子が両基板に対して水平方向に配列する、という垂直配向（ホメオトロピック配向）の構成としても良いし、電圧無印加時には液晶分子が両基板に対して水平方向に配列する一方、電圧印加時には液晶分子が両基板に対して垂直方向に配列する、という平行（水平）配向（ホモジニアス配向）の構成としても良い。このように、本発明では、液晶や配向方式として、種々のものに適用することが可能である。
【０１６４】
くわえて、電気光学装置としては、液晶装置のほかに、エレクトロルミネッセンス（ＥＬ）や、プラズマ発光や電子放出による蛍光などを用いて、その電気光学効果により表示を行う種々の電気光学装置に適用可能である。この際、電気光学物質としては、ＥＬ、ミラーデバイス、ガス、蛍光体などとなる。なお、電気光学物質としてＥＬを用いる場合、素子基板１０１においてＥＬが画素電極１１８と透明導電膜の対向電極との間に介在することになるので、対向基板１０２は不要となる。このように、本発明は、上述した構成と類似の構成を有する電気光学装置のすべてに適用可能である。
【０１６５】
＜電子機器＞
次に、上述した電気光学装置を電子機器に用いた例のいくつかについて説明する。
【０１６６】
＜その１：プロジェクタ＞
まず、上述した液晶パネル１００をライトバルブとして用いたプロジェクタについて説明する。図１９は、このプロジェクタの構成を示す平面図である。この図に示されるように、プロジェクタ１９００内部には、ハロゲンランプ等の白色光源からなるランプユニット１９０２が設けられている。このランプユニット１９０２から射出された投射光は、内部に配置された３枚のミラー１９０６および２枚のダイクロイックミラー１９０８によってＲＧＢの３原色に分離されて、各原色に対応するライトバルブ１００Ｒ、１００Ｇおよび１００Ｂにそれぞれ導かれる。ここで、ライトバルブ１００Ｒ、１００Ｇおよび１００Ｂの構成は、上述した実施形態に係る液晶パネル１００と同様であり、画像信号を入力する処理回路（ここでは図示省略）から供給されるＲ、Ｇ、Ｂの原色信号でそれぞれ駆動されるものである。また、Ｂ色の光は、他のＲ色やＧ色と比較すると、光路が長いので、その損失を防ぐために、入射レンズ１９２２、リレーレンズ１９２３および出射レンズ１９２４からなるリレーレンズ系１９２１を介して導かれる。
【０１６７】
さて、ライトバルブ１００Ｒ、１００Ｇ、１００Ｂによってそれぞれ変調された光は、ダイクロイックプリズム１９１２に３方向から入射する。そして、このダイクロイックプリズム１９１２において、Ｒ色およびＢ色の光は９０度に屈折する一方、Ｇ色の光は直進する。したがって、各色の画像が合成された後、スクリーン１９２０には、投射レンズ１９１４によってカラー画像が投射されることとなる。
【０１６８】
なお、ライトバルブ１００Ｒ、１００Ｇおよび１００Ｂには、ダイクロイックミラー２１０８によって、Ｒ、Ｇ、Ｂの各原色に対応する光が入射するので、上述したようにカラーフィルタを設ける必要はない。また、ライトバルブ１００Ｒ、１００Ｂの透過像はダイクロイックミラー１９１２により反射した後に投射されるのに対し、ライトバルブ１００Ｇの透過像はそのまま投射されるので、ライトバルブ１００Ｒ、１００Ｂによる表示像を、ライトバルブ１００Ｇによる表示像に対して左右反転させる構成となっている。
【０１６９】
＜その２：モバイル型コンピュータ＞
次に、上述した液晶パネル１００を、モバイル型のパーソナルコンピュータに適用した例について説明する。図２０は、このパーソナルコンピュータの構成を示す斜視図である。図において、コンピュータ２０００は、キーボード２００２を備えた本体部２００４と、表示部として用いられる液晶パネル１００とを備えている。なお、この液晶パネル１００の背面には、視認性を高めるためのバックライトユニット（図示省略）が設けられる。
【０１７０】
＜その３：携帯電話＞
さらに、上述した液晶パネル１００を、携帯電話の表示部に適用した例について説明する。図２１は、この携帯電話の構成を示す斜視図である。図において、携帯電話２１００は、複数の操作ボタン２１０２のほか、受話口２１０４、送話口２１０６とともに、上述した液晶パネル１００を備えるものである。なお、この液晶パネル１００の背面にも、視認性を高めるためのバックライトユニット（図示省略）が設けられる。
【０１７１】
なお、電子機器としては、図１９〜図２１を参照して説明した他にも、液晶テレビや、ビューファインダ型・モニタ直視型のビデオテープレコーダ、カーナビゲーション装置、ページャ、電子手帳、電卓、ワードプロセッサ、ワークステーション、テレビ電話、ＰＯＳ端末、ディジタルスチルカメラ、タッチパネルを備えた機器等などが挙げられる。そして、これらの各種の電子機器に対して、実施形態や応用形態に係る電気光学装置が適用可能なのは言うまでもない。
【０１７２】
【発明の効果】
以上説明したように本発明によれば、いわゆるゴーストの発生が抑えられる結果、高品位な表示が可能となる。
【図面の簡単な説明】
【図１】 （ａ）は、本発明の第１実施形態に係る電気光学装置の外観構成を示す斜視図であり、（ｂ）は、（ａ）のＡ−Ａ’線の断面図である。
【図２】 同電気光学装置における素子基板の電気的な構成を示すブロック図である。
【図３】 同電気光学装置における処理回路の構成を示すブロック図である。
【図４】 同電気光学装置の素子基板の要部における配線を示す平面図である。
【図５】 同電気光学装置の動作を説明するためのタイミングチャートである。
【図６】 同電気光学装置の動作を説明するためのタイミングチャートである。
【図７】 同電気光学装置における微分ノイズの打ち消し動作を説明するためのタイミングチャートである。
【図８】 液晶パネルの表示画面において実際に発生するゴーストを詳細に説明するための図である。
【図９】 液晶パネルにおけるゴーストの発生機構を説明するための電気的な等価回路を示す図である。
【図１０】 本発明の第２実施形態に係る電気光学装置の素子基板の電気的な構成を示すブロック図である。
【図１１】 同電気光学装置における処理回路の構成を示すブロック図である。
【図１２】 同処理回路における補正回路の別構成を示すブロック図である。
【図１３】 該別構成による走査信号の電圧波形を示す図である。
【図１４】 本発明の第３の実施形態に係る電気光学装置の処理回路のうち、補正回路の構成を示すブロック図である。
【図１５】 同補正回路の動作を説明するためのタイミングチャートである。
【図１６】 本発明の第４の実施形態に係る電気光学装置の処理回路のうち、補正回路の構成を示すブロック図である。
【図１７】 本発明の第５の実施形態に係る電気光学装置の処理回路の構成を示すブロック図である。
【図１８】 本発明の第６の実施形態に係る電気光学装置の処理回路の要部構成を示すブロック図である。
【図１９】 実施形態に係る電気光学装置を適用した電子機器の一例たるプロジェクタの構成を示す平面図である。
【図２０】 同電気光学装置を適用した電子機器の一例たるパーソナルコンピュータの構成を示す斜視図である。
【図２１】 同電気光学装置を適用した電子機器の一例たる携帯電話の構成を示す斜視図である。
【図２２】 表示品位の低下を説明するための電圧波形図である。
【符号の説明】
１００…液晶パネル
１０１…素子基板
１０２…対向基板
１０５…液晶
１０８…対向基板
１１２…走査線
１１４…データ線
１１６…ＴＦＴ
１１８…画素電極
１１９…蓄積容量
１２０…周辺回路
１３０…走査線駆動回路
１４０…データ線駆動回路（サンプリング信号出力回路）
１５０…サンプリング回路
１５１…サンプリングスイッチ
１６０…プリチャージ回路
１６１…プリチャージングスイッチ
１７１…画像信号線
１７３…補正信号線
１７５…容量線
１７７…プリチャージ制御線
１７９…プリチャージ信号線
２００…処理回路
２１８…補正回路
２２０…反転加算回路
１９００…プロジェクタ
２０００…パーソナルコンピュータ
２１００…携帯電話[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device capable of high-quality display while suppressing the occurrence of display defects such as so-called ghosts, and an electronic apparatus using the electro-optical device as a display unit.
[0002]
[Prior art]
In general, an electro-optical device, for example, a liquid crystal device that performs predetermined display using liquid crystal as an electro-optical material has the following configuration. That is, in such a liquid crystal device, liquid crystal is sandwiched between a pair of substrates, and a plurality of scanning lines and a plurality of data lines are formed on one substrate so as to intersect with each other. A pair of a switching element and a pixel electrode is provided corresponding to each of the electrodes, and a transparent counter electrode (common electrode) facing the pixel electrode is provided on the other substrate.
[0003]
Here, the image signal is usually supplied via an image signal line and is sampled onto a predetermined data line at an appropriate timing by a sampling switch that is turned on / off according to the sampling signal. The switching element provided at the intersection of the scanning line and the data line is turned on when the scanning signal applied to the corresponding scanning line becomes an active level, and the image signal sampled on the corresponding data line is output. This is supplied to the pixel electrode. Further, the counter electrode provided on the counter substrate is maintained at a constant potential.
[0004]
In such a configuration, when the scanning signal supplied to each scanning line and the sampling switch that regulates the on / off of the sampling switch are controlled at an appropriate timing, the pixel electrode, the counter electrode, and both electrodes are sandwiched. A voltage effective value corresponding to the image signal is applied to the pixel capacitor composed of the liquid crystal for each pixel, and a predetermined display is performed.
[0005]
[Problems to be solved by the invention]
However, such a liquid crystal device has a problem that a display defect called ghost occurs. In particular, recently, in order to cope with higher frequencies, one image signal is serial-parallel converted (phase expansion) into a plurality of h systems (h is an integer of 2 or more), and h times on the time axis. A technology has been developed in which the h system image signals are supplied to the h image signal lines, and the h sampling switches simultaneously sample the h system image signals onto the h data lines. However, in such a technique, since a ghost is generated in units of h data lines, the deterioration of display quality becomes a more serious problem.
[0006]
The present invention has been made in view of the above-described circumstances, and an object thereof is to suppress the generation of so-called ghosts and to provide a high-quality display, and to display the electro-optical device as a display unit. It is to provide an electronic device used for the above.
[0007]
[Means for Solving the Problems]
First, before explaining the means for solving the problem, the inventors of the present invention investigated the ghost generation mechanism described above, and as a result, the following points were considered to be the main causes. That is, since the counter electrode formed on the counter substrate is made of a transparent thin film metal such as ITO (Indium Tin Oxide), it has a resistance, and the counter electrode is not only a pixel electrode. It also faces the image signal line. For this reason, the counter electrode is electrically coupled to the image signal line by a kind of differentiation circuit composed of a resistance component and a capacitance component.
[0008]
Here, assuming that the electro-optical device is in a normally white mode in which white display is performed when, for example, the effective voltage applied to the pixel capacitor is zero, as shown in FIG. 22, the image signal line is supplied. When the voltage of the image signal VID changes from the black level to the white level, the counter electrode voltage also decreases according to the amount of change, and then gradually recovers to the original voltage LCcom according to the degree of capacitive coupling. Will do.
[0009]
At this time, if the image signal is supplied to the pixel electrode in the period SMPa before the voltage of the counter electrode recovers to the original voltage LCcom, the effective voltage applied to the pixel capacitor is reduced by the voltage of the counter electrode. It will become bigger by the amount. On the other hand, when the sampled image signal is supplied to the pixel electrode after the voltage of the counter electrode is restored to the original voltage LCcom, the effective voltage value applied to the pixel capacitor becomes the original value. For this reason, when a gray pixel continues from a black pixel, the gray pixel to be written next to the black pixel becomes blacker than the original density, but the subsequent gray pixel becomes the original density, The density of both gray pixels will be different from each other. Such a phenomenon occurs in the outline of a black pixel and is visually recognized as a display image that should not exist originally, so it has been called a ghost.
[0010]
  Therefore, in order to suppress the occurrence of this ghost, the first invention of the present invention is a pixel electrode formed in a display area on the first substrate, a data line for supplying an image signal to the pixel electrode, the pixel electrode, A counter electrode facing through an electro-optic material, an image signal line formed on the first substrate and supplying an image signal to the pixel electrode, and formed on the first substrate, the image signal line A sampling circuit for sampling the image signal supplied to the data line and supplying the sampling signal to the data line, and arranged in parallel with the image signal line in a peripheral area of the display area, and arranged to face the counter electrode, And a correction signal line to which a correction signal for canceling the level fluctuation of the counter electrode is supplied. A pixel electrode formed in a display region of the first substrate; a data line for supplying an image signal to the pixel electrode; a counter electrode facing the pixel electrode through an electro-optic material; and the first electrode An image signal line formed on the substrate for supplying an image signal to the pixel electrode and an image signal formed on the first substrate and supplied to the image signal line are sampled and supplied to the data line. A correction circuit that is arranged side by side with the image signal line and opposite to the counter electrode in a peripheral area of the display area and the sampling circuit is supplied with a correction signal that is inverted with respect to the image signal based on a predetermined potential. And a correction signal line.
[0011]
According to the first invention having such a configuration, in the counter electrode, the level fluctuation accompanying the voltage change of the image signal supplied to the wiring, and the level fluctuation accompanying the voltage change of the correction signal supplied to the correction signal line, However, since they cancel each other, the original voltage is maintained. Therefore, high-quality display that suppresses the generation of ghosts is possible.
[0012]
  Similarly, in order to suppress the occurrence of ghosts, the second invention of the present invention is provided with a plurality of scanning lines formed on the first substrate and one or more h (h is 2) formed on the first substrate. An image signal is supplied corresponding to a plurality of data lines that are blocked for each book and one or h data lines that are formed on the first substrate and constitute the block. The one or h image signal lines and the image signal supplied to the one or h image signal lines are sequentially sampled for each one or h data lines belonging to the block to be the data lines. A sampling circuit to be supplied, a pixel electrode provided corresponding to the intersection of the scanning line and the data line, a counter electrode facing the pixel electrode through an electro-optic material, and the pixel electrode are arranged in a matrix Around the display area Disposed opposite to the counter electrode in the band, the correction signal for canceling the level variation of the opposing electrode is characterized by comprising a correction signal line to be supplied. In addition, a plurality of scanning lines formed on the first substrate and a plurality of scanning lines formed on the first substrate and divided into one or a plurality of h (h is an integer of 2 or more). A data line, one or h image signal lines formed on the first substrate and supplying an image signal corresponding to one or h data lines constituting the block, and the one or h A sampling circuit for sequentially sampling the image signals supplied to the h image signal lines for each one or h data lines belonging to the block and supplying them to the data lines, and the intersection of the scanning lines and the data lines A pixel electrode provided corresponding to the pixel electrode, a counter electrode facing the pixel electrode via an electro-optical material, and a counter electrode disposed in a peripheral region of a display region where the pixel electrode is arranged in a matrix. The above The image signal, characterized by comprising a correction signal line correction signal obtained by inverting reference to a predetermined potential is supplied.
[0013]
According to the second invention having such a configuration, as in the first invention described above, in the counter electrode, the level fluctuation accompanying the voltage change of the image signal supplied to the image signal line and the correction signal line are supplied to the counter electrode. Since the level fluctuations accompanying the voltage change of the correction signal cancel each other, the original potential is maintained. Therefore, high-quality display that suppresses the generation of ghosts is possible.
[0014]
Here, in the second invention, it is desirable that one or h correction signal lines are separately arranged corresponding to the one or h image signal lines on a one-to-one basis. In this configuration, the image signal line and the correction signal line are paired, and the level change accompanying the voltage change of the image signal supplied to the image signal line, and the voltage change of the correction signal supplied to the correction signal line. Level fluctuations associated with each other cancel each other.
[0015]
Further, in such a configuration, it is sufficient to cancel the level fluctuation due to the voltage change of the image signal as the correction signal. Accordingly, at this time, the correction signal supplied to the one or h correction signal lines is obtained by inverting the image signal supplied to the corresponding image signal line with reference to a predetermined potential. The configuration can be simplified.
[0016]
In the second invention, it is not necessary to separately provide a correction signal line. For example, before sampling by the sampling circuit, each of the data lines is precharged in advance to a precharge voltage applied to the precharge signal line according to a precharge control signal supplied to the precharge control line. If a precharge circuit is provided and the correction signal line is also used as the precharge signal line in a period in which the precharge is not performed, it is not necessary to provide a new wiring as the correction signal line, and the configuration is simplified. It can contribute to the conversion.
[0017]
Also, for example, before sampling by the sampling circuit, each of the data lines is precharged to a precharge voltage applied to the precharge signal line in accordance with a precharge control signal supplied to the precharge control line. If the correction signal line is also used as the precharge control line in a period in which the precharge is not performed, it is not necessary to provide a new wiring as the correction signal line. This can contribute to simplification of the configuration.
[0018]
Further, for example, if the correction signal line is also used as a scanning line in which the scanning signal is at an inactive level, it is not necessary to provide a new wiring as the correction signal line, which similarly contributes to simplification of the configuration. can do.
[0019]
Similarly, for example, a storage capacitor is provided for each pixel electrode, one end of which is connected to the corresponding pixel electrode and the other end is commonly connected to a capacitor line, and the correction signal line is also used as the capacitor line. With this configuration, it is not necessary to provide a new wiring as the correction signal line, which can contribute to simplification of the configuration.
[0020]
In the second invention, when the selected block shifts, a voltage signal having a value obtained by multiplying the sum of the change amounts of the image signals supplied to the one or h image signal lines by the first coefficient. Is preferably provided as a correction signal. This is also because the potential fluctuation of the counter electrode can be suppressed by this configuration.
[0021]
In the second invention, when the precharge circuit for precharging each of the data lines to the precharge voltage and the one block are selected before sampling by the sampling circuit, the one line is selected. Alternatively, it is desirable to include a correction circuit that outputs, as the correction signal, a voltage signal having a value obtained by multiplying the sum of the difference between the image signal to be supplied to the h image signal lines and the precharge voltage by the second coefficient. . This is also because the potential fluctuation of the counter electrode can be suppressed by this configuration.
[0022]
Further, in the second invention, before the sampling by the sampling circuit, the precharge circuit that precharges each of the data lines to the precharge voltage and the one block when the selected block shifts. Or a value obtained by multiplying the total amount of change in the image signals supplied to the h image signal lines by the first coefficient, and an image signal to be supplied to the one or h image signal lines in the selection of the block. It is desirable to include a correction circuit that outputs a voltage signal having a value obtained by adding a value obtained by multiplying the sum of differences from the precharge voltage by a second coefficient as the correction signal. According to this configuration, in addition to the ghost described above, the occurrence of the front ghost and the rear ghost described in the embodiment can be suppressed, so that a higher quality display can be achieved.
[0023]
On the other hand, in the second invention, before the sampling by the sampling circuit, the precharge circuit that precharges each of the data lines to the precharge voltage and the one block when the selected block moves. Or a value obtained by multiplying the total amount of change in the image signals supplied to the h image signal lines by the first coefficient, and an image signal to be supplied to the one or h image signal lines in the selection of the block. A voltage obtained by adding a value obtained by multiplying the sum of differences from the precharge voltage by the second coefficient and a value obtained by multiplying the correction signal output when the block immediately before the block is selected by the third coefficient. A configuration including a correction circuit that outputs a signal as the correction signal is desirable. According to this configuration, in addition to the ghost described above, the occurrence of the front ghost and the rear ghost as described in the embodiment can be suppressed almost completely, so that further high-quality display can be achieved.
[0024]
By the way, in the second invention, a part of the correction signal to be supplied to the correction signal line can be superimposed on the image signal. Specifically, in the second invention, before sampling by the sampling circuit, when the precharge circuit for precharging each of the data lines to the precharge voltage and the selected block shift, A value obtained by multiplying the total amount of change in image signals supplied to the one or h image signal lines by a first coefficient, an image to be supplied to the one or h image signal lines in the selection of the block. 1 of the value obtained by multiplying the sum of the difference between the signal and the precharge voltage by the second coefficient, or the value obtained by multiplying the correction signal output when the block immediately before the current block is selected by the third coefficient. Value or binary addition value is added to each of the image signals to be supplied to the one or h image signal lines in the selection of the block and output, while the other binary addition is performed. Or other value 1 is of a configuration and a circuit for outputting as said correction signal. Also in this configuration, in addition to the ghost described above, the occurrence of the front ghost and the rear ghost as described in the embodiment can be suppressed almost completely, so that a higher quality display can be realized.
[0025]
Furthermore, in order to achieve the above object, the electronic apparatus according to the present invention includes the electro-optical device, so that high-quality display with reduced ghosting is possible.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0027]
<First Embodiment>
First, the electro-optical device according to the first embodiment of the invention will be described. This electro-optical device uses a liquid crystal as an electro-optical material, and performs a predetermined display by the electro-optical change. FIG. 1A is a perspective view showing a configuration of the liquid crystal panel 100 excluding the processing circuit in the electro-optical device, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. It is sectional drawing.
[0028]
As shown in these drawings, in the liquid crystal panel 100, an element substrate 101 on which various elements, a pixel electrode 118, and the like are formed, and a counter substrate 102 on which the counter electrode 108 and the like are formed have spacers (not shown). A sealing material 104 is included so that the electrode forming surfaces are bonded to each other while maintaining a certain gap, and a TN (Twisted Nematic) type liquid crystal 105, for example, is sealed in the gap as an electro-optical material. ing. Here, since the element substrate 101 is not necessarily required to be transparent, a semiconductor or the like can be used in addition to glass or quartz. However, since the counter substrate 102 is required to be transparent, glass or the like is used. It is done. Note that the sealant 104 is formed along the periphery of the counter substrate 102, but a part of the sealant 104 is opened to enclose the liquid crystal 105. Therefore, after the liquid crystal 105 is sealed, the opening portion of the sealing material 104 is sealed with the sealing material 106.
[0029]
Next, a data line driving circuit, which will be described later, is formed in a region 140 a on the opposite surface of the element substrate 101 and on the outer side of the sealing material 104 to output a sampling signal. Further, an image signal line and a sampling circuit, which will be described later, are formed in a region 150a in the vicinity where the sealing material 104 is formed on one side. On the other hand, a plurality of connection terminals 107 are formed on the outer peripheral portion of this side, and various signals from the processing circuit are input.
[0030]
Also, two scanning line driving circuits described later are formed in the side region 130a adjacent to the one side, and the scanning lines are driven from both sides. Note that if the delay of the scanning signal supplied to the scanning line is not a problem, a configuration in which the scanning line driving circuit is formed on only one side may be employed. In addition, in the remaining one side region 160a, in addition to a precharge circuit to be described later, a shared wiring used for two scanning line driving circuits is formed.
[0031]
On the other hand, the counter electrode 108 of the counter substrate 102 is formed on the element substrate 101 by a conductive material provided at two corners close to the region 140a among the four corners in the bonding portion with the element substrate 101, as will be described later. Electrical connection with the connected terminal 107 is achieved, and a constant voltage LCcom is applied over time. In this embodiment, the conductive material is provided at two points. However, the conductive material is provided to electrically connect the counter electrode 108 and the connection terminal 107. It is sufficient that at least one point is provided, or three or more points may be provided. In addition, in the counter substrate 102, a colored layer (color filter) is provided in a region facing the pixel electrode 118, while a decrease in contrast is prevented or a non-display region is defined in a region other than the colored layer. A light shielding layer is provided. However, it is not necessary to form a colored layer on the counter substrate 102 when applied to a color light modulation application as in a projector described later.
[0032]
Note that, regardless of whether or not a colored layer is provided on the counter substrate 102, the element substrate 101 is provided with a light-shielding layer (not shown) for preventing deterioration of element characteristics due to light leakage. Further, on each of the opposing surfaces of the element substrate 101 and the counter substrate 102, an alignment film (not shown) is rubbed so that the long axis direction of molecules in the liquid crystal 105 is continuously twisted by about 90 degrees between the two substrates. On the other hand, a polarizer (not shown) corresponding to the orientation direction is provided on each back side.
[0033]
Here, in each pixel, the light passing between the pixel electrode 118 and the counter electrode 108 is about 90 degrees along the twist of the liquid crystal molecules if the voltage difference applied between the two electrodes is zero. On the other hand, as the voltage difference increases, the liquid crystal molecules tilt in the direction of the electric field, and the optical rotation disappears. For this reason, if the liquid crystal panel 100 is, for example, a transmission type, a voltage difference applied to both electrodes can be obtained by arranging polarizers whose polarization axes are orthogonal to each other in accordance with the rubbing direction on the incident side and the back side. If is zero, light is transmitted (blocked), while light is blocked (transmitted) as the voltage difference applied to both electrodes increases. Therefore, in this configuration, predetermined display is possible by controlling the voltage applied to the pixel electrode 118 for each pixel.
[0034]
<Electrical configuration>
Next, an electrical configuration of the electro-optical device according to the present embodiment will be described. Here, FIG. 2 is a block diagram illustrating a configuration of an element substrate in the electro-optical device, and FIG. 3 is a block diagram illustrating a configuration of a processing circuit in the electro-optical device.
[0035]
<Processing circuit>
For convenience of explanation, the processing circuit will be described first. The processing circuit 200 supplies various signals to the liquid crystal panel 100 via the connection terminal 107. For details, as shown in FIG. 3, a timing generator 212 and an S / P (serial / parallel) are provided. ) The circuit is roughly divided into a conversion circuit 214 and six inverting circuits 216. Among them, the timing generator 212 is based on a vertical scanning signal Vs, a horizontal scanning signal Hs and a dot clock signal DCLK supplied from a host device (not shown), and starts a transfer start pulse DY, a clock signal CLY, a transfer start pulse DX, a clock. A signal CLX, a precharge control signal PG, and a precharge voltage signal Vpre are generated.
[0036]
Briefly explaining these signals, first, the transfer start pulse DY is a pulse signal supplied at the beginning of one vertical effective display period as shown in FIG. Second, the clock signal CLY is a signal used when sequentially transferring the transfer start pulse DY as shown in FIG. Note that the half cycle of the clock signal CLY is one horizontal scanning period 1H. Third, the transfer start pulse DX is a pulse signal supplied at the beginning of one horizontal effective display period, as shown in FIG. Fourth, the clock signal CLX is a transfer signal used when the transfer start pulse DX is sequentially transferred as shown in FIG. The precharge voltage signal Vpre and the precharge control signal PG will be described later.
[0037]
Next, as shown in FIG. 6, the S / P conversion circuit 214 distributes one system of image signal VID supplied in synchronization with the dot clock DCLK to 6 systems and expands it 6 times on the time axis. Thus, the image signals VID1 to VID6 are output. Here, the reason why one image signal VID is converted into six image signals VID1 to VID6 is referred to as a thin film transistor (Thin Film Transistor) constituting a sampling switch in a sampling circuit described later. ) To apply the image signal to the source region for a long period of time to ensure sufficient sampling time and charge / discharge time.
[0038]
The inversion circuit 216 is provided corresponding to each of the image signals VID1 to VID6 by the S / P conversion circuit 214, and inverts the level of the corresponding image signal with the voltage LCcom as a reference and outputs the inverted image signal. Is. Note that the timing of supplying the image signals VID1 to VID6 to the liquid crystal panel 100 is the same in the present embodiment, but in the present invention, they may be sequentially shifted in synchronization with the dot clock DCLK.
[0039]
As described above, each of the output stages of the S / P conversion circuit 214 is provided with the inversion circuit 216. In addition to the level inversion by the inversion circuit 216, the S / P conversion circuit 214 performs serial-parallel conversion. An inversion / amplification circuit that inverts an image signal that requires polarity inversion and then amplifies it appropriately is provided.
[0040]
Note that the polarity inversion in the present embodiment means that the voltage level is alternately inverted between positive polarity and negative polarity based on the voltage LCcom applied to the counter electrode 108, but whether or not the polarity is inverted. In general, the application method of the image signal to the data line is (1) polarity inversion in units of scanning lines, (2) polarity inversion in units of data lines, or (3) polarity inversion in units of pixels. The inversion period is set to one horizontal scanning period or a dot clock period.
[0041]
Here, in this embodiment, for convenience of explanation, (1) the case of polarity reversal in units of scanning lines will be described as an example, but the present invention is not limited to this. Further, in this case, the image signals VID1 to VID6 are set to a level corresponding to the positive side and a level corresponding to the negative side for each horizontal scanning period 1H by the inverting / amplifying circuit provided in the S / P conversion circuit 214. Are alternately inverted. In the present embodiment, a total of 12 image signals, such as the image signals VID 1 to VID 6 and the inverted image signals VID 1 inv to VID 6 inv obtained by inverting the levels of the image signals VID 1 to VID 6, are output from the processing circuit 200. The liquid crystal panel 100 is configured to be supplied.
[0042]
<Element substrate>
Next, the electrical configuration of the element substrate 101 in the liquid crystal panel 100 will be described. First, in the display region of the element substrate 101, as shown in FIG. 2, a plurality of scanning lines 112 are formed in parallel along the row (lateral) direction, and a plurality of data Lines 114 are formed in parallel along the column (vertical) direction. At the intersection of the scanning line 112 and the data line 114, the gate of the TFT 116 serving as a switching element for controlling the pixel is connected to the scanning line 112, while the source of the TFT 116 is connected to the data line 114. At the same time, the drain of the TFT 116 is connected to a rectangular transparent pixel electrode 118.
[0043]
As described above, in the liquid crystal panel 100, since the liquid crystal 105 is sandwiched between the electrode formation surfaces of the element substrate 101 and the counter substrate 102, each pixel includes the pixel electrode 118, the counter electrode 108, and both of them. The liquid crystal 105 is sandwiched between the electrodes. Here, for convenience of explanation, if the total number of scanning lines 112 is “m” and the total number of data lines 114 is “6n” (m and n are integers), the pixels are the same as the scanning lines 112. Corresponding to each intersection with the data line 114, it is arranged in a matrix of m rows × 6n columns.
[0044]
In addition, a storage capacitor 119 for preventing leakage of the liquid crystal capacitor is formed for each pixel in the display region composed of matrix pixels. One end of the storage capacitor 119 is connected to the pixel electrode 118, and the other end is commonly connected by a capacitor line 175. In this embodiment, the capacitor line 175 is grounded to a certain potential (for example, the voltage LCcom, the high-side power supply voltage, the low-side power supply voltage, etc. of the drive circuit) via the connection terminal 107.
[0045]
On the other hand, a peripheral circuit 120 is formed in the non-display area of the element substrate 101. The peripheral circuit 120 is conceptually a circuit including a scanning line driving circuit 130, a data line driving circuit 140, a sampling circuit 150, a precharge circuit 160, and an inspection circuit for determining the presence / absence of a defect after manufacture. However, since the inspection circuit is not directly related to the present case, the description thereof will be omitted.
[0046]
In addition, since the constituent elements of the peripheral circuit 120 are configured by combining the TFT 116 for driving the pixel and the P-channel TFT and the N-channel TFT formed by a common manufacturing process, the manufacturing efficiency is improved and the manufacturing cost is increased. Reduction, uniform device characteristics, and the like.
[0047]
Of the peripheral circuits 120, the scanning line driving circuit 130 outputs scanning signals G1, G2,..., Gm that sequentially become active levels in one horizontal scanning period 1H within one vertical effective display period. . Although details are not directly related to the present invention and are not shown, the shift register and a plurality of AND circuits are included. Among these, as shown in FIG. 6, the shift register applies the transfer start pulse DY supplied at the beginning of one vertical effective display period every time the level of the clock signal CLY changes (both at the rising edge and the falling edge). ), Sequentially shifted and output as signals G1 ′, G2 ′, G3 ′,..., Gm ′, and each AND circuit is adjacent to each other among the signals G1 ′, G2 ′, G3 ′,. Are obtained as scanning signals G1, G2, G3,..., Gm.
[0048]
The data line driving circuit (sampling signal output circuit) 140 outputs sampling signals S1, S2,..., Sn that sequentially become active levels within one horizontal effective display period. Although this detail is not directly related to the present invention and is not shown, it is constituted by a shift register and a plurality of AND circuits. Among these, as shown in FIG. 5 or FIG. 6, the shift register sequentially shifts the transfer start pulse DX supplied at the beginning of one horizontal effective display period every time the level of the clock signal CLX changes, Signals S1 ′, S2 ′, S3 ′,..., Sn ′ are output, and each AND circuit overlaps the pulse widths of the signals S1 ′, S2 ′, S3 ′,. In this case, the sampling signals S1, S2, S3,..., Sn are output after being narrowed to the period SMPa.
[0049]
The image signals VID1 to VID6 supplied from the processing circuit 200 are supplied to the sampling circuit 150 via the image signal line 171 and the inverted image signals VID1inv to VID6inv are supplied to the sampling circuit 150 via the correction signal line 173, respectively. Yes. The sampling circuit 150 includes a sampling switch 151 provided for each data line 114. On the other hand, the data lines 114 are divided into blocks of six, and among the six data lines 114 belonging to the i-th block (i is 1, 2,..., N) counting from the left in FIG. A sampling switch 151 connected to one end of the leftmost data line 114 samples the image signal VID1 supplied via the image signal line 171 during a period in which the sampling signal Si is active, and the data line 114 is provided. Similarly, the sampling switch 151 connected to one end of the second data line 114 out of the six data lines 114 belonging to the i-th block also receives the image signal VID2 supplied via the image signal line 171. Are sampled during a period in which the sampling signal Si is active, and supplied to the data line 114. Similarly, each of the sampling switches 151 connected to one end of the third, fourth, fifth, and sixth data lines 114 among the six data lines 114 belonging to the i-th block is the image signal line. Each of the image signals VID3, VID4, VID5, and VID6 supplied via the H.171 is sampled during a period in which the sampling signal Si is active and supplied to the corresponding data line 114.
[0050]
Note that the inverted image signals VID1inv to VID6inv are supplied to the correction signal line 173. In this embodiment, the inverted image signals VID1inv to VID6inv are not actively used. In this embodiment, the TFT constituting the sampling switch 151 is an N-channel type. Therefore, when the sampling signals S1, S2,..., Sn are at the H level, the TFT becomes the active level. Will close. Note that the TFT constituting the sampling switch 151 may be a P-channel type or a complementary type combining both channels.
[0051]
On the other hand, a precharge circuit 160 is provided in a region opposite to the data line driving circuit 140 with respect to the display region. The precharge circuit 160 includes a precharging switch 161 provided for each data line 114. Each precharging switch 161 has a precharge control signal PG supplied via a precharge control line 177 at an active level. In this case, the precharge voltage signal Vpre supplied via the precharge signal line 179 is precharged to the corresponding data line 114.
[0052]
As shown in FIG. 5, the precharge control signal PG is a signal that becomes an active level in a period isolated from the temporal front and rear ends of one horizontal blanking period. The precharge voltage signal Vpre is a signal whose level is inverted by the voltages Vgr + and Vgr− with reference to the voltage LCcom every horizontal scanning period 1H, as shown in FIG.
[0053]
Here, the voltage LCcom is a temporally constant voltage applied to the counter electrode 108 as described above, and is approximately equal to the amplitude center voltage of the image signals VID1 to VID6. Voltages Vgr + and Vgr− are a precharge voltage when a positive image signal is applied and a precharge voltage when a negative image signal is applied, respectively.
[0054]
According to the precharge circuit 160 having such a configuration, in the blanking period before the horizontal effective display period in which the sampling signals S1, S2, S3,. Since Vgr− is precharged in advance, the load when the image signals VID1 to VID6 are sampled on the data line 114 in the horizontal effective display period immediately after that is reduced.
[0055]
In FIG. 2, only one scanning line driving circuit 130 is arranged on one end side of the scanning line 112. However, this is a measure for the sake of convenience for explaining the electrical configuration. As shown in FIG. 1 and FIG. 4 described later, two are arranged at both ends of the scanning line 112. In FIG. 2, the data line driving circuit 140 is located above the display area, and the precharge circuit 160 is located below the display area. This also explains the electrical configuration. In practice, as shown in FIG. 1 and FIG. 4 described later, the data line driving circuit 140 is positioned below the display area, and the precharge circuit 160 is positioned relative to the display area. Is located above.
[0056]
<Outline of wiring on element substrate>
Next, actual wiring on the element substrate 101, particularly wiring from the data line driving circuit 140 to the sampling circuit 150 will be described. FIG. 4 is a plan view showing the outline of this wiring.
[0057]
As shown in this figure, the six image signal lines 171 to which the image signals VID1 to VID6 are supplied wrap around the data line driving circuit 140 from the left side, while the inverted image signals VID1inv to VID6inv are supplied 6 The two correction signal lines 173 wrap around from the right side with respect to the data line driving circuit 140, and both extend alternately in the X direction in the sampling circuit 150 in a comb-like shape opposed from the left and right sides. .
[0058]
A total of twelve of these image signal lines 171 and correction signal lines 173 are formed by patterning from the same thin-film metal layer with approximately the same width, and are disposed substantially parallel and approximately the same length from the terminal 107. Yes. Therefore, the resistances of the image signal line 171 and the correction signal line 173 are substantially the same.
[0059]
Basically, this arrangement is preferable, but it is not limited to this arrangement order. For example, [VID1 to VID6, VID1inv to VID6inv] or [VID1, VID1inv, VID2inv, VID2, VID3, VID3inv , VID4inv, VID4, VID5, VID5inv, VID6inv, VID6] may be arranged in order of actual layout.
[0060]
Further, as shown in FIG. 1B, the region where the sampling circuit 150 is formed faces the counter electrode 108 when bonded to the counter substrate 102, so that the image signal line 171 with respect to the counter electrode 108 is arranged. The capacitive coupling degree and the capacitive coupling degree of the correction signal line 173 are configured to be substantially the same.
[0061]
In the figure, two electrodes 103 are provided at two points corresponding to the corners of the sealing material 104 (see FIG. 1) while the voltage LCcom is applied from the connection terminal 107. Therefore, when the counter substrate 102 is bonded, the electrode 103 and the counter electrode 108 are electrically connected via the conductive material, and as a result, the voltage LCcom is applied to the counter electrode 108. Note that the capacitor line 175 is disposed in each pixel because it is commonly connected to the other end of the storage capacitor 119 in each pixel as described above.
[0062]
<Operation of electro-optical device>
Next, the operation of the electro-optical device according to the above configuration will be described.
[0063]
First, the transfer start pulse DY is supplied to the scanning line driving circuit 130 at the beginning of one vertical effective display period. As shown in FIG. 6, the transfer start pulse DY is sequentially shifted every time the level of the clock signal CLY changes, and is output as signals G1 ', G2', G3 ',. Then, among these signals G1 ′, G2 ′, G3 ′,..., Gm ′, a logical product signal of signals adjacent to each other is obtained, and scanning signals G1, G2 that become an active level every horizontal scanning period are obtained. , G3,..., Gm are output to the corresponding scanning line 112.
[0064]
First, attention is focused on one horizontal scanning period 1H in which the scanning signal G1 is at an active level. In this one horizontal scanning period, for the sake of convenience of explanation, if writing on the positive electrode side is performed, the image signals VID1 to VID6 output from the S / P conversion circuit 214 are the voltages LCcom applied to the counter electrode 108. With respect to the high-side voltage.
[0065]
Prior to this, as shown in FIG. 5, the precharge control signal PG becomes an active level in a period isolated from the front and rear ends of the blanking period. At this time, the precharge voltage signal Vpre becomes the voltage Vgr + corresponding to the writing on the positive electrode side. For this reason, all the data lines 114 are precharged to the voltage Vgr + during this period.
[0066]
Next, when one horizontal blanking period ends and one horizontal effective display period starts, a transfer start pulse DX is first supplied to the data line driving circuit 140 as shown in FIG. 5 or FIG. . The transfer start pulse DX is output as signals S1 ', S2', S3 ',..., Sn' that are sequentially shifted every time the level of the clock signal CLX transitions. Then, the pulse widths of the signals S1 ′, S2 ′, S3 ′,..., Sn ′ are narrowed to the period SMPa so that adjacent ones do not overlap each other, and the sampling signals S1, S2, S3,. , Sn.
[0067]
On the other hand, the image signal VID of one system input to the processing circuit 200 is distributed to the image signals VID1 to VID6 by the S / P conversion circuit 214 as shown in FIG. The image is doubled and supplied to the liquid crystal panel 100. The image signals VID1 to VID6 are inverted in level by the inverting circuit 216 and supplied to the liquid crystal panel 100 as inverted image signals VID1inv to VID6inv.
[0068]
Here, when the sampling signal S1 becomes active during the period in which the scanning signal G1 becomes active, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to the first block from the left, respectively. The sampled image signals VID1 to VID6 are applied to the corresponding pixel electrodes 118 by the TFTs 116 of the pixels intersecting with the first scanning line 112 and the six data lines 114 counted from the top in FIG. The Rukoto.
[0069]
Thereafter, when the sampling signal S2 becomes an active level, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to the second block, respectively, and these image signals VID1 to VID6 are 1 The TFTs 116 of the pixels intersecting the main scanning line 112 and the six data lines 114 are respectively applied to the corresponding pixel electrodes 118.
[0070]
Similarly, when the sampling signals S3, S4,..., Sn sequentially become active levels, the image signal VID1 is respectively applied to the six data lines 114 belonging to the third, fourth,. ~ VID6 are sampled, and these image signals VID1 to VID6 are applied to the corresponding pixel electrodes 118 by the first scanning line 112 and the TFTs 116 of the pixels intersecting with the six data lines 114, respectively. Become. As a result, writing to all the pixels in the first row is completed.
[0071]
Next, a period during which the scanning signal G2 is active will be described. In this embodiment, as described above, since polarity inversion is performed in units of scanning lines, writing on the negative electrode side is performed in this one horizontal scanning period. For this reason, the image signals VID <b> 1 to VID <b> 6 output from the S / P conversion circuit 214 have a lower voltage than the voltage LCcom applied to the counter electrode 108. Prior to this, since the voltage of the precharge voltage signal Vpre in the blanking period becomes Vgr−, when the precharge control signal PG becomes an active level, all the data lines 114 are precharged to the voltage Vgr−. The Rukoto.
[0072]
Other operations are the same, and the sampling signals S1, S2, S3,..., Sn are sequentially set to the active level, and writing to all the pixels in the second row is completed.
[0073]
Similarly, the scanning signals G3, G4,..., Gm become active, and writing is performed on the pixels in the third row, fourth row,. As a result, the pixels on the odd-numbered rows are written on the positive electrode side, while the pixels on the even-numbered rows are written on the negative electrode side. In this one vertical scanning period, Writing over all the pixels in the m-th row is completed.
[0074]
In the next one vertical scanning period, similar writing is performed, but at this time, the writing polarity for the pixels in each row is switched. That is, in the next one vertical scanning period, the pixels on the odd-numbered rows are written to the pixels on the negative side, while the pixels on the even-numbered rows are written on the positive side.
[0075]
As described above, since the writing polarity for the pixel is switched every vertical scanning period, a direct current component is not applied to the liquid crystal 105, and its deterioration is prevented.
[0076]
Further, in such driving, the time for sampling the image signal by each sampling switch 151 is six times that of the method of driving the data lines 114 one by one, so that the charge / discharge time in each pixel is sufficient. Secured. For this reason, high contrast is achieved. Further, since the number of stages of the shift register in the data line driving circuit 140 and the frequency of the clock signal CLX are each reduced to 1/6, the power consumption can be reduced along with the reduction in the number of stages.
[0077]
Further, the active period of the sampling signals S1, S2,..., Sn is narrowed to a half period of the clock signal CLX and is limited to the period SMPa, so that overlapping of adjacent sampling signals is prevented in advance. The Therefore, it is possible to prevent the image signals VID1 to VID6 to be sampled on the six data lines 114 belonging to a certain block from being simultaneously sampled on the six data lines 114 belonging to the adjacent blocks. High quality display is possible.
[0078]
By the way, since the six image signal lines 171 are arranged in the X direction in the sampling circuit 150 as shown in FIG. 4, when they are bonded to the counter substrate 102, they are capacitively connected to the counter electrode 108. To join. Here, in the conventional configuration in which only the image signal line 171 is provided, the level of the counter electrode 108 fluctuates with the voltage change of the image signals VID1 to VID6, and this is a factor that deteriorates the display quality. What can be considered is as described above.
[0079]
On the other hand, in this embodiment, in addition to the six image signal lines 171 to which the image signals VID1 to VID6 are supplied, the correction signal lines 173 to which the inverted image signals VID1inv to VID6inv are supplied are provided. ing. In this configuration, the six image signal lines 171 and the six correction signal lines 173 are capacitively coupled to the counter electrode 108 as shown in FIG. 7A.
[0080]
Here, since the counter electrode 108 is generally formed of a transparent conductive film such as ITO, its resistivity is relatively large. Therefore, even when a constant voltage LCcom is applied to the counter electrode 108 in time, the counter electrode 108 is affected by voltage changes in the image signal line 171 and the correction signal line 173. Note that the resistance Rcom in FIG. 7A is a general term for the resistance in the counter electrode 108.
[0081]
However, in this embodiment, the signals supplied to the six correction signal lines 173 are inverted image signals VID1inv to VID6inv obtained by inverting the levels of the image signals VID1 to VID6 supplied to the six image signal lines 171, respectively. In addition, the six image signal lines 171 and the six correction signal lines 173 are coupled to the counter electrode 108 with substantially the same capacitance.
[0082]
Therefore, as shown in FIG. 7B, the differential noises D1 to D6 accompanying the voltage changes of the image signals VID1 to VID6 are canceled by the differential noises D1inv to D6inv accompanying the voltage changes of the inverted image signals VID1inv to VID6inv. It will be. Therefore, according to the present embodiment, the counter electrode 108 maintains the original voltage LCcom even if there is a change in voltage in the image signal line 171 and the correction signal line 173, thereby preventing deterioration in display quality. Is possible.
[0083]
<Modification of First Embodiment>
In the present embodiment, six correction signal lines 171 are separately provided corresponding to each of the six image signal lines 171, and an inverted image obtained by inverting the levels of the image signals VID1 to VID6 here. By supplying the signals VID1inv to VID6inv, the differential noises D1 to D6 accompanying the voltage changes of the image signals VID1 to VID6 are canceled by the differential noises D1inv to D6inv accompanying the voltage changes of the inverted image signals VID1inv to VID6inv. The present invention is not limited to this. In short, it is sufficient to use a configuration in which a correction signal is supplied to the counter electrode 108 via a capacitor by some kind of wiring so as to cancel out the level fluctuation accompanying the voltage change of the image signals VID1 to VID6.
[0084]
Here, the capacitive coupling with the counter electrode 108 is not limited to the image signal line 171, but the scanning line 112, the data line 114, the capacitor line 175, the precharge control line 177, the precharge signal line 179, and the like are also opposed. Capacitively coupled to electrode 108. Of these, the scanning line 112 can be used as a correction signal line as long as it is within a range that does not affect the operation of the TFT 116, as long as it is limited to a period excluding one selected horizontal scanning period. It is. In addition, since the period during which the precharge control line 177 and the precharge signal line 179 are effectively used is limited to one horizontal blanking period, the operation of the precharging switch 161 is affected during one horizontal effective display period. If it is within the range, it can be used as a correction signal line. Further, the capacitor line 175 can also be used as a correction signal line.
[0085]
As described above, when the scanning line 112, the capacitor line 175, the precharge control line 177, and the precharge signal line 179 are used as the correction signal lines, wiring such as the correction signal line 173 in the above embodiment is provided on the element substrate 101. There is an advantage that it does not need to be formed separately. Here, when the scanning line 112, the capacitor line 175, the precharge control line 177, and the precharge signal line 179 are used as the correction signal lines, the correction signal is a change amount of the image signal lines VID1 to VID6 as described later. A voltage signal having a value obtained by multiplying the sum of the values by a negative coefficient may be used.
[0086]
<Problem of the first embodiment>
In the first embodiment described above, the level change of the counter electrode 108 due to the voltage change of the image signals VID1 to VID6 is canceled by the voltage change of the inverted image signals VID1inv to VID6inv, respectively, and the level of the counter electrode 108 is made constant. Therefore, the occurrence of ghost was suppressed.
[0087]
Here, in the first embodiment described above, the data line 114 is precharged to the voltage (Vgr + or Vgr−) of the precharge voltage signal Vpre before sampling of the image signal, so the voltage of the data line 114 is At the time of sampling, the voltage changes from the precharge voltage to the voltage of the sampled image signal. As described above, since the data line 114 is also capacitively coupled to the counter electrode 108, a correction signal should be supplied in consideration of this voltage change.
[0088]
However, in the first embodiment described above, the voltage change of the image signals VID1 to VID6 in the image signal line 171 is considered, but the voltage change of the data line 114 is not taken into consideration. There is room. In fact, it has been confirmed by the inventor of the present invention that in the configuration in which one system of image signal VID is distributed / expanded to 6 systems, a display problem completely different from the ghost discussed so far occurs. .
[0089]
Here, the details of such display defects will be described. FIG. 8 is a diagram showing the display contents of pixels in a part of the display area in order to explain such a problem. Note that it is assumed that the contents as shown in this figure are displayed by the configuration in which the correction signal line 173 in the first embodiment does not exist. This is a measure for clarifying the problem of the first embodiment.
[0090]
In FIG. 8, the X direction is the extending direction of the scanning line 112 and indicates the output direction of the sampling signals S1, S2, S3,..., Sn, and the Y direction is the extending direction of the data line 114. ., Gm output directions of the scanning signals G1, G2, G3,. One square indicates a display state by one pixel, and the pixels are also divided into blocks every six columns.
[0091]
Now, as shown in this figure, a display defect is clearly visible when a black rectangular window is displayed against a gray-scale gray pixel as a background. Further, this defect occurs in units of blocks of the data line 114, and the degree thereof depends on the width occupied by the left and right edges of the black square in the block. The display defects can be classified into the following three types.
[0092]
First, there is a defect that appears in a pixel that should be gray other than the black display pixel in the block in which the left end of the black rectangular window is located. Since this defect occurs on the left side of the black rectangular window (opposite to the output direction of the sampling signal), for convenience of explanation, if it is called a front ghost, the front ghost is a window that covers the block. It is inconspicuous when the width is narrow, but it becomes brighter and more conspicuous as the window width increases.
[0093]
Second, among the blocks in which the right end of the black rectangular window is located, there is a problem that appears in pixels that should be gray other than black display pixels. Since this defect occurs on the right side of the black square window (on the output side of the sampling signal), for convenience of explanation, if it is called a post-ghost, the post-ghost has a narrow window width in the block. Sometimes it becomes dark and stands out, and once it becomes inconspicuous as the window width widens, but it becomes brighter and stands out when the window width further widens.
[0094]
Third, there is a display defect that appears over the entire six gray pixels belonging to the block on the right one side of the block on which the right end of the black rectangular window is located. Since this defect occurs in the left block of the black rectangular window, for convenience of explanation, if it is called the next ghost, this next ghost is inconspicuous when the window width applied to the left block of the block is narrow, It becomes darker and more conspicuous as the window width increases.
[0095]
Here, regarding the electrical equivalent circuit in the configuration in which the correction signal line 173 of the first embodiment does not exist, in addition to the voltage change of the image signal on the image signal line 171, the voltage change of the data line 114 at the time of sampling. Consider in detail including. FIG. 9 is a diagram showing the configuration of this electrical equivalent circuit.
[0096]
In the figure, the resistance Rcom indicates the resistance component of the counter electrode 108. The counter electrode 108 is applied with a constant voltage LCcom as described above. Further, C1 to C6 are parasitic capacitances between the image signal line 171 and the counter electrode 108 to which the image signals VID1 to VID6 are supplied, respectively. In addition, the six image signal lines 171 are the i-th (i is for general description of the block and is an integer of 1, 2, 3,..., N). While the sampling switches 151 corresponding to the data lines 114 belonging to the block are respectively connected, the six data lines 114 belonging to the block are capacitively connected to the counter electrode 108 through the TFT 116, the pixel electrode 118, and the liquid crystal 105, respectively. And capacitively coupled to the capacitor line 175 via the TFT 116 and the storage capacitor 119, respectively. Therefore, the parasitic capacitance including the pixel capacitance and the storage capacitance in the six data lines 114 belonging to one block is indicated as C11 to C16, respectively.
[0097]
Note that FIG. 9 illustrates the electrical equivalent circuit of the element substrate 101 in a simplified manner by describing resistance components such as the scanning line 112 and the capacitor line 175, parasitic capacitances generated in these elements, and the source / drain of the sampling switch 151. The inter-space capacity is omitted. However, these can be considered to be included in any of the resistor RCcom, the capacitors C1 to C6, and C11 to C16 in FIG. For example, the source / drain capacitance of the sampling switch 151 can be considered as a coupling capacitance between the image signal line 171 and the data line 114 belonging to the non-selected block. Further, the data line 114 includes the TFT 116. Since the pixel electrode and the storage capacitor 119 are connected to each other, it can be considered that any of the parasitic capacitances C1 to C6 between the image signal line 171 and the counter electrode 108 is present.
[0098]
In such an equivalent circuit, as described in the first embodiment, the resistor RCcom and the capacitors C1 to C6 constitute a differentiating circuit. Therefore, the image signals VID1 to VID1 supplied to the image signal line 171 are used. When the voltage of VID6 changes, the counter electrode 108 is distorted with a differential waveform having a wave height corresponding to the amount of change. Similar distortion occurs in the capacitor line 175. The occurrence of such voltage distortion is referred to as “Factor 1” for convenience of explanation.
[0099]
Next, when the i-th block is selected, six sampling switches 151 corresponding to the block are simultaneously turned on. For this reason, the six data lines 114 belonging to the block are charged and discharged from the precharge voltage to the voltages of the corresponding image signals VID to VID6. At this time, voltage distortion with a wave height corresponding to the magnitude of the charge / discharge current occurs in the counter electrode 108. The occurrence of such voltage distortion is referred to as “Factor 2” for convenience of explanation.
[0100]
The voltage distortion in the differential waveform due to “Factor 1” and “Factor 2” as described above attenuates with time, but until the selection of the i-th block is completed, that is, the sampling switch corresponding to the block. If 6 of 151 does not become zero before turning off, an error occurs in the voltage applied to the pixel capacitor, which causes display unevenness. For example, the voltage of the image signal VID1 is set to V₀And the error voltage remaining on the counter electrode 108 when the selection of the i-th block is completed is V_EThen, the voltage between the data line 114 and the counter electrode 108 is V₀-V_EThis voltage is stored in the parasitic capacitors C1 and C11 as they are. When the sampling switch is turned off, the voltage is maintained, resulting in display unevenness. The same applies to the image signals VID2 to VID6 other than the image signal VID1.
[0101]
Next, such display unevenness will be generally described. First, the i-th block is selected, and each of the h data lines belonging to the block is connected to V_{i, j}Assuming that Here, h is for generalizing the serial / parallel conversion described above, and h = 6 in the first embodiment described above.
[0102]
In this case, immediately before the i-th block is selected, the error voltage remaining in the counter electrode 108 is expressed as V_{ε 0}Let us consider a state immediately after the i-th block is selected. In this state, the error voltage generated in the counter electrode 108 due to “Factor 1” is expressed as follows (Equation 1).
[0103]
[Expression 1]

However, in the above term (Equation 1), ζ is a constant, and V_{i-1, j}Is a voltage supplied to the data line corresponding to the image signal VIDj (j = 1, 2, 3,..., H) when the (i−1) -th block is selected.
[0104]
Similarly, the error voltage generated in the counter electrode due to “Factor 2” is expressed as follows (Formula 2).
[0105]
[Expression 2]

However, in the above term (Equation 2), ξ is a constant, and Vpre is a precharge voltage.
[0106]
Therefore, the total error voltage generated in the counter electrode 108 is expressed as follows (Equation 3).
[0107]
[Equation 3]

Here, immediately before the end of selection of the i-th block, a function (hereinafter referred to as an error function f) using an image signal as a variable, as shown in the following equation (Equation 4), multiplied by a constant attenuation coefficient k._errIt can be expressed as
[0108]
However, V_{ε 0}Is the total error voltage immediately before the end of selection of the (i-1) th block.
[0109]
[Expression 4]

Next, this error function f_errEach ghost shown in FIG. 8 will be described with reference to FIG. First, consider the previous ghost. All the pixels located on the left side of the black window in the block where the pre-ghost is generated are gray. Therefore, when the voltage applied to such a grayscale gray pixel is considered to be a voltage equal to the precharge voltage Vpre, for example, the voltage V in the (i−1) th block which is the immediately preceding block._{i-1, j}Becomes Vpre and the voltage V in the i-th block_{i, j}Is Vpre or greater. For this reason, for example, in the writing on the positive electrode side, the error function f expressed by the above equation (Equation 4)_errBoth the second and third terms are non-negative. And V_{i , j}As the number of pixels with> Vpre increases (that is, as the width of the black window occupying the block increases), both the second term and the third term increase, and the error increases to the positive side and is applied to the pixel capacitance. It can be seen that bright unevenness results from the effect that the effective voltage value decreases. This point coincides with the state of the previous ghost described with reference to FIG.
[0110]
Subsequently, the rear ghost also becomes brighter as the width of the black window in the block increases. However, the error function f_errThe second term is non-negative in, for example, writing on the positive electrode side. However, if the width of the black window is narrow, the third term turns to a negative value, and the absolute value increases as the width becomes narrower. For this reason, as the width of the black window in the block becomes narrower, the influence of the third term becomes more dominant than the second term, resulting in dark display unevenness. This point also coincides with the state of the ghost described with reference to FIG.
[0111]
In the next ghost, the error function f_errThe second term in is zero, and the third term is not positive, for example, in writing on the positive side. In addition, as the width occupied by the black window in the (i-1) th block in which the black window exists increases, the absolute value of the third term increases and dark display unevenness occurs.
[0112]
In this way, it is considered that the front ghost, the rear ghost, and the next ghost are generated. In the case of h = 1, in other words, even in the case of so-called dot-sequential scanning drive (when serial / parallel conversion is not performed), a ghost is generated as understood from the above equation (Equation 4).
[0113]
After all, there is a problem that such a ghost occurs and the quality of the display image deteriorates. Here, in the first embodiment described above, the error function f_errThe third term is considered, but the first and second terms are not considered. As described in the modification of the first embodiment, the existing wiring can be used as the correction signal line.
[0114]
Therefore, hereinafter, the error function f in the above equation (Equation 4)_errThe second to sixth embodiments in consideration of the items will be described.
[0115]
Second Embodiment
First, using the precharge signal line 179 as the correction signal line, the error function f_errA second embodiment for canceling the component of the third term will be described.
[0116]
The electro-optical device according to the second embodiment is different from the first embodiment in that the element substrate 101 is slightly changed as shown in FIG. 10 and the processing circuit 200 shown in FIG. 11 is replaced with the processing circuit 202 shown in FIG. 11, and the others are the same as those in the first embodiment. Therefore, the same reference numerals are given and the description thereof is omitted.
[0117]
First, in the element substrate 101 in the second embodiment, as shown in FIG. 10, the correction signal line 173 in the first embodiment is eliminated, and the signal supplied to the precharge signal line 179. Is different from the element substrate in the first embodiment (see FIG. 2) in two points, that is, the precharge voltage signal / correction signal PS.
[0118]
On the other hand, in the processing circuit 202 in the second embodiment, a correction circuit 218 is newly provided in place of the inversion circuit 216 (see FIG. 3), as shown in FIG. However, it is different from the processing circuit 200 in the first embodiment.
[0119]
Here, the correction circuit 216 includes an inverting addition circuit 220 and a switch SW1. Among them, the inverting addition circuit 220 adds each voltage of the image signals VID1 to VID6 converted by the S / P conversion circuit 214, and multiplies the added value by an appropriate coefficient (negative) to obtain a correction signal Vcmp1. Output. Note that the inversion reference in the inversion adding circuit 220 is the voltage LCcom applied to the counter electrode 108 as described above.
[0120]
The switch SW1 selects the precharge voltage signal Vpre when the precharge control signal PG is at the active level, and selects the correction signal Vcmp1 when the precharge control signal PG is at the inactive level. Thus, the precharge voltage signal and the correction signal PS are output.
[0121]
In such a configuration, the correction circuit 218 outputs the precharge voltage signal Vpre as the precharge voltage signal / correction signal PS in one horizontal blanking period. Therefore, in one horizontal blanking period before each block is selected, each data line 114 is precharged to the voltage (Vgr + or Vgr−) of the precharge voltage signal Vpre as in the first embodiment. It becomes.
[0122]
On the other hand, the correction circuit 218 outputs the correction signal Vcmp1 according to the voltages of the image signals VID1 to VID6 every time each block is selected in one horizontal effective display period in which each block is selected. Here, when the selected block shifts from the (i-1) th block to the ith block, the correction signal Vcmp1 is supplied to the six data signals 114 belonging to the (i-1) th block. From the voltage obtained by multiplying the sum of the voltages of the image signals VID1 to VID6 by a negative coefficient, the sum of the voltages of the image signals VID1 to VID6 supplied to the six data signals 114 belonging to the i-th block is multiplied by a negative coefficient. Will fluctuate up to the voltage. Then, as a result of this voltage fluctuation being supplied to the counter electrode 108 via the parasitic capacitance of the precharge signal line 179, the error function f expressed by the above equation (Equation 4) is obtained._errAmong these, the component of the third term is canceled out.
[0123]
Therefore, according to the second embodiment, as in the first embodiment, the error function f_errThe display unevenness caused by the third term component can be eliminated. Furthermore, in the second embodiment, since the precharge signal line 179 is also used as a correction signal line, the configuration can be simplified as compared with the first embodiment having the correction signal line 173 separately. It becomes. However, it goes without saying that a correction signal line may be provided separately.
[0124]
<Modification of Second Embodiment>
In the second embodiment described above, the correction signal line is also used as the precharge signal line 179. However, the counter electrode 108 and the capacitor are also used for the scanning line 112, the capacitor line 175, and the precharge signal line 177. Therefore, a configuration in which this is also used as a correction signal line is possible.
[0125]
For example, when the scanning line 112 is also used as a correction signal line, the configuration shown in FIG. That is, first, the inverting addition circuit 220 obtains the sum of the voltages of the image signal lines VID1 to VID6, obtains a correction signal Vcmp1 multiplied by an appropriate coefficient (negative), and second, the inverting addition circuit 232 The voltage addition value of the correction signal Vcmp1 and the inactive level VGoff of the scanning signal is obtained and the level is inverted. Third, the output of the inversion adding circuit 232 is inverted again by the inversion circuit 234, and fourthly, In the scanning line driving circuit 130, the switch SWa corresponding to one of the scanning lines 114 selects the active level VGon when the scanning signal Gx of the scanning line 112 should be an active level, while in other cases May be configured to select the output signal of the inverting circuit 234.
[0126]
According to such a configuration, the horizontal scanning line 112 is selected as the scanning signal Gy (y is 1, 2, 3,..., M) supplied to the scanning line 112 as shown in FIG. In one horizontal scanning period 1H, the active level VGon is obtained. In other periods, the inactive level VGoff is added to the correction signal Vcmp1, and the level is determined according to the selection of each block. The level will change. Then, as a result of this level fluctuation being supplied to the counter electrode 108 via the parasitic capacitance, the error function f of the above equation (Equation 4) is obtained as in the second embodiment described above._errThe component of the third term is canceled out.
[0127]
In such a configuration, the correction signal Vcmp1 is added to the inactive level VGoff, but this added voltage is sufficiently separated from the threshold voltage VGth of the TFT 116 as shown in FIG. And it is within the off margin. Therefore, such addition does not hinder the on / off control of the TFT 116 which is the original function of the scanning signal.
[0128]
By the way, in such a configuration, the correction signal Vcmp1 cannot be supplied because the switch SWa selects the active level VGon in one horizontal scanning period 1H in which the scanning line 112 is selected. Therefore, during the period when the display screen is divided into two vertically and the scanning line 112 belonging to the upper half is selected, the correction signal Vcmp1 is added to the scanning line 112 belonging to the lower half and output, while the scanning belonging to the lower half is scanned. In the period in which the line 112 is selected, it is desirable that the correction signal Vcmp1 be added to the scanning line 112 belonging to the upper half and output.
[0129]
Note that although the scanning line 112 is also used as a correction signal line here, a configuration in which the precharge control line 177 is also used as a correction signal line is possible. When the precharge control line 177 is also used as a correction signal line in this way, the correction signal Vcmp1 is set to the active level when precharging is performed in one horizontal blanking period, and to the inactive level at other times. The added level may be supplied to the precharge control line 177.
[0130]
<Third Embodiment>
Next, the error function f in the equation (Equation 4)_errA third embodiment for canceling the component of the second term will be described.
[0131]
In the second embodiment, the element substrate 101 itself is the same as that of the second embodiment, except that the inverting addition circuit 220 shown in FIG. 11 is replaced with the circuit shown in FIG. That is, the third embodiment uses a precharge signal line 179 as a correction signal line, as in the second embodiment. In addition, since others are common to the first and second embodiments, the same reference numerals are given and description thereof is omitted.
[0132]
The circuit shown in FIG. 14 includes a subtracting circuit including switches SW2 and SW3, capacitors C21 to C26, a resistor R1, and a buffer 223. Among these, the switch SW2 is composed of six double throw switches provided corresponding to each of the image signals VID1 to VID6, and one of the input terminals of each double throw switch corresponds to one of the image signals VID1 to VID6. The precharge voltage signal Vpre is supplied to the other end of the input. Here, each double-throw switch selects the corresponding one of the image signals VID1 to VID6 when the control signal Sg2 is at the H level, while the precharge voltage signal Vpre is selected when the control signal Sg2 is at the L level. To choose. One ends of capacitors C21 to C26 are connected to the output ends of these six double throw switches, respectively.
[0133]
Next, the other ends of the capacitors C21 to C26 are connected in common, and the common connection portion is connected to the input end of the buffer 223, is grounded via the resistor R1, and is further connected to one end of the single throw switch SW3. Has been. Here, the single throw switch SW3 is closed, for example, when the control signal Sg3 is at the H level, and the other end is grounded. The buffer 223 is a voltage buffer that buffers the voltage supplied to its input terminal and outputs it as a signal Pa.
[0134]
Subsequently, the output end of the buffer 223 is connected to one end of the single throw switch SW4. The single throw switch SW4 is closed when the control signal Sg4 is at H level, for example, and the other end is connected to the input end of the buffer 225 and one end of the capacitor C32. Here, the buffer 225 is a voltage buffer similar to the buffer 223, and the other end of the capacitor C32 is grounded. Therefore, the output signal Pa from the buffer 223 is sampled by opening and closing the single throw switch SW4 and held by the capacitor C31, and the hold voltage is output from the buffer 225 as the output signal Pb.
[0135]
The output signal Pb is multiplied by an appropriate coefficient (negative) by the inversion magnification circuit 235 and output as the correction signal Vcmp2, which is replaced with the correction signal Vcmp1 in FIG. 11 and supplied to the switch SW1. It has become.
[0136]
Here, the control signals Sg2 to Sg4 change in a level relationship as shown in FIG. 15 with respect to the clock signal CLX. First, immediately before the block is selected, the control signal Sg2 is at the L level, so the six single throw switches respectively select the precharge signal voltage Vpre. Therefore, the capacitors C21 to C26 are charged to the precharge signal voltage Vpre.
[0137]
Subsequently, since the control signal Sg2 becomes H level at the boundary of block selection, the six single throw switches select the image signals VID1 to VID6. As a result, the precharge voltage signal Vpre is applied to the input terminal of the buffer 223. And a differential waveform having a wave height corresponding to the sum of the differences between the image signals VID1 to VID6.
[0138]
On the other hand, at the block selection boundary, the control signal Sg4 immediately goes to L level after it goes to H level. For this reason, the peak value corresponding to the sum of the differences between the precharge voltage signal Vpre and the image signals VID1 to VID6 is sampled and held, and is output from the buffer 225 as the signal Pb. The sampled and held signal Pb is multiplied by an appropriate coefficient by the inversion magnification circuit 235 and output as a correction signal Vcmp2.
[0139]
Therefore, in such a configuration, every time a block is selected, a voltage corresponding to the sum of the differences between the precharge voltage Vpre and the image signals VID1 to VID6 supplied in the block is output as the correction signal Vcmp2. It will be. Then, as a result of this voltage fluctuation being supplied to the counter electrode 108 via the parasitic capacitance of the precharge signal line 179, the error function f of the above equation (Equation 4) is obtained._errSince the second term component is canceled out, display unevenness caused by the second term component can be eliminated.
[0140]
Note that the switch SW3 in FIG. 14 may be omitted in nature, but the resistance R1 is short-circuited by momentarily closing the control signal Sb2 while the control signal Sb2 is at the L level (see the control signal Sb3 in FIG. 15). A precharge voltage Vpre is provided for accurately charging the capacitors C21 to C26.
[0141]
In the third embodiment, the correction signal Vcmp2 is supplied to the counter substrate 108 via the precharge signal line 179 in the element substrate 101. However, the scanning line 112 and the precharge control line are also provided. As in the second embodiment, the voltage may be supplied via 177, the capacitor line 175, and the new wiring.
[0142]
<Fourth embodiment>
Next, the error function f in the equation (Equation 4)_errA fourth embodiment for canceling the second and third terms will be described.
[0143]
In the fourth embodiment, the element substrate 101 itself is the same as in the second and third embodiments, except that the inverting addition circuit 220 shown in FIG. 11 is replaced with the circuit shown in FIG. That is, the fourth embodiment also uses the precharge signal line 179 as the correction signal line, as in the second and third embodiments.
[0144]
Here, the circuit shown in FIG. 16 obtains the sum of the signal Pb and the image signals VID1 to VID6 in FIG. 14 by the inverting addition circuit 228, and multiplies the sum by an appropriate coefficient to obtain the correction signal Vcmp3 (= Vcmp1 + Vcmp2) is output.
[0145]
Therefore, according to the fourth embodiment, the error function f in the equation (Equation 4)_errSince the components of the second and third terms can be canceled out, it is possible to eliminate not only the next ghost but also the previous ghost and further the next ghost.
[0146]
In the fourth embodiment, the correction signal Vcmp2 is supplied to the counter substrate 108 via the precharge signal line 179 in the element substrate 101. However, in addition to this, the scanning line 112 and the precharge control line are provided. It is the same as in the second to fourth embodiments that the voltage may be supplied via 177, the capacitor line 175, and the new wiring.
[0147]
<Fifth Embodiment>
Next, the error function f in the equation (Equation 4)_errA fifth embodiment for canceling all the first, second and third terms will be described.
[0148]
In the fifth embodiment, the element substrate 101 itself is the same as in the second to fourth embodiments, except that the inverting addition circuit 220 shown in FIG. 11 is replaced with the circuit shown in FIG. That is, the fifth embodiment also uses the precharge signal line 179 as the correction signal line, as in the second to fourth embodiments.
[0149]
Here, the circuit shown in FIG. 17 obtains the sum of the signal Pb, the image signals VID1 to VID6, and the signal Pd in FIG. Is inverted and the level is inverted and output as a correction signal Vcmp4.
[0150]
Among these, the signal Pd is output by the following configuration. That is, the inverting circuit 235 that inverts the level of the correction signal Vcmp4 output when the (i-1) th block is selected, and the output signal Pc of the inverting circuit 235 is sampled and held, and the ith block The signal Pb is output by the sample and hold circuit that outputs during the period when the block is selected. The sample and hold circuit is composed of a switch SW5 for sampling the signal Pc, a capacitor C32 for holding the sampled voltage, and a buffer 227.
[0151]
According to such an embodiment, the error voltage V remaining on the counter electrode 108 immediately before the i-th block is selected._{ε 0}Since the component of the first term can also be canceled together with the components of the second and third terms, a higher-quality display can be achieved as compared with the fourth embodiment.
[0152]
<Sixth Embodiment>
Note that the error function f in the equation (Equation 4)_errAs for the configuration for canceling the components of the first term, the second term, and the third term, the correction for canceling the component of each term in the precharge signal line 179 used as the correction signal line as in the fifth embodiment. In addition to the configuration for supplying the signal Vcmp4, the correction signal that cancels the component of a certain term is superimposed on the image signals VID1 to VID6 that are analog signals, while the correction signal that cancels the component of the other term is a correction signal line. A configuration may be employed in which the precharge signal line 179 or the like to be used is supplied.
[0153]
For example, the error function f_errThe correction signal for canceling the second term component is superimposed on each of the image signals VID1 to VID6, while the correction signal for canceling the first term and third term components is used as a correction signal line. It is good also as a structure supplied to etc.
[0154]
Among such configurations, the error function f_errThe configuration for superimposing the correction signal for canceling the component of the second term on each of the image signals VID1 to VID6 may be as follows, for example. That is, the circuit shown in FIG. 18 may be inserted in the next stage of the S / P conversion circuit 214, and the image signals VID1 'to VID6' that are the outputs of this circuit may be supplied to the liquid crystal panel 100. In the circuit shown in FIG. 18, the adder circuit 242 calculates the difference between each of the image signals VID1 to VID6 and the precharge voltage Vpre, and outputs a correction signal by multiplying the sum of the differences by an appropriate coefficient. The addition circuit 244 adds the correction signal V to each of the image signals VID1 to VID6.
[0155]
On the other hand, the error function f_errAs for the correction signal for canceling the components of the first term and the third term, the signal Pb is not input to the inverting addition circuit 229 in FIG.
[0156]
According to the sixth embodiment as described above, high-quality display in which the occurrence of ghosts is suppressed can be performed as in the fifth embodiment described above.
[0157]
In the present embodiment, the error function f_errThe correction signal for canceling the second term component is superimposed on each of the image signals VID1 to VID6, while the correction signal for canceling the first term and third term components is preliminarily used as a correction signal line. Although it is configured to supply to the charge signal line 179 and the like, various other modes are possible. In short, the error function f_errAmong them, a correction signal for canceling a component of a certain term is superimposed on the image signals VID1 to VID6, while a correction signal for canceling a component of some or all of the remaining terms is corrected by a correction signal line. The configuration may be such that it is supplied to the precharge signal line 179 and the like used as the above.
[0158]
In general, the image signal is digitally supplied, converted into analog, and finally supplied to the liquid crystal panel 100. For this reason, when the correction signal is superimposed on the image signals VID1 to VID6 as in this embodiment, the digital correction signal is added to the digital image signal, and then converted into an analog signal and supplied to the liquid crystal panel 100. It is good also as composition to do.
[0159]
<Others>
In the embodiment described above, the six data lines 114 are grouped into one block, and the image signals VID1 to VID6 converted into six systems with respect to the six data lines 114 belonging to one block. However, the number of conversions and the number of data lines applied simultaneously (that is, the number of data lines constituting one block) are not limited to “6”. For example, if the response speed of the sampling switch 151 in the sampling circuit 150 is sufficiently high, the image signal is serially transmitted to one image signal line without being converted into parallel and sequentially sampled for each data line 114. You may comprise. Further, assuming that the number of conversions and the number of data lines to be applied simultaneously are “3”, “12”, “24”, etc., three-line conversion, twelve, twenty-four data lines, etc. A configuration may be adopted in which image signals subjected to system conversion, 24-system conversion, and the like are simultaneously supplied. Note that the number of conversions and the number of data lines to be applied simultaneously are multiples of 3 in order to simplify the control, the circuit, etc., because the color image signal is composed of signals related to the three primary colors. preferable. However, in the case of a simple light modulation application such as a projector described later, it is not necessary to be a multiple of 3.
[0160]
In the above-described embodiment, the scanning line 112 is scanned from the top to the bottom, while the block is selected from the left to the right. However, the configuration may be selected in the opposite direction. A configuration in which one of the directions can be selected according to the application may be used.
[0161]
Furthermore, in the above-described embodiment, the TFT 116 and the like are formed on the element substrate 101. However, the present invention is not limited to this. For example, the element substrate 101 may be formed of a semiconductor substrate, and a complementary transistor may be formed here instead of the TFT 116. Further, an SOI (Silicon On Insulator) technique may be applied to form a silicon single crystal film on an insulating substrate such as sapphire, quartz, or glass, and various elements may be formed therein to form the element substrate 101. However, when the element substrate 101 does not have transparency, it is necessary to use the liquid crystal panel 100 as a reflective type by forming the pixel electrode 118 with aluminum or separately forming a reflective layer.
[0162]
In addition, in the above-described embodiment, the TN type is used as the liquid crystal, but a bistable type having a memory property such as a BTN (Bi-stable Twisted Nematic) type and a ferroelectric type, a polymer dispersion type, Dissolve a dye (guest) having anisotropy in absorption of visible light in the major axis direction and minor axis direction of the molecule in a liquid crystal (host) with a certain molecular arrangement, and arrange the dye molecule in parallel with the liquid crystal molecule. Alternatively, a guest-host type liquid crystal may be used.
[0163]
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.
[0164]
In addition to the liquid crystal device, the electro-optical device can be applied to various electro-optical devices that display by the electro-optical effect using electroluminescence (EL), plasma emission or fluorescence by electron emission. It is. In this case, the electro-optical material is EL, mirror device, gas, phosphor, or the like. Note that in the case where EL is used as the electro-optical material, the EL is interposed between the pixel electrode 118 and the counter electrode of the transparent conductive film in the element substrate 101, so that the counter substrate 102 is not necessary. Thus, the present invention can be applied to all electro-optical devices having a configuration similar to the above-described configuration.
[0165]
<Electronic equipment>
Next, some examples in which the above-described electro-optical device is used in an electronic apparatus will be described.
[0166]
<Part 1: Projector>
First, a projector using the liquid crystal panel 100 described above as a light valve will be described. FIG. 19 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 1902 made of a white light source such as a halogen lamp is provided inside the projector 1900. The projection light emitted from the lamp unit 1902 is separated into three primary colors of RGB by three mirrors 1906 and two dichroic mirrors 1908 disposed therein, and the light valves 100R, 100G corresponding to the primary colors and 100B, respectively. Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal panel 100 according to the above-described embodiment, and R, G, and B supplied from a processing circuit (not shown here) that inputs an image signal. The primary color signals are respectively driven. In addition, B light has a long optical path compared to other R colors and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 1921 including an incident lens 1922, a relay lens 1923, and an exit lens 1924. Led.
[0167]
The light modulated by the light valves 100R, 100G, and 100B is incident on the dichroic prism 1912 from three directions. In the dichroic prism 1912, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Accordingly, after the images of the respective colors are combined, a color image is projected onto the screen 1920 by the projection lens 1914.
[0168]
Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter as described above. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 1912, whereas the transmission image of the light valve 100G is projected as it is. The display image is horizontally reversed with respect to the display image by 100G.
[0169]
<Part 2: Mobile computer>
Next, an example in which the liquid crystal panel 100 described above is applied to a mobile personal computer will be described. FIG. 20 is a perspective view showing the configuration of this personal computer. In the figure, a computer 2000 includes a main body portion 2004 provided with a keyboard 2002 and a liquid crystal panel 100 used as a display portion. Note that a backlight unit (not shown) for improving visibility is provided on the back surface of the liquid crystal panel 100.
[0170]
<Part 3: Mobile phone>
Further, an example in which the above-described liquid crystal panel 100 is applied to a display unit of a mobile phone will be described. FIG. 21 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 2100 includes the liquid crystal panel 100 described above together with a plurality of operation buttons 2102, an earpiece 2104 and a mouthpiece 2106. Note that a backlight unit (not shown) for enhancing visibility is also provided on the back surface of the liquid crystal panel 100.
[0171]
In addition to the electronic devices described with reference to FIGS. 19 to 21, liquid crystal televisions, viewfinder type / direct monitor type video tape recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors , Workstations, videophones, POS terminals, digital still cameras, devices equipped with touch panels, and the like. Needless to say, the electro-optical device according to the embodiment or the application mode can be applied to these various electronic devices.
[0172]
【The invention's effect】
As described above, according to the present invention, the generation of so-called ghost is suppressed, and as a result, high-quality display is possible.
[Brief description of the drawings]
FIG. 1A is a perspective view illustrating an external configuration of an electro-optical device according to a first embodiment of the invention, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. .
FIG. 2 is a block diagram showing an electrical configuration of an element substrate in the electro-optical device.
FIG. 3 is a block diagram illustrating a configuration of a processing circuit in the electro-optical device.
FIG. 4 is a plan view showing wiring in a main part of an element substrate of the electro-optical device.
FIG. 5 is a timing chart for explaining the operation of the electro-optical device.
FIG. 6 is a timing chart for explaining the operation of the electro-optical device.
FIG. 7 is a timing chart for explaining an operation of canceling differential noise in the electro-optical device.
FIG. 8 is a diagram for explaining in detail a ghost actually generated on the display screen of the liquid crystal panel.
FIG. 9 is a diagram showing an electrical equivalent circuit for explaining a ghost generation mechanism in a liquid crystal panel.
FIG. 10 is a block diagram showing an electrical configuration of an element substrate of an electro-optical device according to a second embodiment of the invention.
FIG. 11 is a block diagram showing a configuration of a processing circuit in the electro-optical device.
FIG. 12 is a block diagram showing another configuration of a correction circuit in the processing circuit.
FIG. 13 is a diagram illustrating a voltage waveform of a scanning signal according to the different configuration.
FIG. 14 is a block diagram illustrating a configuration of a correction circuit in a processing circuit of an electro-optical device according to a third embodiment of the invention.
FIG. 15 is a timing chart for explaining the operation of the correction circuit;
FIG. 16 is a block diagram illustrating a configuration of a correction circuit in a processing circuit of an electro-optical device according to a fourth embodiment of the invention.
FIG. 17 is a block diagram illustrating a configuration of a processing circuit of an electro-optical device according to a fifth embodiment of the invention.
FIG. 18 is a block diagram illustrating a main configuration of a processing circuit of an electro-optical device according to a sixth embodiment of the invention.
FIG. 19 is a plan view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device according to the embodiment is applied.
FIG. 20 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device is applied.
FIG. 21 is a perspective view showing a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device is applied.
FIG. 22 is a voltage waveform diagram for explaining a decrease in display quality.
[Explanation of symbols]
100 ... Liquid crystal panel
101: Element substrate
102. Counter substrate
105 ... Liquid crystal
108 ... Counter substrate
112 ... Scanning line
114 ... data line
116 ... TFT
118: Pixel electrode
119 ... Storage capacity
120 ... peripheral circuit
130: Scanning line driving circuit
140: Data line driving circuit (sampling signal output circuit)
150 ... Sampling circuit
151. Sampling switch
160: Precharge circuit
161: Precharging switch
171: Image signal line
173 ... Correction signal line
175 ... Capacity line
177 ... Precharge control line
179 ... Precharge signal line
200: Processing circuit
218 ... Correction circuit
220 .. Inverting addition circuit
1900: Projector
2000 ... Personal computer
2100 ... Mobile phone

Claims (14)

A pixel electrode formed in the display area of the first substrate;
A data line for supplying an image signal to the pixel electrode;
A counter electrode facing the pixel electrode via an electro-optic material;
An image signal line formed on the first substrate for supplying an image signal to the pixel electrode;
A sampling circuit formed on the first substrate and sampling the image signal supplied to the image signal line and supplying the sampled signal to the data line;
A correction signal line that is arranged alongside the image signal line in the peripheral area of the display area and is opposed to the counter electrode, and is supplied with a correction signal for canceling the level fluctuation of the counter electrode;
An electro-optical device comprising: A pixel electrode formed in the display area of the first substrate;
A data line for supplying an image signal to the pixel electrode;
A counter electrode facing the pixel electrode via an electro-optic material;
An image signal line formed on the first substrate for supplying an image signal to the pixel electrode;
A sampling circuit formed on the first substrate and sampling the image signal supplied to the image signal line and supplying the sampled signal to the data line;
A correction signal that is arranged alongside the image signal line in the peripheral area of the display area and is opposed to the counter electrode, and is supplied with a correction signal that is inverted with respect to the image signal based on a predetermined potential. Lines and,
An electro-optical device comprising: A plurality of scanning lines formed on the first substrate;
A plurality of data lines formed on the first substrate and blocked for each one or a plurality of h (h is an integer of 2 or more);
One or h image signal lines formed on the first substrate and supplying image signals corresponding to one or h data lines constituting the block;
A sampling circuit that sequentially samples the image signals supplied to the one or h image signal lines for each one or h data lines belonging to a block and supplies the sampling signals to the data lines;
A pixel electrode provided corresponding to the intersection of the scanning line and the data line;
A counter electrode facing the pixel electrode via an electro-optic material;
A correction signal line that is arranged to face the counter electrode in a peripheral area of the display area in which the pixel electrodes are arranged in a matrix, and that is supplied with a correction signal for canceling the level fluctuation of the counter electrode;
An electro-optical device comprising: A plurality of scanning lines formed on the first substrate;
A plurality of data lines formed on the first substrate and blocked for each one or a plurality of h (h is an integer of 2 or more);
One or h image signal lines formed on the first substrate and supplying image signals corresponding to one or h data lines constituting the block;
A sampling circuit that sequentially samples the image signals supplied to the one or h image signal lines for each one or h data lines belonging to a block and supplies the sampling signals to the data lines;
A pixel electrode provided corresponding to each intersection of the scanning line and the data line;
A counter electrode facing the pixel electrode via an electro-optic material;
A correction signal line that is arranged to face the counter electrode in a peripheral area of the display area in which the pixel electrodes are arranged in a matrix, and that is supplied with a correction signal that is inverted with respect to the image signal based on a predetermined potential;
An electro-optical device comprising: 5. The correction signal line according to claim 3, wherein one or h correction signal lines are separately arranged corresponding to the one or h image signal lines on a one-to-one basis. Electro-optic device. The correction signal supplied to the one or h correction signal lines is a signal obtained by inverting an image signal supplied to a corresponding image signal line with a predetermined potential as a reference. 5. The electro-optical device according to 3 or 4.   7. The electro-optical device according to claim 1, wherein the correction signal line is arranged in a peripheral area of the display area so as to run along with the image signal line that supplies the image signal. . In the first substrate, a pixel electrode disposed corresponding to the intersection of the scanning line and the data line;
A counter electrode facing the pixel electrode via an electro-optic material,
An electro-optical device, wherein a correction signal for canceling the level fluctuation of the counter electrode is supplied to the scanning line during a period when the scanning signal is in an inactive level. In the first substrate, a pixel electrode disposed corresponding to the intersection of the scanning line and the data line;
A counter electrode facing the pixel electrode via an electro-optic material;
A storage capacitor provided for each pixel electrode, having one end connected to the corresponding pixel electrode and the other end commonly connected to the capacitor line;
An electro-optical device, wherein a correction signal for canceling a level fluctuation of the counter electrode is supplied to the capacitor line. In the first substrate, a pixel electrode disposed corresponding to the intersection of the scanning line and the data line;
A counter electrode facing the pixel electrode via an electro-optic material,
An electro-optical device, wherein a correction signal based on a value obtained by multiplying a total sum of changes in an image signal by a predetermined coefficient is supplied to the scanning line during a period in which the scanning signal is in an inactive level. In the first substrate, a pixel electrode disposed corresponding to the intersection of the scanning line and the data line;
A counter electrode facing the pixel electrode via an electro-optic material;
A precharge circuit for precharging the data line with a precharge voltage before supplying an image signal to the data line;
An electro-optical device, wherein a correction signal based on a value obtained by multiplying a sum of differences between the image signal and the precharge voltage by a predetermined coefficient is supplied to the scanning line during a period when the scanning signal is in an inactive level. In the first substrate, a pixel electrode disposed corresponding to the intersection of the scanning line and the data line;
A counter electrode facing the pixel electrode via an electro-optic material;
A storage capacitor provided for each pixel electrode, having one end connected to the corresponding pixel electrode and the other end commonly connected to the capacitor line;
An electro-optical device, wherein a correction signal based on a value obtained by multiplying a total sum of changes in image signals by a predetermined coefficient is supplied to the capacitor line. In the first substrate, a pixel electrode disposed corresponding to the intersection of the scanning line and the data line;
A counter electrode facing the pixel electrode via an electro-optic material;
A precharge circuit for precharging the data line with a precharge voltage before supplying an image signal to the data line;
A storage capacitor provided for each pixel electrode, having one end connected to the corresponding pixel electrode and the other end commonly connected to the capacitor line;
An electro-optical device, wherein a correction signal based on a value obtained by multiplying a sum of differences between the image signal and the precharge voltage by a predetermined coefficient is supplied to the capacitor line.   An electronic apparatus comprising the electro-optical device according to claim 1.

Images