JP4055767B2 - Image signal correction circuit, image signal correction method, electro-optical device, and electronic apparatus - Google Patents

Description

The present invention relates to an image signal correction circuit of an electro-optical device, an image signal correction method, an electro-optical device, and an electronic apparatus in which the electro-optical device is applied to a display unit.

In a display panel that performs display by optical change of an electro-optical material such as liquid crystal, the liquid crystal is sandwiched between a pair of substrates. This display panel can be classified into several types according to the driving method. For example, an active matrix type in which the pixel electrode is driven by a three-terminal switching element has the following configuration. Yes. That is, among a pair of substrates constituting this type of display panel, one substrate is provided so that a plurality of scanning lines and a plurality of data lines intersect with each other, and corresponds to each of these intersecting portions. A pair of a three-terminal switching element such as a thin film transistor and a pixel electrode is provided,
Further, peripheral circuits for driving each of the scanning lines and the data lines are provided around the area (display area) where these pixel electrodes are provided. The other substrate is provided with a transparent counter electrode (common electrode) facing the pixel electrode, and is maintained at a constant potential. In addition, each opposing surface of both substrates is provided with an alignment film that has been rubbed so that the long axis direction of the liquid crystal molecules is continuously twisted, for example, by about 90 degrees between the two substrates. A polarizer corresponding to the orientation direction is provided on the back side.

Here, the switching element provided at the intersection of the scanning line and the data line is turned on when the scanning signal applied to the scanning line becomes an active level, and the image signal sampled on the data line is applied to the pixel electrode. To do. For this reason, a voltage that is the difference between the potential of the counter electrode and the potential of the image signal is applied to the liquid crystal capacitor composed of the pixel electrode, the counter electrode, and the liquid crystal sandwiched between the two electrodes. Thereafter, even if the switching element is turned off, the applied voltage is held in the liquid crystal capacitor due to the capacitance of itself and the storage capacitor.

At this time, if the effective voltage value between the two electrodes is zero, the light passing between the pixel electrode and the counter electrode rotates about 90 degrees along the twist of the liquid crystal molecules, while the effective voltage value is large. As the liquid crystal molecules are tilted in the direction of the electric field, the optical rotation disappears. For this reason, for example, in the transmission type, when polarizers whose polarization axes are orthogonal to each other according to the alignment direction are arranged on the incident side and the back side (normally white mode), the voltage between both electrodes is effective. If the value is zero, light is transmitted and white is displayed (increasing the transmittance), while light is blocked as the effective voltage value is increased, and finally black (the transmittance is decreased). Display. Therefore, predetermined display is possible by controlling the voltage applied to the pixel electrode for each pixel.

By the way, this display panel has a problem that display quality is deteriorated due to so-called lateral crosstalk. Here, the horizontal crosstalk is, for example, in the normally white mode, as shown in FIG. 21, when a rectangular black region is displayed in a window with a gray background, the right side (the side in the horizontal scanning direction) The gray area in) gradually returns to the original gray after it becomes lighter than the original gray (in some cases after dark). In FIG. 21, the gradation is indicated by the hatched line density.
This type of lateral crosstalk can be eliminated to some extent by a technique of adding the potential fluctuation of the counter electrode to the image signal supplied to the pixel electrode (see, for example, Patent Document 1).
JP 2002-116735 A (see FIG. 4).

However, although the occurrence of the above-mentioned type of lateral crosstalk can be suppressed to some extent, another type of lateral crosstalk has now occurred. This horizontal crosstalk is
As shown in FIG. 22, when a black area is displayed in a window with a gray background, the gray area of the background is an area adjacent to the black area in the left-right direction, and is perpendicular to the black area. The area shifted by one line is brightened.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide an image signal correction circuit for an electro-optical device capable of high-quality display while suppressing the occurrence of this new lateral crosstalk, An image signal correcting method, an electro-optical device, and an electronic apparatus in which the electro-optical device is applied to a display unit.

In order to achieve the above object, an image signal correction circuit of an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality provided at intersections of the scanning lines and the data lines. Switching elements, a plurality of pixel electrodes provided corresponding to the switching elements, and a counter electrode opposed to the pixel electrode through an electro-optic material, and setting each data line to a predetermined voltage An image signal correction circuit that corrects and supplies the image signal to a display panel that applies an image signal to the pixel electrode located on the selected scanning line after the pre-charge via the data line. A subtractor for obtaining a difference between a tone and a gradation of a pixel indicated by the image signal; an integrator for integrating a subtraction output by the subtractor for one row of pixels located on a selected scanning line; The integrator The integrated output by, and then added to the pixel one line image signal which is located to the scanning line to be selected, and having an adder for supplying the corrected image signal. If the precharge period is not sufficiently secured, the precharge cannot be sufficiently performed, and the precharge voltage applied to each data line is different. For this reason, even if the voltage of the image signal is the same, if the video signal of the previous row is different, the precharge voltage of the next row is different and the voltage actually written to the pixel electrode is also different. On the other hand, according to the present invention, the accumulated value of the difference from the reference gradation is obtained for one row, and the accumulated value is added as a correction value to the image signal of the next row. Thus, it is possible to perform correction so that the voltages applied to the pixel electrodes are uniform.

Here, in the present invention, it is preferable that the reference gradation corresponds to gray in a pixel. This is because the deterioration in display quality is likely to occur in a gray display area where the gradation change rate is large with respect to the effective voltage value, and therefore, when gray is selected as the reference gradation, the comparison works effectively.
In the present invention, a configuration may further include a first multiplier that multiplies the integration output of the integrator by a first coefficient.
On the other hand, in the so-called dot-sequential type, the degree of influence due to the precharge voltage gradually changes from one end side to the other end side in the direction along the scanning line.
It is also preferable to further include a circuit for gradually attenuating or increasing the integration output by the integrator as the pixel located at the next selected scanning line is horizontally scanned from one end side to the other end side.
As a configuration for this, the circuit for attenuating or increasing may be a second multiplier that multiplies the integral output by a second coefficient. Here, as a configuration for outputting the second coefficient, for example, a counter that performs counting according to the horizontal scanning from the start of horizontal scanning, and a conversion table that converts the counting result of the counter into the second coefficient. A counter that counts according to the horizontal scan from the start of horizontal scanning, a storage unit that stores a plurality of representative values of the second coefficient, and a representative value stored in the storage unit And a configuration including an interpolation unit that interpolates a second coefficient corresponding to the counting result of the counter.

Further, in the present invention, not only the image signal correction circuit of the electro-optical device but also an image signal correction method of the electro-optical device can be conceptualized as an electro-optical device itself.
When considered as an electro-optical device, the display panel has an even number of regions divided along the horizontal scanning direction, and each region is a pixel region including two or more adjacent scanning lines. The scanning line driving circuit selects a scanning line belonging to one region among the regions, and then selects a scanning line belonging to another region, and the image signal correction circuit includes the scanning line belonging to one region. In the period in which the image signal is supplied to the counter electrode at a higher voltage, the image signal is supplied to the counter electrode at a voltage lower than the counter electrode. It may be configured to supply a signal.
In this configuration, it is preferable that the number of scanning lines included in each region is the same .
In this configuration, the image signal correction circuit preferably includes a frame memory that temporarily stores the image signal, sequentially reads out the image signal corresponding to the selected scanning line, and supplies the image signal to the subtracter.
Further, in the electro-optical device, in consideration of the difference in influence due to the precharge voltage, the integration output by the integrator is horizontally shifted from one end side to the other end side. As a configuration further including, or a configuration for, a circuit that gradually attenuates or increases as it is scanned, the circuit that attenuates or increases may be a second multiplier that multiplies the integrated output by a second coefficient. Here, the same applies to the example of the configuration for outputting the second coefficient.
In addition, since the electronic apparatus according to the present invention includes the electro-optical device as a display unit, occurrence of lateral crosstalk can be suppressed.

Before describing an image signal correction circuit according to an embodiment of the present invention, an electro-optical device to which the image signal correction circuit is applied will be described. Here, the reason for describing the electro-optical device is that the image signal correction circuit is closely related to the driving of the electro-optical device, and it is difficult to explain the image signal correcting circuit without understanding the driving. is there.

<First Embodiment>
FIG. 1 is a block diagram showing the overall configuration of the electro-optical device according to the first embodiment of the invention. This electro-optical device performs predetermined display using liquid crystal as an electro-optical material,
As shown in FIG. 1, the display panel 100, the control circuit 200, and the image signal processing circuit 30
0 is included. Among these, the control circuit 200 generates a timing signal, a clock signal, and the like for controlling each unit in accordance with a vertical scanning signal Vs, a horizontal scanning signal Hs, and a dot clock signal DCLK supplied from a host device (not shown).

The image signal processing circuit 300 further includes an image signal correction circuit 302, a D / A converter 304,
An S / P conversion circuit 306 and an amplification / inversion circuit 308 are included.
Among these, the image signal correction circuit 302 receives a digital image signal VID supplied in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK (that is, according to vertical scanning and horizontal scanning), which will be described later. To correct the image signal VID
This is output as a. Details of the image signal correction circuit 302 will be described later.
The D / A converter 304 converts the corrected image signal VIDa into an analog image signal. In addition, when an analog image signal is input, the S / P conversion circuit 306 distributes the analog image signal to N (N = 6 in the figure) system and expands it N times (serial-parallel conversion) on the time axis. Output. The reason for serial-parallel conversion of the image signal is to secure a sample and hold time and charge / discharge time by increasing the time during which the image signal is applied in a sampling switch 151 (see FIG. 3) described later. is there. The amplifying / inverting circuit 308 inverts the serial-parallel converted image signal that requires polarity inversion, and then amplifies it appropriately and supplies it to the display panel 100 as the image signals VID1 to VID6. It is. Here, regarding polarity inversion, (1) every scanning line, (
There are various modes such as 2) every data signal line, (3) every pixel, etc. In this first embodiment, for convenience of explanation, (1) the case of polarity inversion in units of scanning lines is shown. Let's take an example.

The polarity reversal in the present embodiment refers to reversing the voltage level alternately with reference to a predetermined constant voltage Vc (the amplitude center potential of the image signal, which is substantially equal to the voltage LCcom applied to the counter electrode). Say. Writing in which a higher voltage than the voltage Vc is applied to the pixel electrode is referred to as positive polarity writing, and writing in which a lower voltage than the voltage Vc is applied to the pixel electrode is referred to as negative polarity writing.
In this embodiment, the image signal VIDa corrected by the image signal correction circuit 302 is also used.
However, it is needless to say that analog conversion may be performed after serial-parallel conversion or after amplification / inversion. Further, the converted image signals VID1 to VID
The supply timing to the display panel 100 of 6 is the same in the present embodiment, but may be sequentially shifted in synchronization with the dot clock. In this case, N-system image signals are sequentially supplied by a sampling circuit described later. It becomes the structure which samples.

Next, the structure of the display panel 100 will be described. FIG. 2A shows the display panel 10.
FIG. 2B is a cross-sectional view taken along the line AA ′ in FIG.
As shown in these drawings, in the display panel 100, an element substrate 101 on which various elements, pixel electrodes 118 and the like are formed, and a counter substrate 102 on which the counter electrode 108 and the like are provided have spacers (not shown). The sealing material 104 included is bonded so that the electrode forming surfaces face each other while maintaining a certain gap, and in this gap, for example, TN (Twisted Nematic)
A type liquid crystal 105 is enclosed. In this embodiment, glass, semiconductor, quartz, or the like is used for the element substrate 101, but an opaque substrate may be used. However, when an opaque substrate is used as the element substrate 101, it is necessary to use a reflective type instead of a transmissive type. Further, the sealant 104 is formed along the periphery of the counter substrate 102, but a part of the sealant 104 is opened to enclose the liquid crystal 105. For this reason, after the liquid crystal 105 is sealed,
The opening is sealed with a sealing material 106.

Next, the data line driving circuit 140 is formed in a region 140a on the outer side of the sealing material 104 on the opposite surface of the element substrate 101, and the sampling circuit 150 is formed in the inner region 150a. ing. On the other hand, there are a plurality of mounting terminals 1 on the outer peripheral portion of this side.
07 is formed, and various signals are input from the control circuit 200, the image processing circuit 300, and the like. In addition, a scanning line driving circuit 130 is formed in each of the two side regions 130a adjacent to the one side, and the scanning line is driven from both sides. Note that if the delay of the scanning signal supplied to the scanning line is not a problem, the scanning line driving circuit 130 may be formed on only one side. Further, in the remaining one side area 160a, wiring (not shown) shared by the two scanning line driving circuits 130, a precharge circuit 1 described later, and so on.
60 and the like are formed.

On the other hand, the counter electrode 108 provided on the counter substrate 102 is mounted on the element substrate 101 by a conductive material such as silver paste provided at at least one of the four corners in the bonding portion with the element substrate 101. A constant voltage LCcom is applied by being electrically connected to the terminal 107.
Note that the counter substrate 102 is not particularly illustrated, but in a region facing the pixel electrode 118,
A colored layer (color filter) is provided as necessary. However, it is not necessary to form a colored layer on the counter substrate 102 when applied to a color light modulation application as in a projector described later.
Regardless of whether or not a colored layer is provided, a light shielding film is provided in a portion other than the region facing the pixel electrode 118 in order to prevent a decrease in contrast ratio due to light leakage (not shown). .
Further, on the opposing surfaces of the element substrate 101 and the counter substrate 102, an alignment film that is rubbed so that the major axis direction of molecules in the liquid crystal 105 is continuously twisted by about 90 degrees between the two substrates is provided. A polarizer corresponding to the orientation direction is provided on each back side, but since it is not directly related to the present case, the illustration thereof will be omitted. In FIG. 2B, the counter electrode 108, the pixel electrode 118, the mounting terminal 107, and the like have a thickness, but this is a convenient measure for indicating the positional relationship. Is sufficiently thin to be negligible with respect to the thickness of the substrate.

Next, an electrical configuration of the element substrate 101 in the display panel 100 will be described. FIG. 3 is a block diagram illustrating a configuration of the element substrate 101.
As shown in this figure, in the display area of the element substrate 101, a plurality of scanning lines 11 are provided.
2 are formed substantially parallel to each other along the row (X) direction, and a plurality of data lines 114 are formed substantially parallel to each other along the column (Y) direction. These scanning lines 112
A thin film transistor (hereinafter referred to as “TFT”) 11 serving as a switching element for switching a pixel at a portion where the data line 114 and the data line 114 intersect.
6 is connected to the scanning line 112, the source of the TFT 116 is connected to the data line 114, and the drain of the TFT 116 is connected to the rectangular transparent pixel electrode 118.

As described above, in the display panel 100, the liquid crystal 105 is sandwiched between the electrode formation surfaces of the element substrate 101 and the counter substrate 102.
18, a counter electrode 108, and a liquid crystal 105 sandwiched between the two electrodes. Here, for convenience of explanation, if the total number of scanning lines 112 is “m” and the total number of data lines 114 is “6n” (m and n are integers), the pixels are the same as the scanning lines 112. Corresponding to each intersection with the data line 114, it is arranged in a matrix of m rows × 6n columns.
In addition, a storage capacitor 119 for reducing leakage of the liquid crystal capacitor via the TFT 116 is formed for each pixel in the display region composed of matrix pixels. One end of the storage capacitor 119 is connected to the pixel electrode 118 (the drain of the TFT 116), and the other end is commonly connected by a capacitor line 175. In this embodiment, the capacitor line 175 is maintained at a constant potential (for example, the voltage LCcom, the higher power supply voltage of the drive circuit, the lower power supply voltage, etc.) via the mounting terminal 107.

On the other hand, a peripheral circuit 120 is formed in the non-display area of the element substrate 101. The peripheral circuit 120 includes a scanning line driving circuit 130, a data line driving circuit 140, a sampling circuit 1
50. In addition to the precharge circuit 160, it is conceptualized as a circuit including an inspection circuit for determining the presence / absence of a defect after manufacturing. However, the inspection circuit is not directly related to the present case, so the description thereof Will be omitted.
Note that the constituent elements of the peripheral circuit 120 are formed by a manufacturing process common to the TFT 116 for driving the pixels. In this way, when the peripheral circuit 120 is built in the element substrate 101 and the constituent elements are formed by a common process, the peripheral circuit 120 is formed on a separate substrate and compared with a type in which the peripheral circuit 120 is externally attached. This is advantageous for downsizing and cost reduction.

Of the peripheral circuits 120, the scanning line driving circuit 130 applies scanning signals G1, G2,..., Gm that become active (H) level for one horizontal effective display period as shown in FIG.
The signals are output over one vertical effective display period in order every horizontal scanning period (1H).
The details of the scanning line driving circuit 130 are omitted because they are not directly related to the present invention, but the transfer start pulse DY supplied at the beginning of one vertical scanning period is sequentially changed every time the level of the clock signal CLY changes. After shifting, waveform shaping or the like is performed, and scanning signals G1, G2,.
Is generated.
Further, the data line driving circuit 140 sequentially receives the sampling signal S1 that becomes an active level.
, S2,..., Sn are output within one horizontal effective display period. Although this detail is not directly related to the present invention and is not shown in the figure, it is composed of a shift register and a plurality of logical product circuits. Of these, the shift register is one horizontal effective display as shown in FIG. The transfer start pulse DX supplied at the beginning of the period is sequentially shifted each time the level of the clock signal CLX transitions, and is output as signals S1 ′, S2 ′, S3 ′,. Are output as sampling signals S1, S2, S3,..., Sn with the pulse widths of the signals S1 ′, S2 ′, S3 ′,. To do.

The sampling circuit 150 receives the image signal VI supplied through the six image signal lines 171.
D1 to VID6 are sampled on the respective data lines 114 in accordance with the sampling signals S1, S2, S3,..., Sn, and are composed of sampling switches 151 provided for each data line 114.
Here, the data lines 114 are divided into blocks every six lines, and among the six data lines 114 belonging to the i-th block counted from the left in FIG.
4 is configured to sample the image signal VID1 supplied via the image signal line 171 during a period in which the sampling signal Si is active, and supply the sampled signal to the data line 114. ing. Note that i is a generalized description without specifying a data line, and is an integer satisfying 1 ≦ i ≦ n.
Similarly, the sampling switch 151 connected to one end of the second data line 114 among the six data lines 114 belonging to the i-th block is connected to the image signal VID2.
Are sampled during a period in which the sampling signal Si is active and supplied to the data line 114. Similarly, each of the sampling switches 151 connected to one end of the third, fourth, fifth, and sixth data lines 114 of the six data lines 114 belonging to the i-th block is connected to the image signal VID3. , VID4, VID5, V
Each of ID6 is sampled during a period when the sampling signal Si is at an active level, and is supplied to the corresponding data line 114.
In the present embodiment, the TFT constituting the sampling switch 151 is N
Since it is a channel type, when the sampling signals S1, S2,..., Sn become H level, the corresponding sampling switch 151 is turned on. Note that the TFT constituting the sampling switch 151 may be a P-channel type or a complementary type combining both channels.

On the other hand, a precharge circuit 160 is provided in a region opposite to the data line driving circuit 140 with respect to the display region. The precharge circuit 160 includes a precharging switch 161 provided for each data line 114, and each precharging switch 161 has an active precharge control signal PG supplied via a precharge control line 177 ( H
), The precharge voltage PS supplied via the precharge signal line 179 is precharged to the data line 114.
As shown in FIG. 5, the precharge control signal PG becomes an active level in a blanking period obtained by removing one horizontal effective display period from one horizontal scanning period in a period isolated from the temporal front and rear ends. Signal. Further, as shown in the figure, the precharge voltage PS is a signal whose level is inverted by, for example, the voltages Vg + and Vg− with respect to the voltage Vc every horizontal scanning period, and is positive in the horizontal effective display period. If the negative writing is performed, the voltage Vg + is taken in the immediately preceding blanking period. If the negative writing is performed, the voltage Vg- is taken in the immediately preceding blanking period.

Here, the voltage Vc is the amplitude center potential of the image signals VID <b> 1 to VID <b> 6 as described above, and is substantially equal to the voltage LCcom applied to the counter electrode 108. Also, voltage Vg +
, Vg− are voltages higher and lower than the voltage Vc, respectively, and are voltages corresponding to gray. Note that the precharge voltage PS is not limited to a voltage corresponding to gray.
Further, the voltages Vb + and Vb− are voltages when black display is performed in positive polarity writing and negative polarity writing, respectively, in the case where the present embodiment is a normally white mode in which white display is performed with no voltage applied. It is.
According to the precharge circuit 160 having such a configuration, the sampling signals S1, S2
, S3,..., Sn in the blanking period immediately before the horizontal effective display period, each data line 114 is precharged in advance to the voltage Vg + or Vg−. The load when the image signals VID1 to VID6 are sampled on the data line 114 should be reduced.
In FIG. 3, only one scanning line driving circuit 130 is arranged on one end side of the scanning line 112. However, this is a measure for the sake of convenience for explaining the electrical configuration. 2 are arranged at both ends of the scanning line 112, as shown in FIG.

Next, the operation of the electro-optical device will be described by taking as an example a case where the image signal VID is not directly corrected by the image signal correction circuit 302 but is directly supplied to the D / A converter 304.
First, the transfer start pulse DY is supplied to the scanning line driving circuit 130 at the beginning of one vertical scanning period. By this supply, as shown in FIG. 4, the scanning signals G1, G2, G3,..., Gm are sequentially and exclusively set to the active level and output to the scanning lines 112, respectively.
First, attention is focused on one horizontal effective display period in which the scanning signal G1 is at an active level. Note that in this one horizontal effective display period, for the sake of convenience of description, assuming that positive writing is performed, the image signals VID1 to VID6 output from the amplification / inversion circuit 308 (see FIG. 1) are:
The voltage LCcom (strictly speaking, the voltage Vc) applied to the counter electrode 108 is higher and becomes higher as the color becomes black.
On the other hand, in the blanking period preceding the horizontal effective display period, as shown in FIG. 5, the precharge control signal PG becomes an active level in a period isolated from the front and rear ends of the blanking period. At this time, the precharge voltage PS becomes the voltage Vg + corresponding to the positive polarity writing. For this reason, all the data lines 114 are precharged to the voltage Vg + during the period.

Next, when the blanking period ends and the horizontal effective display period starts and the scanning signal G1 becomes the active level, the transfer start pulse DX is first driven as shown in FIG. 4 or FIG. This is supplied to the circuit 140. Thereby, the sampling signals S1, S2, S3,..., S narrowed in the period SMPa so that the pulse widths of adjacent ones do not overlap each other.
n is output in order.

When the image signal VID is not corrected by the image signal correction circuit 302, the image signal VID is first converted to D /
A signal is converted to an analog signal by the A conversion circuit 304, and secondly, it is distributed to the image signals VID1 to VID6 by the S / P conversion circuit 306, and is expanded six times with respect to the time axis. The signal is appropriately amplified and inverted by the inverting circuit 308 and supplied to the display panel 100.
When the scanning signal G1 is in the active level and the sampling signal S1 is in the active level, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to the first block from the left, respectively. The sampled image signals VID <b> 1 to VID <b> 6 are respectively corresponding to the corresponding pixel electrode 1 by the TFT 116 of the pixel intersecting with the first scanning line 112 and the six data lines 114 counted from the top in FIG. 3.
18 is applied.
Thereafter, when the sampling signal S2 becomes an active level, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to the second block, respectively, and these image signals VID1 to VID6 are 1 The corresponding pixel electrodes 11 are respectively formed by the TFTs 116 of the pixels intersecting the sixth scanning line 112 and the six data lines 114.
8 is applied.

Similarly, when the sampling signals S3, S4,..., Sn are sequentially set to the active level, the image signal VID1 is applied to each of the six data lines 114 belonging to the third, fourth,. ~ VID6 is sampled and these image signals VID1 ~ VID1 ~
VID6 is the TF of the pixel that intersects the first scanning line 112 and the six data lines 114.
By T116, it is applied to the corresponding pixel electrode 118, respectively. As a result, writing to all the pixels in the first row is completed.

Next, a period during which the scanning signal G2 is active will be described. In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, in this one horizontal scanning period,
Negative polarity writing is performed. Therefore, the image signals VID1 to VID6 output from the amplifying / inverting circuit 308 are on the lower side with respect to the voltage LCcom applied to the counter electrode 108, and become lower as the color becomes black. Prior to this, since the precharge voltage PS in the blanking period becomes the voltage Vg− corresponding to the negative polarity writing, when the precharge control signal PG becomes the active level, all the data lines 114 have the voltage It will be precharged to Vg-.

Other operations are the same, and the sampling signals S1, S2, S3,..., Sn are sequentially set to the active level, and writing to all the pixels in the second row is completed. Similarly, the scanning signals G3, G4,..., Gm become active, and writing is performed on the pixels in the third row, fourth row,. This
While the positive polarity writing is performed for the pixels in the odd-numbered rows, the negative polarity writing is performed for the pixels in the even-numbered rows, and in the first vertical scanning period, the first to m-th rows are performed. Writing will be completed across all of the pixels.
In the next one vertical scanning period, similar writing is performed. At this time, the writing polarity for the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows. In this way, since the writing polarity for the pixels is switched every vertical scanning period, a direct current component is not applied to the liquid crystal 105, and deterioration of the liquid crystal 105 is prevented.

However, as described above, when such a display panel 100 displays a black region with a gray background as a window, horizontal crosstalk as shown in FIG. 22 occurs. Here, paying attention to the fact that the bright gray area is shifted by one line with respect to the black area, the writing of the bright gray area is affected by the writing of the line including the black area, which is the immediately preceding line. You can imagine to some extent what you will be receiving. For this reason, the inventor of the present application displays various patterns, and from the relationship of the degree of brightness difference that occurs, the cause of the lateral crosstalk targeted in the present invention is a description of the precharge voltage that is executed during the blanking period. It was almost specified that it was insufficient.

Therefore, the point of insufficient writing of the precharge voltage will be described in detail.
In FIG. 22, the display area is divided into three row ranges A, B, and C in the direction along the horizontal scanning direction, and divided into three column ranges D, E, and F in the direction along the vertical scanning direction. In this example, the region of the row range B and the column range E displays a black window.
In FIG. 22, when the scanning line 112 belonging to the row range A or C is selected (when only the gray area not including the black area is horizontally scanned), the image signal VIDi (supplied to a certain image signal line 171 ( As shown in FIG. 6A, one of VID1 to VID6 is one of the voltages Vg + and Vg− corresponding to gray over one horizontal effective display period. This means that, for example, in one horizontal effective display period in which positive polarity writing is performed, the voltage Vg + is sampled on all the data lines 114 when the corresponding sampling switch 151 is turned on. Further, since a certain amount of capacitance is parasitic on the data line 114, even if the corresponding sampling switch 151 is turned off, the voltage Vg + of the image signal sampled at the time of turning on is maintained. That is, immediately before the precharge, all the data lines 114 are at the voltage Vg +.
After the positive polarity writing, the negative polarity writing is performed, but the precharge is executed immediately before that as described above. Therefore, immediately before the negative polarity writing, all the data lines 114 are precharged from the voltage Vg + to the voltage Vg− corresponding to the negative polarity writing.

On the other hand, when the scanning line 112 belonging to the row range B in FIG. 22 is selected (when the region including the black region is horizontally scanned), the image signal VIDi supplied to a certain image signal line 171 is selected.
6B, during horizontal scanning of the data line 114 belonging to the column range D or F, the voltage Vg + (or Vg−) corresponding to gray is obtained, and the data line 1 belonging to the column range E
During horizontal scanning of 14, the voltage Vb + (or Vb−) corresponding to black is obtained. This means
For example, in one horizontal effective display period in which positive polarity writing is performed, the voltage Vg + is sampled on the data line 114 belonging to the column ranges D and F, and the voltage Vb + is sampled on the data line 114 belonging to the column range E. This means that the sampling switch 151 is maintained even when the sampling switch 151 is turned off. That is, immediately before the precharge, the data line 114 belonging to the column ranges D and F is at the voltage Vg +, but the data line 114 belonging to the column range E is at the voltage Vb + higher than the voltage Vg +.

Therefore, immediately after selecting the scanning line 112 belonging to the row range B, in order to precharge all the data lines 114 to the voltage Vg−, the scanning line 11 belonging to the row range A or C is used.
Compared with the case immediately after 2 is selected, it can be seen that a long period is required because the charge / discharge amount is large.
In recent display panels, the number of pixels is increased and high-speed driving is required. Therefore, it is not possible to secure a sufficient time for precharging. Accordingly, the voltage actually precharged to the data line 114 is greater after the scanning line 112 belonging to the row range B is selected than after the scanning line 112 belonging to the row range A or C is selected. As shown in FIG.
It becomes higher by ΔV (in the case of precharge immediately after the positive polarity writing and immediately before the negative polarity writing).
Immediately before the negative polarity writing, when the data line 114 is at the voltage Vb− and when it is higher than the voltage ΔV, even if the same gray voltage Vg− is sampled on the data line 114, the data line 114 is finally The voltage written to the pixel electrode 118 is higher in the latter case. For this reason, the latter has a smaller effective voltage value of the liquid crystal capacitance. That is, the effective voltage value of the liquid crystal capacitance written in the horizontal scanning period subsequent to the horizontal scanning period in which the scanning line 112 belonging to the row range B is selected is the value of the horizontal scanning period in which the scanning line 112 belonging to the row range A or C is selected. Even if it is the same gray, it becomes smaller than the voltage effective value of the liquid crystal capacitance written in the next horizontal scanning period.
This is considered to be visually recognized as a brightness difference.

Immediately after the negative polarity writing and immediately before the positive polarity writing, the voltage fluctuation direction is reversed, but the voltage effective value does not change. Also, in the black region other than gray, the voltage effective value is considered to be small for the same reason,
In the black area, the brightness difference is hardly visible. The reason is that in the liquid crystal device, the transmittance characteristic (VT characteristic) with respect to the effective voltage value is duller in the vicinity of white or black than in the vicinity of gray, so even if there is a slight difference in the effective voltage value, the lightness This is because the difference is hardly visible.
Here, if lateral crosstalk occurs due to insufficient writing of precharge, a measure that such precharge is not required can be considered. However, in today's display panels, the number of pixels is extremely large, and it is in a situation where a sufficient writing time to the pixel electrode cannot be secured. For this reason, if the data line 114 is not precharged, the data line 1 can be obtained within a short time.
14 when the image signal cannot be sampled and when the image signal is written to the pixel electrode through the data line in a state where the voltages remaining on the data line are different from each other, the display quality is higher than the horizontal crosstalk. A decrease occurs. Therefore, the policy of not performing precharge cannot be easily adopted.

As described above, the effective voltage value written in the liquid crystal capacitor by performing horizontal scanning in a certain horizontal scanning period varies depending on the voltage precharged to the data line 114 immediately before, and further, the data line. The voltage precharged to all 114 depends on the gradation content of one row of pixels that are horizontally scanned immediately before. In other words, the gradation content of one row of pixels that are horizontally scanned in one horizontal scanning period is the same as the effective voltage value of the pixels of one row that are horizontally scanned in the next one horizontal scanning period. It means to change by degree.
Therefore, a voltage determined by the gradation content of the pixels for the immediately preceding row is added to the image signal supplied when the pixels for one row are horizontally scanned in a certain horizontal scanning period in anticipation of insufficient writing of the precharge voltage. Thus, it is considered that the original effective voltage value can be applied to the liquid crystal capacitor by superimposing in advance in the direction to cancel the fluctuation. The configuration for this is the image signal correction circuit 302. Therefore, the image signal correction circuit 302 will be described below.

FIG. 7 is a block diagram showing a configuration of the image signal correction circuit 302.
In this figure, a subtractor 312 subtracts the reference signal Ref from the digital image signal VID and outputs the subtraction result Def. As described above, the fluctuation amount of the precharge voltage is determined by the gradation contents of one row of pixels that are horizontally scanned immediately before, but in order to specify the gradation change, it is necessary to determine the gradation reference in advance. is there. The reference signal Ref is used to determine this gradation reference.
The integrator 314 is supplied with the signal HR which becomes H level only during the horizontal effective display period from the control circuit 200, resets the integration result at the rising edge of the signal HR, and then outputs the signal HR.
The subtraction result Def is integrated only during the period when is at the H level, and the integration result Int is output.
The latch circuit 316 latches the integration result Int at the timing when the image signal VID corresponding to the final n columns of pixels is output, and outputs the result as the signal L1. The multiplier 318 receives the signal L
1 is multiplied by a coefficient k1. The latch circuit 320 latches the multiplication result by the multiplier 318 and holds it as correction data Er for the next horizontal effective display period. The adder 322 adds the correction data Er to the image signal VID, and outputs the corrected image signal VIDa.

The operation of the image signal correction circuit 302 will be described with reference to the timing chart of FIG. First, in one horizontal effective display period, a digital image signal VID is supplied according to horizontal scanning. Here, a pixel 1 that is horizontally scanned in one horizontal effective display period.
The correction data Er obtained in the previous one horizontal effective display period is added to the image signal VID for the row, and the corrected image signal VIDa is output.
On the other hand, regarding the calculation of the correction data Er obtained in one horizontal effective display period, the subtraction result Def between the image data VID and the reference signal Ref is calculated by one line for each pixel by the subtractor 312 and then subtracted. The integration result Int of the result Def is integrated by the integrator 314. Therefore, the signal L1 latched by the latch circuit 316 uses the subtraction result Def indicating the difference between the gray level of the pixel that is horizontally scanned in the one horizontal effective display period and the gray level reference of the reference signal Ref as the pixel 1. The accumulated value for the line. The signal L1 multiplied by the coefficient k1 becomes the correction data Er. Further, the correction data Er is added to the image signal VID for one row of pixels that are horizontally scanned in the next one horizontal effective display period, respectively. The corrected image signal VIDa is supplied to the D / A converter 304.
Therefore, the image signal VID for one row of pixels scanned horizontally in a certain horizontal scanning period.
In this case, the correction data Er determined by the gradation content of the pixels for the immediately preceding row is preliminarily added as the correction data Er with a component that cancels the fluctuation.
The original effective voltage value is applied to the liquid crystal capacitance.
For example, in FIG. 22, when the scanning line 112 belonging to the row range A or C is selected, the pixels that are horizontally scanned are all gray, whereas when the scanning line belonging to the row range B is selected. In the case of the horizontally scanned pixels, the black in the column range E is added to the gray in the column range D or F. Therefore, the integration result Int obtained by accumulating the difference of the reference gradation indicated by the reference signal Ref for one row is the latter case. Is bigger. Since the result obtained by multiplying the integration result Int by the coefficient k1 is added to the image data for one row of pixels to be horizontally scanned next, the brightened portion is corrected in the darkening direction. Can be eliminated.

Note that, in the horizontal effective display period in which a certain scanning line 112 is selected as in the present embodiment, when six data lines 114 are grouped together and the image signal is sampled in order, the first one in the horizontal effective display period. Since the elapsed time from the end of the precharge is different from the last one, it can be considered that the fluctuation of the precharge voltage is different.
Therefore, as shown in FIG. 9, a multiplier 324 that multiplies the correction data Er by a coefficient k2 may be interposed between the latch circuit 320 and the adder 322. Where the coefficient k
2 is set so as to decrease, for example, linearly from the start to the end of one horizontal effective display period, as indicated by the characteristic A in FIG.
With this setting, the correction amount is large at the start of one horizontal effective display period, and the correction amount decreases with time. Therefore, it is possible to consider the influence of the difference in elapsed time from precharge. Become.
Here, for convenience of explanation, the coefficient k2 is assumed to have a characteristic A that linearly decreases with the passage of time. However, in consideration of the discharge characteristics of the precharge voltage, the characteristic B that has a decreasing rate that decreases with the passage of time. However, depending on the precharge voltage setting,
A characteristic C in which the decrease rate increases with time can also be considered.
Furthermore, as to the coefficient k2, as shown by the characteristic D in FIG. 11A, depending on whether or not the mode is a normally white mode, the voltage corresponding to what gradation the precharge voltage is set, etc. It can be considered that the characteristic D increases linearly with the passage of time, or the characteristic E or F where the increase rate increases or decreases with the passage of time is assumed.

In this way, in order to change the coefficient k2 from the start to the end of one horizontal effective display period, for example, a configuration as shown in FIG.
In this figure, a counter 332 counts up the count result HN (data indicating) at the rising and falling double edges of the clock signal CLX and resets the count result HN with the transfer start pulse DX. As described above, the transfer start pulse DX is supplied at the beginning of one horizontal effective display period, and the signal S1 ′ which is the basis of the sampling signals S1, S2, S3,..., Sn at the rising or falling edge of the clock signal CLX. , S2 ′, S3 ′,..., Sn ′ are output so as to sequentially become H level,
The counting result HN indicates the elapsed time in one horizontal effective display period in the form of what number block is selected. Therefore, the counting result HN is 1 to n, 1
If the first block is selected, that is, the start time in one horizontal effective display period, and if n, the last nth block is selected, that is, the end in one horizontal effective display period Will show the time.
The conversion table 334 converts the count result HN into a coefficient k2 according to any of the characteristics described above.
It is to convert to.
According to such a configuration, the coefficient k2 can be output while changing from the start to the end of one horizontal effective display period.

Further, in order to change the coefficient k2 from the start to the end of one horizontal effective display period, a configuration as shown in FIG.
In the configuration shown in this figure, the conversion table 334 shown in FIG.
6 and the interpolation unit 338.
Among these, the memory | storage part 336 memorize | stores the representative value of several points among the characteristics of the coefficient k2 with the count result. For example, when the coefficient k2 is set to the characteristic B in FIG.
In the storage unit 336, for example, as shown in FIG. 11B, the coefficient result HN is 1, Hb,
Only representative values ka, kb, kc, kd respectively corresponding to the points Hc, n are stored.

The interpolation unit 338 stores the coefficient k2 corresponding to the counting result Hc by the counter 332 in the storage unit 33.
6 is obtained by interpolation from the representative values ka, kb, kc, kd stored in FIG. For example,
If the counting result HN is 1 <HN <Hb, {ka− (ka−kb) · (HN−1) / (H
b-1)}, the coefficient k2 is obtained by internally dividing ka and kb according to the position of the counting result HN.
In addition to the internal interpolation, various interpolation methods such as external interpolation and function approximation can be applied as the interpolation method.
According to such a configuration, the storage unit 336 does not need to store the coefficient k2 over the entire area from the start to the end of one horizontal effective display period, and only stores a representative value. Is less.
Although the case where the coefficient k2 is the characteristic B has been described here, any of the characteristics described above may be used.

In the embodiment, the vertical scanning direction is G1 → Gm, and the horizontal scanning direction is S1 → Gm.
Although it was the direction of Sn, when it is set as the projector mentioned later or a rotatable display panel,
It is necessary to reverse the scanning direction. However, since the image signal VID is supplied in synchronization with the vertical scanning and the horizontal scanning, the image signal processing circuit 30 including the image signal correction circuit 302 is provided.
There is no need to change the entire zero.

Second Embodiment
In the first embodiment described above, (1) the case of polarity inversion in units of scanning lines has been described as an example. Such (1) polarity reversal for each scanning line and (3) pixel is effective as a countermeasure against flicker. However, since the writing polarity differs between adjacent pixels, a so-called horizontal electric field is generated and As a result of the occurrence of disclination (orientation failure) due to the electric field, the display quality is likely to deteriorate.
From the viewpoint of suppressing the occurrence of disclination, a surface inversion driving method in which the writing polarities of adjacent pixels are the same, that is, in a certain vertical scanning period, all pixels are set to positive writing. For example, in the next vertical scanning period, a driving method in which all pixels have negative polarity writing is ideal.
However, in such a surface inversion driving method, for example, when the writing polarity is inverted every vertical scanning period and the vertical scanning direction is the G1 → Gm direction (the direction from top to bottom), the following is performed: Problems have been pointed out. That is, in such a surface inversion driving method, when attention is paid to a certain column of data lines 114, for all the pixels corresponding to the focused data line,
The same polarity writing is performed over a certain vertical scanning period, but at the moment of shifting to the next vertical scanning period, the polarity of the image signal sampled on the data line is inverted. Is almost the same as the polarity of the image signal sampled on the data line of interest, whereas in the lower pixel, the retention period after the image signal is written Is opposite to the polarity of the image signal sampled on the data line of interest.
For this reason, there is a problem in that the display is nonuniform depending on the position of the pixel as a result of a difference in the influence (mainly light leakage) of the data line voltage on the pixel electrode between the upper pixel and the lower pixel. there were.
In order to solve this problem, in recent years, a driving method for selecting the scanning lines 112 in a new order has been proposed.

In this driving method, a display area, which is an area where the pixel electrodes 118 are arranged, is moved from the first line (m /
2) The upper region belonging to the scanning line up to the row and the lower region belonging to the scanning line from the (m / 2 + 1) th row to the m-th row are divided into two, and the selection of the scanning line is shown in FIG. As shown, the upper region and the lower region are selected alternately and from the top toward the bottom. In this case, m is a multiple of 2 (even number). Further, as shown in FIG. 15, in one vertical scanning period, for example, the upper region is written with negative polarity, while the lower region is written with positive polarity, and in the next one vertical scanning period, the upper region is positive. While writing is performed, negative writing is performed in the lower region.
According to this driving method, as shown in FIG. 16A, the area for positive polarity writing and the area for negative polarity writing move downward by one row in each of two horizontal scanning periods. Therefore, both areas are scrolled from the top to the bottom, and thus each pixel is written twice with positive polarity and negative polarity.
As described above, since one cycle of scrolling in the area for positive polarity writing and the area for negative polarity writing is performed twice, that is, positive polarity and negative polarity, in the first embodiment. This corresponds to two vertical scanning periods.

According to such a driving method, the writing polarity is inverted between adjacent pixels in one horizontal scanning period at the time of writing, but the adjacent pixels have the same writing polarity in other periods. Therefore, disclination hardly occurs. Further, since the positive polarity writing and the negative polarity writing are alternately performed, the polarity ratio of the image signal sampled on each data line is positive and negative in the holding period after the image signal is written. As a result, the display does not become non-uniform depending on the pixel position.

Then, next, an electro-optical device according to a second embodiment employed in such a driving method will be described.
In this electro-optical device, the scanning line driving circuit 130 (see FIG. 3) in the first embodiment outputs a scanning signal having a waveform as shown in FIG. 14, and the image processing circuit 300 in the first embodiment. (See FIG. 1) is that the image processing circuit 310 is replaced as shown in FIG. Others are the same as those in the first embodiment shown in FIG. 1, and the waveform of the scanning signal has already been described. Therefore, here, the description will focus on the image processing circuit 310 shown in FIG.

The image signal correction circuit 302 in FIG. 1 is replaced with the image signal correction circuit 303 in FIG. A detailed configuration of the image signal correction circuit 303 is shown in FIG. The image signal correction circuit 303 shown in FIG. 13 is provided with a frame memory 328 at the input stage of the image signal correction circuit 302 shown in FIG.
The frame memory 328 has two buffer areas, and in one buffer area,
A digital image signal VID supplied in accordance with vertical scanning and horizontal scanning is written for one screen in accordance with a write address Wad supplied from the control circuit 200. Also,
From the other buffer area, the image signals of the pixels located in the row of the selected scanning line are sequentially read according to the read address Rad supplied from the control circuit 200. When an image signal for one screen is written in one buffer area and an image signal for one screen is read from the other buffer area, writing and reading are switched. That is, the two buffer areas are alternately switched for writing and reading.
The reason why such a frame memory 328 is provided is that, in the first embodiment, the image signals supplied in accordance with the vertical scanning and the horizontal scanning may be processed in the order, whereas the second embodiment is used. This is because, in the embodiment, the selection order of the scanning lines 112 alternates between the upper area and the lower area, so that it is necessary to buffer one screen instead of the order of the vertical scanning and the horizontal scanning.

Note that the amplifying / inverting circuit 308 in FIG. 12 makes the serial-parallel converted image signal negative polarity when the scanning line belonging to the upper region is selected in one vertical scanning period, while the lower region. When the scanning line belonging to is selected, the serial-parallel converted image signal is made positive, and the polarity in the upper region and the lower region is inverted in the next vertical scanning period.
The other configuration is the same as that of the image signal correction circuit 302 in FIG.

In such a driving method, when the image signal correction circuit 303 does not exist, a difference in display quality appears as in the first embodiment. That is, a difference in display quality that appears in a pixel in a certain row of interest appears depending on the image signal of the row selected immediately before that row of interest. However, the first
In the embodiment, the line of interest and the line selected immediately before the line of interest are adjacent to each other. Therefore, if the image signal correction circuit 302 does not exist, a display difference as shown in FIG. As the contents, in the driving method applied in the second embodiment, the target row and the row selected immediately before the target row are separated by about half of the total number of rows. If 303 does not exist, the display content is as shown in FIG.
Specifically, after the scanning line a belonging to the row range B is selected, 2 /
The scanning line b spaced downward by m is selected, and then the scanning line c is selected.
Since a, b, c, d,..., e, f, g, h are made in this order, the difference in display quality when the black window display is selected is the total number of lines m from the start line of the black window display. A position separated downward by 2 / m, which is half of the first line, appears as a starting line, and appears in a width corresponding to the line range B. In this case, if the distance from the starting point row to the lower end of the display area is shorter than the width corresponding to the row range B, a short portion appears from the upper end of the display area, as shown in FIG.

In the second embodiment, the display screen is divided into two areas, an upper area and a lower area, but may be divided into, for example, even areas of 4 or more. For example, dividing the first to fourth areas into four areas, the scanning lines are first → second → third → fourth → first area, and selected in order from the top,
When the positive polarity writing and the negative polarity writing are executed alternately, as shown in FIG. 16B, the same positive polarity region and the negative polarity region scroll similarly.

Here, even when the image processing circuit 310 is employed for the driving method of the second embodiment, the image signal correction circuit 303 is interposed between the latch circuit 320 and the adder 322 as shown in FIG. A configuration may be adopted in which a multiplier 324 that multiplies the correction data Er by a coefficient k2 is inserted.
The coefficient k2 may also be set with any of the characteristics shown in FIG. 11A depending on whether or not the mode is the normally white mode and the gradation corresponding to the precharge voltage. . Also, the configuration for supplying the coefficient k2 is as shown in FIG.
As shown in FIG. 10B, the coefficient k2 may be output while changing from the start to the end of one horizontal effective display period using the counter 332 and the conversion table 334 as shown by 0 (a). Counter 332, storage unit 336 and interpolation unit 3
38, the coefficient k2 may be obtained by interpolation from the representative value.

In the first and second embodiments described above, precharging is performed by the precharging switch 1.
The precharge voltage PS is precharged to the data line 114 by turning on 61. For example, while the precharge control signal PG is at the H level, all the sampling switches 151 are turned on, and A configuration in which precharging is performed by applying a precharging voltage PS to the image signal line 171 may be employed.

In the embodiment described above, six data lines 114 are grouped into one block, and 1
The image signal VID1 converted into six systems for the six data lines 114 belonging to the block
Although ~ VID6 is sampled, the number of conversions and the number of data lines applied simultaneously (that is, the number of data lines constituting one block) are not limited to "6". For example, if the response speed of the sampling switch 151 in the sampling circuit 150 is sufficiently high, the corrected image signal is serially transmitted to one image signal line without being converted into parallel and sequentially sampled for each data line 114. You may comprise as follows. Also, the number of conversions and the number of data lines to be applied simultaneously are “3”, “12”, “24”, etc.
A configuration may be adopted in which correction image signals subjected to three-line conversion, 12-line conversion, 24-line conversion, or the like are simultaneously supplied to 12 or 24 data lines. The number of conversions is preferably a multiple of 3 in view of the fact that the color image signal is made up of signals related to the three primary colors in order to simplify the control and the circuit. However, in the case of a simple light modulation application such as a projector described later, it is not necessary to be a multiple of 3.

On the other hand, in the embodiment described above, the image signal processing circuit 300 (303) processes the digital image signal VID. However, the image signal processing circuit 300 (303) may be configured to process an analog image signal. In this configuration, the voltage of the image signal indicates the gradation of the pixel. In the embodiment, the image signal processing circuit 300 is configured to perform the correction before the serial-parallel conversion of the image signal. However, the image signal processing circuit 300 may be configured to perform the correction after the serial-parallel conversion. However, as described above, a configuration in which serial-parallel conversion is not performed may be used.

Furthermore, in the above-described embodiment, the description has been given of the normally white mode in which white display is performed when the effective voltage value between the counter electrode 108 and the pixel electrode 118 is small. However, the normally black mode in which black display is performed may be used. good. Further, as the precharge voltage PS, voltages Vg + and Vg− corresponding to gray are selected and the level is inverted every horizontal scanning period according to the writing polarity. However, a voltage corresponding to white may be used. As shown by the broken line in FIG. 5, in the positive polarity writing, the voltage Vc corresponding to white is selected, and in the negative polarity writing, the voltage Vb + corresponding to black is selected, and according to the writing polarity. A voltage corresponding to a different gradation may be used. When the precharge voltage PS has different gradations according to the writing polarity, it is necessary to prepare the gradation indicated by the reference signal Ref according to the polarity.

In addition, in the embodiment, a glass substrate is used as the element substrate 101.
(Silicon On Insulator) technology may be applied to form a silicon single crystal film on an insulating substrate such as sapphire, quartz, glass, etc., and various elements may be incorporated therein. Further, a silicon substrate or the like may be used as the element substrate 101, and various elements may be formed here. In such a case, field effect transistors can be used as the various switches, which facilitates high-speed operation. However, in the case where the element substrate 101 does not have transparency, it is necessary to use the pixel electrode 118 as a reflective type by forming the pixel electrode 118 with aluminum or separately forming a reflective layer.

Further, in the above-described embodiment, the TN type is used as the liquid crystal, but BTN (Bi-stable Tw
isted Nematic) type and ferroelectric type bistable types with memory properties, polymer dispersed types, and dyes that have anisotropy in visible light absorption in the major and minor axis directions of molecules ( Guest) is dissolved in a liquid crystal (host) with a fixed molecular arrangement, and dye molecules are aligned parallel to the liquid crystal molecules.
A (guest host) type liquid crystal may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.

<Electronic equipment>
Next, some electronic apparatuses using the electro-optical device according to the above-described embodiment will be described.

<Part 1: Projector>
First, a projector using the above-described display panel 100 as a light valve will be described. FIG. 18 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 2102 made of a white light source such as a halogen lamp is provided inside the projector 2100. The projection light emitted from the lamp unit 2102 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 100 in the above-described embodiment, and R supplied from the processing circuit (not shown in FIG. 18).
, G, and B are driven by image signals corresponding to the respective colors. That is, the projector 2100 has a configuration in which three sets of the display panel 100 shown in FIG. 1 are provided corresponding to each of R, G, and B colors.
Now, the light modulated by the light valves 100R, 100G, and 100B, respectively,
The light enters the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, the projection lens 2 is displayed on the screen 2120.
In 114, a color image is projected.

The light valves 100R, 100G, and 100B include a dichroic mirror 2
Since light corresponding to the primary colors of R, G, and B is incident by 108, it is not necessary to provide a color filter as described above. Further, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the light valve 10
Since the 0G transmission image is projected as it is, the horizontal scanning direction by the light valves 100R and 100B is opposite to the horizontal scanning direction by the light valve 100G, and an image obtained by inverting the left and right is displayed.

<Part 2: Mobile computer>
Next, an example in which the above-described liquid crystal display device is applied to a mobile personal computer will be described. FIG. 19 is a perspective view showing the configuration of this personal computer. In the figure, a computer 2200 includes a main body unit 2204 provided with a keyboard 2202 and a display panel 100 used as a display unit. Note that a backlight unit (not shown) for improving visibility is provided on the back surface.

<Part 3: Mobile phone>
Further, an example in which the above-described liquid crystal display device is applied to a display unit of a mobile phone will be described.
FIG. 20 is a perspective view showing the configuration of this mobile phone. In the figure, the mobile phone 2300 is
In addition to a plurality of operation buttons 2302, a display panel 100 used as a display unit is provided along with an earpiece 2304 and a mouthpiece 2306. A backlight unit (not shown) for improving visibility is also provided on the back surface of the display panel 100.

<Summary of electronic devices>
In addition to the electronic devices described with reference to FIGS. 18, 19 and 20, the electronic devices include a television, a viewfinder type / direct monitor type video tape recorder, a car navigation device, a pager, an electronic notebook, Examples include calculators, word processors, workstations, videophones, POS terminals, digital still cameras, and devices equipped with touch panels. Needless to say, the electro-optical device according to the present invention is applicable to these various electronic devices.

1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. (A) is a perspective view which shows the structure of the display panel in the liquid crystal display device, (b) is sectional drawing about the line A-A '. It is a block diagram which shows the electric constitution of the element substrate in the display panel. 4 is a timing chart for explaining the operation of the liquid crystal display device. 4 is a timing chart for explaining the operation of the liquid crystal display device. It is a figure for demonstrating prevention of the display quality fall by the liquid crystal display device. It is a block diagram which shows the structure of the correction circuit in the liquid crystal display device. It is a timing chart for explaining operation of the correction circuit. It is a block diagram which shows another structure of the correction circuit in 1st Embodiment. It is a figure for outputting coefficient k2 in the same composition. It is a figure which shows the coefficient k2 in the same structure. It is a block diagram which shows the whole structure of the liquid crystal display device which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the correction circuit of the liquid crystal display device which concerns on 2nd Embodiment of this invention. FIG. 3 is a diagram showing the selection order and polarity of scanning lines in the liquid crystal display device. It is a figure which shows the polarity of the display area in the liquid crystal display device. It is a figure which shows the voltage waveform of the scanning signal in the liquid crystal display device. It is a block diagram which shows another structure of the correction circuit in 2nd Embodiment. It is sectional drawing which shows the structure of the projector which is an example of the electronic device to which the liquid crystal display device which concerns on embodiment is applied. It is a perspective view which shows the structure of the personal computer which is an example of the electronic device to which the liquid crystal display device which concerns on embodiment is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the liquid crystal display device is applied. It is a top view which shows the fall of the display quality by horizontal crosstalk. It is a top view which shows the fall of the display quality by horizontal crosstalk. It is a top view which shows the fall of the display quality by horizontal crosstalk.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display panel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ...
Pixel electrode 130... Scanning line driving circuit 140 140 data line driving circuit 150 sampling circuit 160 precharge circuit 300 image signal processing circuit 302 image signal correction circuit 312 subtractor 314 integration , 318 ... multiplier, 322 ... adder, 2100 ... projector, 2200 ... personal computer, 2300 ... mobile phone

Claims (16)

A plurality of scanning lines, a plurality of data lines,
A plurality of switching elements respectively provided at intersections of the scanning lines and the data lines;
A plurality of pixel electrodes provided corresponding to the switching elements,
The pixel electrode has a counter electrode facing through an electro-optic material,
After precharging each data line to a predetermined voltage, an image signal that is supplied by correcting the image signal to a display panel that applies the image signal to the pixel electrode located on the selected scanning line via the data line A correction circuit,
A subtractor for obtaining a difference between a reference gradation and a gradation of a pixel indicated by the image signal;
An integrator that integrates the subtraction output of the subtractor for one row of pixels located on the selected scan line;
An adder that adds the integration output of the integrator to an image signal for one row of pixels located on the next selected scanning line, and supplies the image signal as a corrected image signal. Correction circuit. The image signal correction circuit according to claim 1, wherein the reference gradation corresponds to a gray gradation in a pixel. The image signal correction circuit according to claim 1, further comprising: a first multiplier that multiplies the integration output by the integrator by a first coefficient. A circuit for gradually attenuating or increasing the integration output by the integrator as a pixel located on the next selected scanning line is horizontally scanned from one end side to the other end side;
The image signal correction circuit according to claim 1, further comprising:   5. The image signal correction circuit according to claim 4, wherein the circuit for attenuating or increasing is a second multiplier that multiplies the integral output by a second coefficient. A plurality of scanning lines, a plurality of data lines,
A switching element provided at an intersection of the scanning line and the data line, and is interposed between the data line and a pixel electrode paired with the switching element, and when the scanning line is selected A switching element to turn on;
The pixel electrode has a counter electrode facing through the electro-optic material,
Image signal correction after precharging each data line to a predetermined voltage and supplying the image signal to the display panel that applies the image signal to the pixel electrode located on the selected scanning line via the data line. A method,
A subtraction step asking you to difference integral value of the gray level of the pixel that is indicated by the reference gray image signal,
An integration step of integrating the difference value obtained in the subtraction step for one row of pixels located on the selected scanning line ;
An addition supplying step of adding the integration value obtained in the integration step to an image signal for one row of pixels located on the next selected scanning line and supplying the corrected image signal ;
An image signal correction method comprising: An electro-optical device having a display panel having a plurality of pixels that perform display according to an image signal, and an image signal correction circuit that corrects and supplies the image signal to the display panel,
The image signal correction circuit includes:
A subtractor for obtaining a difference between the reference gradation and the gradation of the pixel indicated by the image signal;
An integrator that integrates the subtraction output of the subtractor for one row of pixels located on the selected scan line;
An adder that adds the integration output of the integrator to an image signal for one row of pixels located on the next selected scanning line and supplies the image signal as a corrected image signal, and the display panel includes:
A plurality of scanning lines, a plurality of data lines,
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A sampling circuit that samples an image signal on each of the data lines when a scan line is selected;
A switching element provided at an intersection of the scanning line and the data line, and is interposed between the data line and a pixel electrode paired with the switching element, and when the scanning line is selected A switching element to turn on;
The pixel electrode has a counter electrode opposed to the pixel electrode via an electro-optic material, and after precharging each data line to a predetermined voltage, the pixel electrode positioned on the selected scanning line is interposed via the data line. An electro-optical device that applies an image signal.   The electro-optical device according to claim 7, further comprising: a first multiplier that multiplies an integration output by the integrator by a first coefficient. A circuit for gradually attenuating or increasing the integration output by the integrator as a pixel located on the next selected scanning line is horizontally scanned from one end side to the other end side;
The electro-optical device according to claim 7, further comprising:   The electro-optical device according to claim 9, wherein the attenuation or increase circuit is a second multiplier that multiplies the integral output by a second coefficient. The display panel has an even number of regions divided along a horizontal scanning direction,
Each region is a pixel region including two or more adjacent scanning lines,
The scanning line driving circuit selects a scanning line belonging to one region among the regions, and then selects a scanning line belonging to another region,
The image signal correction circuit includes:
In a period in which a scanning line belonging to one region is selected, an image signal is supplied at a higher voltage to the counter electrode,
The electro-optical device according to claim 7, wherein an image signal is supplied to the counter electrode at a lower voltage during a period in which a scanning line belonging to another region is selected. The electro-optical device according to claim 11, wherein the number of scanning lines included in each region is the same . The image signal correction circuit includes:
12. The electro-optical device according to claim 11, further comprising a frame memory that temporarily stores the image signal, sequentially reads out the image signal corresponding to the selected scanning line, and supplies the image signal to the subtracter. A circuit for gradually attenuating or increasing the integration output by the integrator as a pixel located on the next selected scanning line is horizontally scanned from one end side to the other end side;
The electro-optical device according to claim 11, further comprising:   15. The electro-optical device according to claim 14, wherein the attenuation or increase circuit is a second multiplier that multiplies the integral output by a second coefficient.   An electronic apparatus comprising the electro-optical device according to claim 7 as a display unit.

Images