JP2002215105A - Electro-optical device, driving circuit, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To deal with high definition by making a wiring pitch p arrangement of scanning lines 112 narrower. SOLUTION: This driving circuit is provided with a pulse signal Pk outputted from a k-th stage unit circuit 1310, a NAND circuit 1320 for obtaining a NAND signal of the pulse signal Pk and the pulse signal P(k+1) outputted from the next (k+1)th stage unit circuit 1310, a NOT circuit 1330 for obtaining a level- inverted pulse signal Qk, enable signal lines 1351, 1352 to which such enable signals Enb1Y, Enb2Y are supplied, respectively, as their ON-level periods do not overlapping with each other over the output period of the pulse signal Qk, and TFTs 1341, 1342 which are inserted between either of the enable signal lines and one of the scanning lines 112 and are also turned on in the period in which the pulse signal Qk is being outputted. In this case, the NAND circuits 1320 and the NOT circuits 1330 are arranged in the direction orthogonal to the direction in which the scanning lines are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electro-optical device, a driving circuit, and an electronic apparatus capable of achieving high definition by narrowing an arrangement pitch of pixels.

[0002]

2. Description of the Related Art In recent years, an electro-optical device which performs display by electro-optical change of an electro-optical material has been known as a cathode ray tube (CRT).
In addition to direct-view display units such as various information processing devices and wall-mounted televisions, projection display units such as light valves of projectors are being used as display devices replacing the above. Such an electro-optical device can be classified into various types according to a driving method or the like. An active matrix electro-optical device that drives pixels by switching elements has the following configuration.

That is, in an active matrix type electro-optical device, a pixel electrode is formed corresponding to the intersection of a scanning line extending in a row direction and a data line extending in a column direction. A switching element such as a thin film transistor (hereinafter, referred to as a “TFT”) that is turned on and off in accordance with a scanning signal supplied to a scanning line is interposed between the pixel electrode and the data line, and is opposed to the pixel electrode. The electrodes face each other via the electro-optical material.

In such a configuration, when an on-level scanning signal is applied to a scanning line, a switching element connected to the scanning line becomes conductive. In this conductive state, when an image signal according to the gradation (density) is applied to the pixel electrode via the data line, the image signal is applied to the electro-optical material sandwiched between the pixel electrode and the counter electrode. Is applied. After that, even if the scanning signal is turned off and the switching element is turned off, the voltage applied to the electro-optical material depends on the capacitive property of the electro-optical material itself and the storage capacitance attached thereto. Maintained by As described above, when each switching element is driven to control the applied voltage, a predetermined display is possible because the electro-optical change of the electro-optical material differs for each pixel.

Here, a scanning signal is supplied to the above-mentioned scanning line by a scanning line driving circuit.
In detail, the scanning line driving circuit outputs signals from a Y shift register in which a plurality of unit circuits are arranged in a column direction orthogonal to a row direction, which is a direction in which the scanning lines extend, and an adjacent unit circuit. A logical operation circuit that performs a logical operation on the signals. Here, the Y shift register shifts the transfer start pulse supplied at the beginning of the vertical scanning period in order in accordance with the Y-side clock signal (and its inverted clock signal) serving as the reference for vertical scanning and transfers it. There is a configuration in which the logical operation circuit performs a logical operation on the transferred signals to generate a pulse signal in which the ON level period is sequentially and exclusively, and supplies the pulse signal to the scanning line. I have.

On the other hand, an image signal is sampled on a data line by a data line drive circuit. Specifically, the data line driving circuit outputs signals from an X shift register in which a plurality of unit circuits are arranged in a row direction orthogonal to a column direction which is a direction in which the data lines extend, and an adjacent unit circuit. The circuit includes a logical operation circuit for performing logical operation on signals, and a sampling switch interposed between one end of the data line and the image signal line. Among them, the X shift register sets the start pulse supplied at the beginning of the horizontal scanning period to be exclusively ON level in accordance with the X-side clock signal (and its inverted signal) serving as the reference for horizontal scanning. The pulse signals are sequentially transferred and the transferred pulse signals are output as sampling control signals. In addition, the logical operation circuit performs a logical operation on the transferred signals, so that the ON level periods are sequentially and
An exclusive sampling control signal is output. The sampling switch samples the image signal supplied to the image signal line according to the sampling control signal and supplies the image signal to the corresponding data line.

In this type of electro-optical device, the above-described scanning line driving circuit and data line driving circuit are formed on an element substrate constituting the electro-optical device together with switching elements connected to pixel electrodes. In many cases, it is practically used as a drive circuit built-in type (integrated type).
In this case, by reducing the space of the peripheral circuit including the drive circuit, it is possible to reduce the size of the entire device, and furthermore, the constituent elements of the peripheral circuit are formed in the same process as the switching element for driving the pixel electrode. By forming them, it is possible to improve the manufacturing efficiency of the entire device and reduce the cost.

[0008]

However, a one-stage unit circuit in the above-described Y shift register, and
Since the arithmetic circuits are provided in units of one scanning line, they must be arranged within the scanning line pitch. Therefore, in the conventional electro-optical device,
The scanning line pitch could not be reduced below the arrangement pitch (currently, 20 μm) of the unit circuit and the operation circuit of one stage of the Y shift register, which was a major obstacle in achieving higher definition.

Note that, unlike the Y shift register, the one-stage unit circuit in the X shift register has one data line.
There is no need to provide them for books. This is because P signals can be simultaneously driven by distributing a single (serial) image signal to a plurality of P systems and expanding them P times on the time axis (converting them into parallel). This is because, in such a configuration, the unit circuits in the X shift register need only be provided in one stage for P data lines.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electro-optical device, a driving circuit thereof, and an electronic device which can easily narrow the arrangement pitch of pixels. Is to do.

[0011]

In order to achieve the above object, a driving circuit according to a first aspect of the present invention comprises a pixel electrode provided corresponding to an intersection between a scanning line and a data line; A drive circuit that supplies a scanning signal to the scanning line, for an electro-optical device including a pixel switch that is interposed between the data line and a pixel switch that is turned on and off according to the scanning signal supplied to the scanning line, Each time the level of the clock signal changes, it consists of a plurality of stages of unit circuits that transfer the input pulse signal, and the output of the unit circuit in a certain stage is
A shift register connected to the input of the next unit circuit;
A pulse signal output by a unit circuit of a certain stage and a pulse signal output by a unit circuit of the next stage are input,
An arithmetic circuit that outputs a pulse signal having a width corresponding to a period in which the logic levels of both pulse signals overlap each other, and an enable signal in which the on-level periods do not overlap each other over a period in which the pulse signal is output by the arithmetic circuit, respectively. It is characterized by comprising a supplied enable signal line, and a division switch that is interposed between one enable signal line and one scanning line and that is turned on during a period when a pulse signal is output by the arithmetic circuit. And According to this configuration, the enable signal supplied by the enable signal line is extracted by turning on the division switch and supplied to the scan line as a scan signal. Therefore, the unit circuits and the arithmetic circuits in the shift register need only be arranged with a plurality of scanning lines as one unit. Furthermore, a simple switch that turns on in accordance with a pulse signal output from the arithmetic circuit is simply inserted between the enable signal line and the scanning line. Therefore, it is easy to narrow the scanning line pitch.

Here, in the first invention, each time the level of the clock signal changes, in the unit circuit for transferring the input pulse signal, the pulse signal output by the unit circuit of a certain stage and the unit circuit of the next stage Since the pulse signal output by the above has a period that overlaps with each other, these cannot be used as a scanning signal as they are. Therefore, a pulse signal output from a unit circuit in a certain stage and a pulse signal output from a unit circuit in the next stage are input, and a pulse signal having a width corresponding to a period in which the logic levels of both pulse signals overlap is input. Is output, overlapping of adjacent pulse signals can be avoided. As an arithmetic circuit that performs such an operation, a first logic that performs an elementary operation by inputting a pulse signal output from a unit circuit in a certain stage and a pulse signal output from a unit circuit in the next stage is used as an input. It is preferable that the circuit be composed of an arithmetic circuit and a second logical operation circuit that executes an elementary operation by using a signal output from the first logical operation circuit as an input.

Since the first and second logical operation circuits need only be arranged with a plurality of scanning lines as one unit, similarly to the unit circuit in the shift register, the first and second logical operation circuits are orthogonal to the extending direction of the scanning lines. There is some margin in area in the direction of movement. Therefore, in the first invention, it is preferable that the first logical operation circuit and the second logical operation circuit are arranged along a direction substantially perpendicular to the scanning line.
In this configuration, as compared with the configuration in which the first and second logical operation circuits are linearly arranged in the scanning line direction, the width of the area necessary for circuit formation in the scanning line forming direction is reduced. In addition, it is possible to reduce the size of the entire device. In particular, forming a large number of element substrates from one mother substrate,
In the case of so-called multi-panning, the number of rows from the mother substrate increases as the width of the scanning line in the forming direction is reduced, so that productivity can be improved.

On the other hand, a configuration in which a pulse signal having a width corresponding to a period in which a logic level of a pulse signal output from a unit circuit in a certain stage and a pulse signal output from a unit circuit in the next stage overlap is output. In general, a logical product signal of the two is obtained.
Circuit or a NOR circuit, the first logical operation circuit is a NAN for obtaining a NAND of two input signals.
Preferably, the circuit is a D circuit, and the second logical operation circuit is a NOT circuit for obtaining a negation of an input signal. Accordingly, the arithmetic circuit for obtaining the logical product of the pulse signal output from the unit circuit in a certain stage and the pulse signal output from the unit circuit in the next stage has the best characteristic.

The split switch in the first invention is a transistor of one of N-channel type and P-channel type, and a pulse signal output by the arithmetic circuit is used as a gate input. A configuration is preferred. According to this configuration, the number of required transistors can be reduced. In addition, since the mobility of electrons is higher than the mobility of holes, it is preferable that the N-channel transistor has the same dimensions and the same structure from the viewpoint of high-speed operation.

The split switch according to the first invention is a transmission gate combining N-channel and P-channel transistors, and outputs a pulse signal output from the arithmetic circuit to a gate input. Is also preferable. In this configuration, the number of transistors constituting the split switch is doubled as compared with the case where one channel type transistor is used as the split switch, but voltage drop and signal delay of an enable signal supplied as a scanning signal are prevented. It is possible to do.

Next, in order to achieve the above object, a driving circuit according to the second aspect of the present invention comprises a pixel electrode provided corresponding to an intersection of a scanning line and a data line; And a pixel switch that is turned on and off according to the scanning signal supplied to the scanning line, and supplies a scanning signal to the scanning line. Each time the level transitions, it consists of a plurality of stages of unit circuits that transfer the input pulse signal. An operation to input a pulse signal output by a circuit and a pulse signal output by a unit circuit at the next stage and output a pulse signal having a width corresponding to a period in which the logic levels of both pulse signals overlap. Between an enable signal line and an enable signal line to which enable signals whose ON-level periods do not overlap each other are provided over a period in which a pulse signal is output by the arithmetic circuit. And a pixel switch corresponding to the intersection of a divided switch that is turned on during a period in which a pulse signal is output by the arithmetic circuit and a scanning line connected to the turned on divided switch. And a data line driving circuit for supplying a signal. According to the second invention having such a configuration, similarly to the first invention, it is easy to reduce the scanning line pitch.

In order to achieve the above object, an electro-optical device according to a third aspect of the present invention includes a pixel electrode provided corresponding to an intersection of a scanning line and a data line; And a plurality of stages of unit circuits for transferring an input pulse signal each time the level of a clock signal changes, and a pixel switch that is turned on and off in accordance with the scan signal supplied to the scan line. The output of the unit circuit of a certain stage is a shift register connected to the input of the unit circuit of the next stage, the pulse signal output by the unit circuit of a certain stage, and the pulse signal output by the unit circuit of the next stage. An arithmetic circuit for inputting and outputting a pulse signal having a width corresponding to a period in which the logic levels of the two pulse signals overlap; A period in which a pulse signal is output by the arithmetic circuit while being inserted between an enable signal line to which an enable signal is supplied and an enable signal that does not overlap each other, and one enable signal line and one scan line. , And a data line driving circuit for supplying an image signal via a data line to a pixel electrode corresponding to an intersection of a scanning line connected to the turned on divided switch. . According to the third aspect of the present invention, similarly to the first and second aspects, it is easy to narrow the scanning line pitch. In addition, as the electro-optical device, a liquid crystal device, an EL (electro luminescence) device, a PDP (plasma display device).
Panel).

Further, the electronic apparatus according to the present invention is characterized in that:
Since the electro-optical device according to the present invention is provided as a display unit, a high-definition display in which the scanning line pitch is easily narrowed can be realized.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment First, an electro-optical device according to a first embodiment of the present invention will be described. This electro-optical device uses liquid crystal as an electro-optical material and performs display by electro-optical change. Figure 1
FIG. 1A is a perspective view illustrating a configuration of a liquid crystal panel 100 excluding an external circuit in the electro-optical device, and FIG.
FIG. 2B is a sectional view taken along line AA ′ in FIG.

As shown in these figures, in the liquid crystal panel 100, an element substrate 101 on which various elements and pixel electrodes 118 are formed, and a counter substrate 102 on which a counter electrode 108 and the like are provided are formed by spacers (shown in FIG. 1). Seal material 1 including (omitted)
The electrodes are bonded so that the electrode forming surfaces are opposed to each other with a certain gap maintained by the gap 04, and a TN (Twisted Nematic) type liquid crystal 105 is sealed as an electro-optical material in this gap.

Here, the element substrate 101 includes glass,
Although a semiconductor, quartz, or the like is used, glass or the like is used for the counter substrate 102. When an opaque substrate is used as the element substrate 101, it is used as a reflection type instead of a transmission type. In addition, the sealing material 10
Numeral 4 is formed along the periphery of the counter substrate 102, and is partially open to seal the liquid crystal 105. For this reason, after the liquid crystal 105 is sealed, the opening thereof is
6 sealed.

Next, on the opposing surface of the element substrate 101,
In a region 140a on one side outside the sealing material 104,
An X shift register described later is formed. further,
A sampling circuit is formed along with an image signal line, which will be described later, in an area 150a near this one side where the sealant 104 is formed. On the other hand, a plurality of mounting terminals 107 are formed on an outer peripheral portion of this one side, so that various signals are input from an external circuit. Further, a scanning line driving circuit, which will be described later, is formed in each of the two side regions 130a adjacent to this one side, so that the scanning lines are driven from both sides. Note that a configuration in which the scanning line driving circuit is formed only on one side may be employed as long as the delay of the scanning signal supplied to the scanning line does not matter. In addition, wirings and the like shared by the two scanning line driving circuits are formed in the remaining area 160a on one side.

On the other hand, as will be described later, the opposing electrode 108 provided on the opposing substrate 102 has conductive materials provided at two corners close to the regions 140a and 150a among the four corners of the bonding portion with the element substrate 101. The element substrate 10
1 and is electrically connected to the mounting terminal 107 formed in the first terminal.
In addition, a coloring layer (color filter) is provided on the counter substrate 102 in a region facing the pixel electrode 118 as necessary, though not shown. However, when it is applied to a color light modulation application as in a projector described later, it is not necessary to form a coloring layer on the counter substrate 102. In addition, regardless of whether or not a colored layer is provided, the pixel electrode 11 is used to prevent a decrease in contrast ratio due to light leakage.
A light-shielding film is provided in a portion other than the region facing 8 (not shown).

The element substrate 101 and the opposing substrate 10
2 is provided with an alignment film that has been rubbed so that the major axis direction of the molecules of the liquid crystal 105 is continuously twisted by about 90 degrees between the two substrates. Are provided with polarizers each having an absorption axis set. Thereby, the liquid crystal capacitance (capacitance sandwiching the liquid crystal 105 between the pixel electrode 118 and the counter electrode 108)
If the effective value of the voltage applied to the substrate is zero, the transmittance is maximized, while as the effective value of the voltage is increased, the transmittance is gradually reduced, and finally the transmittance is minimized (normally white). mode).

Since the alignment film and the polarizer are not directly related to the present invention, their illustration is omitted. In FIG. 1B, the counter electrode 108, the pixel electrode 118, the mounting terminal 107, and the like are provided with a thickness, but this is a convenient measure for indicating a positional relationship. Is negligibly thin relative to the thickness of the substrate.

<Electrical Configuration> Next, the electrical configuration of the above-described liquid crystal panel 100 will be described. FIG. 2 is a diagram showing an equivalent circuit of a display area in the liquid crystal panel. As shown in this figure, in the display area 100a, a plurality of scanning lines 112 are formed extending in the row (X) direction, and a plurality of data lines 114 are formed in the column (Y). ), And pixels are provided corresponding to these intersections.

More specifically, the scanning line 112 and the data line 114
Is provided at the intersection with the pixel switch TFT 116 for controlling the pixel, the gate of which is connected to the scanning line 112, the source of the TFT 116 is connected to the data line 114, and the TFT 11
6 is connected to the pixel electrode 118. That is, the TFT 116 is connected to the data line 114 and the pixel electrode 11.
8, it is turned on and off in accordance with the logical level of the scanning signal supplied to the scanning line 112.
Here, in the present embodiment, since the TFT 116 is of an N-channel type, when the scanning signal is at the H level,
The FT 116 will be turned on. On the other hand, as described above, in the liquid crystal panel 100, the liquid crystal 105
1 and the opposing substrate 102, the liquid crystal capacitance is constituted by the pixel electrode 118, the opposing electrode 108, and the liquid crystal 105 interposed between these electrodes. .

Here, for convenience of explanation, the total number of scanning lines 112 is "m", and the total number of data lines 114 is "6 ·
n ”(where m and n are integers), the pixels are arranged in a matrix of m rows × (6 · n) columns corresponding to the intersections of the scanning lines 112 and the data lines 114. Will be. In addition, the display area 100a further includes a storage capacitor 119 for reducing leakage of the liquid crystal capacitance.
Is provided for each pixel. Specifically, the storage capacity 11
One end of 9 is connected to the pixel electrode 118 (the drain of the TFT 116), and the other end is commonly connected by a capacitance line 175. For this reason, the storage capacity 119
Since it is electrically parallel to the liquid crystal capacitance, the retention characteristics of the liquid crystal capacitance are improved, and a display with a high contrast ratio is achieved.

Next, a circuit formed around the display area 100a will be described. FIG. 3 is a block diagram showing an electrical configuration of the element substrate 101 in the liquid crystal panel 100. In this figure, a scanning line driving circuit 1
30 is a lower voltage VssY and a higher voltage VddY
Is used as a power supply voltage to transfer the transfer start pulse DY in accordance with the clock signal CLY and the inverted clock signal CLYinv, thereby obtaining the scan signals G1, G2,
, Gm, and outputs them to each of the scanning lines 112.

More specifically, the scanning line driving circuit 130 is configured as shown in FIG.
As shown in (1), first, each time the logic level of the clock signal CLY (and the inverted clock signal CLYinv) transitions for one cycle of four horizontal scanning periods (4H), it is supplied at the beginning of the vertical scanning period. By sequentially shifting the transfer start pulse DY, signals P1, P2, P3,... Are obtained, and secondly, AND signals Q1, Q2, Q3,. Third, the period in which the supplied enable signals Enb1Y and Enb2Y are at the H level is sequentially extracted in the period in which the AND signal is output, and the signals are extracted as scanning signals G1, G2,. .., M-th scanning line 11
2. Note that the enable signal Enb
1Y and Enb2Y are enable signal lines 1351 and 13
Each of them is supplied from an external circuit via a corresponding one of the external circuits 52.

On the other hand, the X shift register 140 sequentially excludes the transfer start pulse DX by transferring the transfer start pulse DX according to the clock signal CLX and the inverted clock signal CLXinv using the lower voltage VssX and the higher voltage VddX as the power supply voltage. .., Sn, which are at H level, are output within the horizontal scanning period. The detailed configuration is not shown because it is not directly related to the present invention, but (n + 1)
It is composed of a unit circuit of a stage and an AND circuit. As shown in FIG. 9, the unit circuit of the (n + 1) stage includes the clock signal CLX (and the inverted clock signal CL).
Xinv), the signals S1 ′, S2 ′, S3 ′,... Are obtained by sequentially shifting the transfer start pulse DX supplied at the beginning of the horizontal scanning period every time the level changes.
Each AND circuit outputs the enable signal Enb1X or Enb1X.
The signals S1 ′, S2 ′, S3 ′,..., S
The pulse width of n 'is narrowed down to the period Smp so that adjacent ones do not overlap each other, and output as sampling control signals S1, S2, S3,..., Sn.

Next, the image signals VID1 to VID6 supplied via the six image signal lines 122 are, as shown in FIG. 9, one system image signal VID supplied in synchronization with the dot clock DCLK. Is distributed to six systems by an external circuit and is extended six times in the time axis. The polarity of the image signals VID1 to VID6 is appropriately inverted by an external circuit. Here, in the present embodiment, the polarity inversion of the image signal refers to the counter electrode 108.
Means that the level is alternately inverted between positive polarity and negative polarity with reference to a voltage substantially equal to the voltage LCcom applied to the voltage. At this time, whether or not the polarity is inverted is generally determined based on whether the method of applying the image signal to the data line is a polarity inversion in a scanning line unit, a polarity inversion in a data line unit, or a polarity in a pixel unit. It is determined according to whether it is inversion or polarity inversion in frame units, and the inversion cycle is
The period is set to the period of one horizontal scanning period, the dot clock DCLK, or one vertical scanning period. However, in the present embodiment, for convenience of explanation, a case where the polarity is inverted in units of scanning lines will be described as an example, but the present invention is not limited to this.

Subsequently, the sampling circuit 150 includes a sampling switch 151 provided for each data line 114.
Consists of Here, the data lines 114 are divided into blocks every six lines, and j (j is
The leftmost data line 114 among the six data lines 114 belonging to the (1, 2, 3,..., N) -th block
Is connected to one end of the image signal VID1 supplied through the image signal line 122.
Is sampled during a period in which the sampling control signal Sj is at the H level, and is supplied to the data line 114. Also, of the six data lines 114 belonging to the j-th block, the sampling switch 151 connected to one end of the second data line 114 is connected to the image signal VID2 supplied via the image signal line 122. Is sampled during the period when the sampling control signal Sj is at the H level, and the data line 1
14.

Similarly, among the six data lines 114 belonging to the j-th block, the sampling switch 151 connected to one end of the third, fourth, fifth and sixth data lines 114 is connected to the image signal line. The image signals VID3, VID4, VID5, VID6 supplied via
The sampling is performed during the period when the sampling control signal Sj is at the H level, and the corresponding data line 114 is sampled.
It is configured to supply to. That is, when the sampling control signal Sj goes to the H level, the image signals V
ID1 to VID6 are simultaneously sampled. Therefore, a data line driving circuit is constituted by the X shift register 140 and the sampling circuit 150.

In FIG. 3, two electrodes 109 to which the voltage LCcom is applied via the mounting terminal 107 are provided at points corresponding to corners of the counter substrate 102, respectively. Therefore, when the element substrate 101 is actually bonded to the counter substrate 102, the electrode 109 and the counter electrode 108 are connected via the conductive material, and the counter electrode 10
8, the voltage LCcom is applied. In the present embodiment, the electrode 109 is provided at two points. However, the electrode 109 is provided because the voltage LCcom is applied to the counter electrode 108 via a conductive material. It is sufficient that at least one location is provided with 109. Therefore, the location where the electrode 109 is provided may be one location, or may be three or more locations. Further, in the present embodiment, the capacitance line 175
The lower voltage VssY of the power supply is applied.
Since a constant voltage only needs to be applied, the higher voltage VddY of the power supply and the power supply voltages VssX and Vdd on the X side are used.
X, voltage LCcom, etc. may be applied.

<Scanning Line Driving Circuit> Next, details of the scanning line driving circuit 130 will be described. FIG. 4 is a block diagram illustrating a configuration of the scanning line driving circuit. As shown in this figure, the scanning line driving circuit 130 includes a unit circuit 1310,
A Y shift register 1300 connected from the first stage to the (M + 1) th stage is provided. Here, in the present embodiment, the number of stages “M” is a value corresponding to 「of the total number“ m ”of the scanning lines 112. That is, in the present embodiment, the unit circuit 1310 of the Y shift register 1300
The number of stages is one more than half the total number of lines.
For convenience of explanation, signals output from the first, second, third,..., Mth and (M + 1) th unit circuits 1310 are respectively represented by P1, P2, P3,. , P
(M + 1).

<Unit Circuit> Here, for convenience of explanation, details of the unit circuit 1310 will be described. FIG. 5 is a circuit diagram showing a detailed configuration of the unit circuit 130. As shown in this figure, the unit circuits of the odd-numbered stages (1, 3, 5,...) First have the case where the clock signal CLY is at the H level (the case where the inverted clock signal CLYinv is at the L level).
Second, a clocked inverter 1312a for inverting the level of the input pulse signal, second, an inverter 1314a for reinverting the inverted pulse signal, and third, when the clock signal CLY is at the L level (inverted clock signal C
A clocked inverter 1316a that further inverts the level of the re-inversion pulse signal when LYinv is at the H level and feeds back the input signal to the inverter 1314a. Among these, the pulse signal from the inverter 1314a is supplied to one of the input terminals of the NAND circuit 1320 to be described later as the output of the unit circuit 1310 in the stage, and is also supplied to the input terminal of the unit circuit 1310 in the next stage. It has become.

On the other hand, the unit circuits of the even-numbered stages (2, 4, 6,...) First include a clocked inverter 1312b for inverting the level of the input pulse signal when the clock signal CLY is at the L level. Second, the inverter 1314b re-inverts the inverted pulse signal, and thirdly, when the clock signal CLY is at the H level, the level of the re-inverted pulse signal is further inverted and fed back to the input terminal of the inverter 1314b. A clocked inverter 1316b. That is, the clocked inverter 131 of the even-numbered stage
2b and 1316b are odd-numbered clocked inverters 1
The supply of the clock signal CLY and the supply of the inverted clock signal CLYinv are reversed with respect to 312a and 1316a. Note that the pulse signal from the inverter 1314b is supplied to the other of the input terminals of the NAND circuit 1320, which will be described later, as the output of the unit circuit 1310 in the stage, and to the input terminal of the unit circuit 1310 in the next stage.

Next, the operation of the Y shift register 1300 in which the unit circuits 1310 are connected in a plurality of stages will be described. First, in FIG. 8, at time t ₁ , which is the beginning of the vertical scanning period, the transfer start pulse DY goes to the H level, is input to the first unit circuit 1310, and the clock signal CLY goes to the H level (inverted clock). When the signal CLYinv transitions to the L level, the transfer start pulse DY is inverted by the clocked inverter 1312a in the first unit circuit 1310 and is again inverted by the inverter 1314a in the same stage.
The output signal P1 of the first-stage unit circuit 1310 becomes H level.

Subsequently, at time t ₂ , when the clock signal CLY changes to the L level (the inverted clock signal CLYinv changes to the H level), the H-level output signal P 1 becomes the first output signal P 1.
Clocked inverter 1 in stage unit circuit 1310
The signal is inverted by the input terminal 316a and fed back to the input terminal of the inverter 1314a. Therefore, the output signal P1 maintains the H level. On the other hand, the H-level output signal P1 is inverted by the clocked inverter 1312b in the second-stage unit circuit 1310, and is again inverted by the same-stage inverter 1314b, so that the output signal P2 of the second-stage unit circuit 1310
Becomes H level.

[0043] Then, at time t _3, the clock signal CLY is H level (the inverted clock signal CLYinv is L level) transition, the output signal P2 of the H level, the second
Clocked inverter 1 in stage unit circuit 1310
Since the latch state is established by 316b and inverter 1314b, output signal P2 maintains the H level. On the other hand, the H-level output signal P2 is output from the third stage unit circuit 13.
10, the signal is inverted by the clocked inverter 1312a and further inverted again by the inverter 1314a in the same stage, so that the output signal P3 of the unit circuit 1310 in the third stage becomes H level.

Thereafter, when similar operations are repeatedly performed, the unit circuit 131 in the Y shift register 1300
0, signals P1, P2, P3,...
M and P (M + 1) are obtained by sequentially shifting the transfer start pulse DY each time the logic levels of the clock signal CLY and the inverted clock signal CLYinv change.

<Circuit Configuration from Unit Circuit to Scanning Line> Returning to FIG. 4 again, NAN as the first logical operation circuit
The D circuit 1320 is a unit circuit 131 of a stage adjacent to each other.
A NOT circuit (inverter) 1330 as a second logical operation circuit inverts the logical level of the NAND signal by the NAND circuit 1320. It is.
Therefore, the NOT circuit 1330 outputs a signal that becomes H level during a period in which pulse signals output from the unit circuits 1310 in adjacent stages overlap each other.

Here, in order to generalize and describe the output signal of the NOT circuit 1330, an integer k satisfying 1 ≦ k ≦ M is used. The NOT corresponding to the k-th unit circuit 1310 and the (k + 1) -th unit circuit 1310
The output signal from the circuit 1330 is denoted by Qk. For example, an output signal from the NOT circuit 1330 corresponding to the third-stage unit circuit 1310 and the fourth-stage unit circuit 1310 is denoted by Q3.

Next, the signal Qk output from the NOT circuit 1330 is applied to the odd-numbered (2 · k−1) -th scanning line 11.
N-channel TFT (split switch) 1 provided in 2
341 and the scanning line 112 of the even (2 · k) th row
N-channel TFT (split switch) 13 provided in
It is supplied to 42 gates. Among them, TFT1341
Is interposed between the enable signal line 1351 and one end of the (2 · k−1) -th scanning line 112, while the TFT
Reference numeral 1342 denotes an enable signal line 1352 and (2 · k)
It is interposed between one end of the scanning line 112 of the row.

Therefore, the TFTs 1341 and 1342 are
Although provided corresponding to one of the scanning lines 112, a unit circuit 1310, a NAND circuit 1320, and a NOT circuit 1330 of the Y shift register are provided for every two scanning lines 112. That is, assuming that the arrangement pitch of the scanning lines 112 is p, the unit circuit 1310, NAN
The D circuit 1320 and the NOT circuit 1330 need only be arranged at twice the pitch 2p.

On the other hand, the enable signal Enb1Y supplied to the enable signal line 1351 and the enable signal Enb2Y supplied to the enable signal line 1352
Is a clock signal CL as shown in FIG.
It has a period of two horizontal scanning periods (2H) corresponding to a half period of Y (inverted clock signal CLYinv), and in a period in which the clock signal is at the H or L level, the H level is sequentially increased with some time margin. Is the signal

<Layout from unit circuit to scanning line>
Next, an actual circuit layout from the unit circuit 1310 to the scanning line 112 will be described. FIG. 6 is a plan view showing this circuit layout, and FIG. 7 is a diagram showing this equivalent circuit.

In FIG. 6, the lowest layer is the NAND circuit 1
320, a semiconductor layer of a TFT constituting the NOT circuit 1330 and TFTs 1341 and 1342 serving as division switches. The second layer is a conductive layer made of, for example, polysilicon or the like, and is roughly divided into a gate electrode of a TFT and a scanning line 112. Therefore, an intersection between the lowermost semiconductor layer and the second conductive layer becomes a channel region of the TFT.
Subsequently, the third layer is, for example, an aluminum layer, and TF
Wiring for connecting to the source and drain of T, voltage V
ddY, VssY power supply line, enable signal line 135
1, 1352, and the like. Note that wirings made of different layers, or a source / drain of a TFT and a third
The wirings composed of layers are connected by contact holes indicated by “x” in the figure.

Now, 2 which constitutes the NAND circuit 1320
The P-channel TFTs and the two N-channel TFTs are arranged in a straight line along the X direction, which is the direction in which the scanning lines 112 extend. More specifically, in the four TFTs constituting the NAND circuit 1320, the semiconductor layers are arranged on the same straight line in which the longitudinal directions of the semiconductor layers are all X directions and parallel to the X direction. . Similarly, NOT circuit 13
In one P-channel TFT and one N-channel TFT constituting 30, the longitudinal directions of the semiconductor layers are all in the X direction, and are on the same straight line parallel to the X direction. Are arranged.

However, the four TFTs forming the NAND circuit 1320 and the two TFTs forming the NOT circuit 1330 are not located on the same straight line but are arranged on two different straight lines. Specifically, in the NAND circuit 1320 and the NOT circuit 1330, the P-channel region (P-ch) and the N-channel region (N-ch) that are separated from each other as viewed in the X direction are shared. , The scanning lines 112 are arranged in the Y direction orthogonal to the X direction, which is the extending direction of the scanning lines 112. Therefore, a signal output from the unit circuit 1310 in the X direction is output from the NAND circuit 1320.
Is bent 90 degrees in the −Y direction (upward direction), and is output.
It will be bent and output.

Note that the TFT 1341, which is a division switch,
The reason why the channel width of the channel 1342 is wider than the channel width of the TFTs forming the NAND circuit 1320 and the NOT circuit 1330 is to drive the scanning line 112 having a relatively large capacitive load and to increase the driving capability. It is.

<Operation of Electro-Optical Device> Next, the operation of the electro-optical device according to the above configuration will be described. Here, FIG. 8 is a timing chart for explaining the vertical scanning (Y side) operation of the electro-optical device, and FIG.
5 is a timing chart for explaining a horizontal scanning (X side) operation.

First, the operation on the scanning line side (Y side) will be described. As described above, the signals P1, P2, P3,..., P (M + 1) output from each stage of the unit circuit 1310,
As shown in FIG. 8, the PM is obtained by sequentially shifting the transfer start pulse DY supplied at the start of the vertical scanning every time the logic levels of the clock signal CLY and the inverted clock signal CLYinv change. Therefore, NAN
Signal Q by D circuit 1320 and NOT circuit 1330
, QM are signals P1, P2
, P (M + 1), PM, the signals Q1, Q2, Q3,.
The QM sequentially and exclusively starts at time t ₂ (time delayed from the time t _{1 at} which the transfer start pulse DY was captured by a half cycle of the clock signal CLY or the inverted clock signal CLYinv) every half cycle of the clock signal CLY. It becomes H level.

[0057] Of this, the period during which the signal Q1 becomes the H level, i.e., during the period from time t ₂ to time t _3, 1
TFT 1341 connected to the scanning line 112 of the second row, and TFT 1342 connected to the scanning line 112 of the second row
Are turned on, the enable signal Enb1Y in the period is extracted and supplied as the scanning signal G1, and the enable signal Enb2Y in the period is extracted and supplied as the scanning signal G2.

Further, during a period when the signal Q2 is at the H level, the TFT 134 connected to the third scanning line 112 is turned on.
TFTs connected to the first and fourth scanning lines 112
1342 are both turned on, the enable signal Enb1Y in this period is used as the scanning signal G3,
The enable signal Enb2Y in the period is supplied as the scanning signal G4.

Thereafter, the same operation is repeated until signal QM attains H level. When the signal QM becomes H level, the TFT 1341 connected to the (2 · M−1) th row, ie, the (m−1) th row, and the TFT 1341 connected to the (2 · M) th row, ie, the last mth row The turned-on TFTs 1342 are both turned on, and the enable signal E during the on-period is turned on.
nb1Y is supplied as the scanning signal G (m-1), and the enable signal Enb2Y in the period is supplied as the scanning signal Gm.

Next, the operation on the data line side (X side) will be described. First, attention is paid to a period in which the scanning signal G1 is at the H level. When the scanning signal G1 becomes H level, a transfer start pulse DX is supplied to the X shift register 140 as shown in FIG. This transfer start pulse DX
Is the clock signal CLX (and the inverted clock signal CL
Xinv) are sequentially shifted each time the level changes, and output as signals S1 ', S2', S3 ',..., Sn'. The signals S1 ′, S2 ′, S3 ′,.
n ′ are equal to the enable signals Enb1X and Enb1X.
By b2X, the period is shortened to the period Smp so that adjacent ones do not overlap each other, and are output as sampling control signals S1, S2, S3,..., Sn.

On the other hand, as shown in FIG. 9, the image signal VID of one system is supplied by an external circuit as shown in FIG.
To VID6, and is extended to 6 times the time axis and supplied to the liquid crystal panel 100. Here, during the period when the scanning signal G1 is at the H level, for the sake of convenience of description, if writing on the positive electrode side is performed, the image signals VID1 to VID6 are applied to the voltage LCco of the counter electrode 108.
Supplied at a higher level than m.

When the sampling control signal S1 goes high during the period in which the scanning signal G1 goes high, the TFT whose gate is connected to the scanning line 112 in the first row.
All 116 are turned on, and the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to the first block from the left. Then, the sampled image signals VID1 to VID6
Are the scanning line 112 of the first row and the six data lines 1
The TFT 116 corresponding to the intersection with 14 applies the voltage to the corresponding pixel electrode 118.

Thereafter, when the sampling control signal S2 goes to the H level, the image signals VID1 to VID are respectively applied to the six data lines 114 belonging to the second block.
D6 is sampled and these image signals VID1
To VID6 are determined by the TFT 116 corresponding to the intersection of the first scanning line 112 and the six data lines 114.
The voltage is applied to the corresponding pixel electrode 118. Hereinafter, similarly, the sampling control signals S3, S
,..., Sn sequentially become H level, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to the third, fourth,. Image signals VID1 to
VID6 is applied to the corresponding pixel electrodes 118 by the TFTs 116 corresponding to the intersections of the scanning lines 112 in the first row and the six data lines 114 belonging to the block whose sampling control signal has become H level. It will be. Thus, writing to all the pixels in the first row is completed.

Next, a period during which the scanning signal G2 is at the H level will be described. In the present embodiment, as described above, since the polarity inversion is performed in units of scanning lines, the writing on the negative electrode side is performed during this period. Therefore, the image signals VID1 to VID6 are supplied at a lower level than the voltage LCcom applied to the counter electrode 108. The other operations are the same, and the sampling control signals S1, S2, S3,..., Sn sequentially become H level, and the writing to all the pixels in the second row is completed.

Similarly, the scanning signals G3, G4,
.., Gm becomes H level, and the third line, the fourth line,
.., Writing is performed on the pixels in the m-th row. As a result, the positive-side writing is performed on the odd-numbered pixels, while the negative-side writing is performed on the even-numbered pixels. Writing over all the pixels in the m-th row is completed.

The same writing is performed in the next vertical scanning period, but at this time, the writing polarity for the pixels in each row is switched. That is, in the next vertical scanning period, writing is performed on the pixels on the negative side for the pixels on the odd-numbered rows, while writing on the positive side is performed on the pixels on the even-numbered rows. As described above, since the write polarity with respect to the pixel is switched every vertical scanning period, the DC component is not applied to the liquid crystal 105, and the occurrence of flicker or the like due to the deterioration is prevented.

<Comparison of Scan Line Drive Circuit of Present Embodiment with Conventional Scan Line Drive Circuit> Next, a comparative example of the scan line drive circuit 130 of the present embodiment, that is, the conventional scan line drive circuit 136
Will be described. Here, FIG. 14 is a block diagram showing the configuration of a conventional scanning line driving circuit 136 in comparison with FIG. 4, and FIG. 15 is a diagram showing a circuit layout of a main part in the same scanning line driving circuit. FIG. 16 is a plan view for comparison with FIG. 6, and FIG. 16 is a diagram for showing the equivalent circuit in comparison with FIG.

First, as shown in FIG. 14, a conventional scanning line driving circuit 136 is composed of a unit shift circuit 1300 having a plurality of stages of a Y shift register 1300 and an adjacent unit circuit 1
A NAND circuit 1372 for obtaining a NAND signal between the signals output from the signal 310 and a NOT circuit 13 for inverting the logical level of the NAND signal and supplying the inverted signal as a scanning signal
74.

Here, in the conventional scanning line driving circuit 136, the Y shift register 1300 is replaced by the unit circuit 1310.
Is common to the present embodiment in that a plurality of stages are provided, but the number of stages is different. That is, in the conventional scanning line driving circuit 136, the number of the unit circuits 1310 is “1” greater than the total number “m” of the scanning lines 112, whereas
In the present embodiment, the number is merely “1” larger than M which is a half value of the total number “m” of the scanning lines 112.
For this reason, the number of stages of the Y shift register and the frequency of the clock signal CLX (inverted clock signal CLYinv) are each reduced to about そ れ ぞ れ, so that the power consumption can be reduced together with the reduction in the number of stages. become.

On the other hand, in the conventional scanning line driving circuit 136,
Not only the unit circuit 1310 but also the NAND circuit 1372,
Since the NOT circuit 1374 must also be formed at the same pitch as the arrangement pitch p of the scanning lines 112, the arrangement pitch of the scanning lines 112 cannot be reduced below the arrangement pitch of these circuits. On the other hand, in the scanning line driving circuit 130 according to the present embodiment, the unit circuit 1
310, NAND circuit 1320 and NOT circuit 133
For 0, 2 for the arrangement pitch p of the scanning lines 112.
Since it is only necessary to form the scanning line 112 at a double pitch 2p, the arrangement pitch of the scanning lines 112 can be narrowed below the arrangement pitch of these circuits.

In the conventional scanning line driving circuit 136,
The final stage is a NOT circuit 1374. Therefore, in each row, the lower voltage VssY and the higher voltage VddY, which are power supply voltages, must be supplied to the NAND circuits 1372 and NOT circuits 1374 that are linearly arranged. Here, the power supply line of the power supply voltage needs a certain width to reduce the wiring resistance.
Therefore, in practice, as shown in FIG. 15, in the conventional scanning line driving circuit 136, the NAND circuit 13
72 and a region W where the NOT circuit 1374 is formed, the width Wc in the X direction along the extending direction of the scanning line 112.
Will inevitably become wider. On the other hand, in the scanning line drive circuit 130 according to the present embodiment, the last stage is merely one TFT 1341 or 1342 inserted between the enable signal line 1351 or 1352 and the scanning line 112. Therefore, there is no need to supply power supply voltage, and the enable signals Enb1Y and Enb2Y
Just supply them. In addition, since only one TFT 1341 or 1342 provided for each row of the scanning line 112 is turned on during one horizontal scanning period, the load on the enable signal lines 1351 and 1352 is small. Therefore, the enable signal lines 1351 and 1352 do not need to be as wide as the power supply line for the power supply voltage.

Further, in the present embodiment, the NAND circuit 1
The 320 and the NOT circuits 1330 are alternately arranged along the Y direction in the circuit arrangement. Therefore,
In the present embodiment, the NAND circuit 1320 and the NOT circuit 1
The width Wa in the X direction in the region where the 330 and the TFTs 1341 and 1342 are formed is
Even if the point that 2 is only an N-channel type is subtracted, it will be understood that the width becomes shorter than the width Wc when both circuits are linearly arranged along the X direction. Moreover, when two scanning line driving circuits exist at both ends of the scanning line 112 (see FIG. 3).
The effect that the width in the X direction decreases from Wc to Wa is as follows.
It works twice. Therefore, in the present embodiment, the size of the element substrate 101 in the X direction is reduced even when the size of the display region 100a is the same, so that the size of the entire panel can be reduced. In particular, forming a large number of element substrates from one mother substrate,
In the case of so-called multi-chamfering, the number of chips from the mother substrate increases as the width in the X direction is reduced, so that productivity can be improved.

The unit circuit 1 in the scanning line driving circuit
As a configuration for reducing the number of stages 310, for example, FIG.
(See the technology described in Japanese Patent Application Laid-Open No. 11-296129) is also conceivable. That is,
The scanning line driving circuit 138 firstly outputs a signal Pk output from the k-th unit circuit 1310 and a signal P (k + 1) output from the (k + 1) -th unit circuit 1310 adjacent thereto. AND signal Qk of the NAND circuit 13
25 and NOT circuit 1335,
An AND signal of the signal Qk and the enable signal Enb1Y is obtained by the NAND circuit 1381 and the NOT circuit 1391, and is output as the scanning signal G (2 · k−1), and an AND signal of the signal Qk and the enable signal Enb2Y Is obtained by the NAND circuit 1382 and the NOT circuit 1392, and is output as the scanning signal G (2 · k).

In this scanning line driving circuit 138, the number of stages of the unit circuit 1310 can be reduced as in the present embodiment, but this time, the NAND circuit 1381 (1382) and the NOT circuit 1391 (1
392) must be formed at the same pitch as the arrangement pitch p of the scanning lines 112. Therefore, with this configuration, the arrangement pitch p of the scanning lines 112 cannot be narrowed below the arrangement pitch of the NAND circuits 1381 (1382) and NOT circuits 1391 (1392).

Further, in the configuration shown in FIG.
Actually, NAND circuits 1381 (1382) and N
For the OT circuit 1391 (1392), the lower voltage VssY and the higher voltage VddY, which are power supply voltages, are supplied, respectively.
Must be powered. In addition, in this configuration, the enable signal Enb1Y (Enb2Y) is supplied to the NAND circuit 1381 provided for every two scanning lines 112.
Since the gate input is provided for all of (1382), the load on the enable signal line 1351 (1352) increases. Therefore, in this configuration,
Assuming that NAND circuit 1381 (1382) and NOT
Even when the circuits 1391 (1392) are formed at the same pitch as the arrangement pitch p of the scanning lines 112, the width Wd in the X direction in the region formed from the NAND circuit 1325 to the NOT circuits 1391 and 1392 is equal to the present embodiment. It becomes wider than it can be compared with.

<Second Embodiment> In the above-described first embodiment, only the TFT 1341 is provided for each of the odd-numbered rows and only the TFT 1342 is provided for the even-numbered rows. In addition, the arrangement pitch p of the scanning lines 112 can be easily reduced. However, in the first embodiment, the enable signal Enb1Y (Enb2Y)
When the H level portion is extracted and supplied as a scanning signal, the voltage amplitude of the scanning signal becomes smaller than the voltage amplitude of the enable signal Enb1Y (Enb2Y) due to the voltage drop caused by the ON resistance of the TFTs 1341 and 1342. I will. Therefore, in the first embodiment, it is necessary to design a circuit while paying attention to this voltage drop.

Therefore, a description will be given of a second embodiment which does not require such voltage drop. Note that the electro-optical device according to the second embodiment of the present invention is different from the above-described first embodiment only in the internal configuration of the scanning line driving circuit 130. For this reason, the second embodiment will be described focusing on this difference. FIG. 10 is a block diagram illustrating a configuration of the scanning line driving circuit 130 according to the second embodiment of the present invention.

As shown in this figure, in this embodiment, the scanning lines 112 of the odd (2 · k−1) th row are generally used.
In the above, a transmission gate 1361 is provided instead of the TFT 1341, while an even number (2 · k) is provided.
A transmission gate 1362 is provided instead of the TFT 1342 in the scanning line 112 of the row. Transmission gates 1361, 1362
It is a combination of a P-channel TFT and an N-channel TFT in a complementary manner.
The output signal of the NAND circuit 1320 is applied to the gate of T.
A NOT circuit 1 is connected to the gates of both N-channel TFTs.
330 output signals Qk are supplied respectively. Here, the signal Qk is obtained by inverting the output signal of the NAND circuit 1320 by the NOT circuit 1330.
The transmission gate 1361 provided on the odd (2 · k-1) th scanning line 112 and the transmission gate 1362 provided on the even (2 · k) th scanning line 112 are the same as the TFT 134 in the first embodiment.
As in the case of 1, 1342, they are turned on at the same time. Therefore, in the second embodiment, exactly the same operation as in the first embodiment is executed.

In the second embodiment, only two TFTs are required to form the transmission gate.
Compared with the first embodiment, the configuration is not so complicated. Therefore, the NAND circuit 1320, NOT
Circuit 1330 and transmission gate 136
1 and 1362 are formed in the scanning line 112.
The width Wb in the direction in which is extended can be easily reduced as compared with the conventional width Wc as in the first embodiment. Furthermore, in the first embodiment, the TFT 1341, the TFT 134
2 cannot be ignored, but in the second embodiment, the on-resistance of the transmission gates 1361 and 1362 is reduced to a negligible level. The drive circuit 130 can be designed.

<Applications and Modifications> The present invention is not limited to the above-described embodiments, and various applications and modifications are possible. For example, in the first and second embodiments, the NAND circuit 13
20 and an AND signal Qk from the NOT circuit 1330 divides the switch into two (TFTs 1341, 134
2 or transmission gate 1361, 136
2) at the same time, and the two enable signals En
Although two scan signals are generated from b1Y and Enb2Y, three or more split switches may be simultaneously turned on to generate three or more scan signals from three or more enable signals. . On the other hand, the pulse signal divided by the division switch may be further divided. Further, it goes without saying that not only the scanning line driving circuit 130 but also the X shift register 140 may have the same configuration. Further, in the embodiment, the normally white mode in which the maximum transmittance is obtained when no voltage is applied to the liquid crystal capacitor is described. good.

On the other hand, in the above-described embodiment, the six data lines 114 are grouped into one block, and the image data converted into six systems is applied to the six data lines 114 belonging to one block. Although VID1 to VID6 are sampled, the number of conversions and the number of data lines applied simultaneously (ie, the number of data lines constituting one block)
Is not limited to “6”. For example, if the response speed of the sampling switch 151 is sufficiently high, the image signal is serially transmitted to one image signal line without being converted in parallel, and sampling is sequentially performed for each data line 114. Is also good.

Further, assuming that the number of conversions and the number of data lines to be applied simultaneously are “3”, “12”, “24”, etc., three, 12, or 24 data lines are converted into three systems Alternatively, a configuration may be adopted in which image signals subjected to 12-system conversion, 24-system conversion, and the like are simultaneously supplied. In addition, as the conversion number,
In view of the fact that a color image signal is composed of signals related to three primary colors, a multiple of 3 is preferable in terms of simplifying control and circuits. However, in the case of a simple light modulation application such as a projector to be described later, the number need not be a multiple of three.

Further, in the embodiment, the element substrate 10
Although a glass substrate was used for SOI (Silicon On Insu
lator), a single crystal silicon film is formed on an insulating substrate such as sapphire, quartz, glass, or the like, and various elements are formed therein to form the element substrate 101.
In addition, a silicon substrate or the like may be used as the element substrate 101, and various elements may be formed here. When a silicon substrate is used in this manner, a high-speed field-effect transistor can be used as a switching element, so that high-speed operation is easier than that of a TFT. However,
Since the element substrate 101 using a silicon substrate becomes opaque, it is necessary to use the pixel electrode 118 as a reflective type by forming the pixel electrode 118 with aluminum or separately forming a reflective layer.

Further, in the above-described embodiment, the TN type liquid crystal is used, but the BTN (Bi-stable Twisted Nema
tic) type, ferroelectric type and other bistable types having memory properties, polymer dispersed types, and dyes having anisotropy in visible light absorption in the major axis direction and minor axis direction (guests) ) Is dissolved in a liquid crystal (host) having a fixed molecular arrangement, and a GH (guest host) type liquid crystal in which dye molecules are arranged in parallel with the liquid crystal molecules may be used. In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, and the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. In addition, liquid crystal molecules are aligned in a horizontal direction with respect to both substrates when no voltage is applied, while liquid crystal molecules are aligned in a vertical direction with respect to both substrates when voltage is applied. It is good also as composition.

As described above, the present invention can be applied to various types of liquid crystal and alignment system, and further, can be applied to any of transmission type, reflection type, and semi-transmission / semi-reflection type. It is. In addition, in addition to these liquid crystal display devices, the present invention provides electroluminescent devices that arrange a plurality of pixels in a matrix to emit light, and self-luminous devices such as fluorescent display tubes and plasma display panels. It is also applicable to That is, the present invention is applicable to all configurations in which a plurality of scanning lines are sequentially selected and driven.

<Electronic Equipment> Next, some electronic equipment using the liquid crystal display device according to the above-described embodiment will be described.

<Part 1: Projector> First, a projector using the above-described liquid crystal panel 100 as a light valve will be described. FIG. 11 is a plan view showing the configuration of this projector. As shown in this figure, inside the projector 2100, a lamp unit 2102 including a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 2102 is R (red) and G by three mirrors 2106 and two dichroic mirrors 2108 disposed inside.
The light is separated into three primary colors (green) and B (blue), and guided to light valves 100R, 100G, and 100B corresponding to the respective primary colors.

Here, the light valves 100R, 100G
And 100B are basically the same as the liquid crystal panel 100 according to the above-described embodiment. That is, each of the light valves 100R, 100G, and 100B functions as an optical modulator that generates an RGB primary color image. The B light has a longer optical path compared to the other R and G lights.
22, relay lens 2123 and emission lens 2124
Is conducted through a relay lens system 2121 composed of

Now, the light valves 100R, 100G,
The lights modulated by 100B respectively enter dichroic prism 2112 from three directions. And
In the dichroic prism 2112, the R and B lights are refracted at 90 degrees, while the G light goes straight.
Thus, a color image obtained by combining the primary color images is projected onto the screen 2120 via the projection lens 2114. The light valves 100R, 100R
G and 100B have dichroic mirror 2108
Accordingly, light corresponding to each of the primary colors of RGB is incident, so that it is not necessary to provide a color filter as in a direct-view panel.

<Part 2: Personal Computer> Next, an example in which the above-described liquid crystal panel 100 is applied to a display unit of a personal computer compatible with multimedia will be described. FIG. 12 is a perspective view showing the configuration of the personal computer. As shown in this figure, the main body 2210 of the computer 2200 includes a liquid crystal panel 100 used as a display unit and a read / write unit for an optical disk.
A write drive 2212, a magnetic disk read / write drive 2214, a stereo speaker 2216, and the like are provided. The keyboard 2222 and the pointing device (mouse) 2224 are configured to transmit and receive input signals, control signals, and the like to and from the main body 2210 wirelessly via infrared rays or the like. This liquid crystal panel 100
Is used as a direct view type, so that one pixel is
A dot is formed, and a color filter is provided for each pixel. A backlight unit (not shown) for ensuring visibility in a dark place is provided on the back surface of the liquid crystal panel 100.

<Part 3: Mobile Phone> Further, an example in which the above-described liquid crystal panel 100 is applied to a display unit of a mobile phone will be described. FIG. 13 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 2300 includes a plurality of operation buttons 2302, an earpiece 2304, a mouthpiece 2
306 as well as the liquid crystal panel 100 described above. A backlight unit (not shown) for ensuring visibility in a dark place is also provided on the back of the liquid crystal panel 100, similarly to the personal computer described above.
Is provided.

<Summary of Electronic Equipment> In addition to the electronic equipment described with reference to FIGS. 11, 12 and 13, a liquid crystal television, a viewfinder type / monitor direct-view type video tape recorder, Examples include a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a POS terminal, a digital still camera, and a device having a touch panel. And for these various electronic devices,
Needless to say, the liquid crystal display device according to the embodiment, the application, and the modification is applicable.

[0093]

As described above, according to the present invention, the arrangement pitch of the pixels can be easily reduced, and the area of the driving circuit can be reduced.

[Brief description of the drawings]

FIG. 1A is a perspective view illustrating an external configuration of an electro-optical device according to a first embodiment of the invention, and FIG. 1B is a cross-sectional view taken along line AA ′.

FIG. 2 is a diagram showing an equivalent circuit in a display area of the electro-optical device.

FIG. 3 is a block diagram illustrating an electrical configuration of the electro-optical device.

FIG. 4 is a block diagram illustrating a configuration of a scanning line driving circuit in the electro-optical device.

FIG. 5 is a circuit diagram showing a configuration of a transfer stage in the scanning line driving circuit.

FIG. 6 is a plan view showing a main part configuration of the scanning line driving circuit.

7 is a diagram showing an equivalent circuit of a main part configuration in FIG. 6;

FIG. 8 is a timing chart illustrating a vertical scanning operation of the electro-optical device.

FIG. 9 is a timing chart for explaining a horizontal scanning operation of the electro-optical device.

FIG. 10 is a block diagram illustrating a configuration of a scanning line driving circuit of an electro-optical device according to a second embodiment of the invention.

FIG. 11 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the liquid crystal display device according to the embodiment is applied.

FIG. 12 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal display device according to the embodiment is applied.

FIG. 13 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device according to the embodiment is applied.

FIG. 14 is a block diagram illustrating a configuration of a conventional scanning line driving circuit.

FIG. 15 is a plan view showing a configuration of a main part thereof.

16 is a diagram showing an equivalent circuit of a main part configuration in FIG.

FIG. 17 is a block diagram illustrating a configuration of a conventional scanning line driving circuit.

[Explanation of symbols]

Reference Signs List 100: liquid crystal panel 100a: display area 105: liquid crystal 108: counter electrode 112: scanning line 114: data line 116: TFT (pixel switch) 118: pixel electrode 130: scanning line driving circuit 140: X shift register 150: sampling circuit 1300 ... Y shift register 1310... Unit circuit 1320... NAND circuit 1330... NOT circuit 1341, 1342... …mobile phone

Claims (9)

[Claims] A pixel electrode provided corresponding to an intersection of a scanning line and a data line; a pixel electrode interposed between the pixel electrode and the data line;
A driving circuit for supplying a scanning signal to the scanning line for an electro-optical device including a pixel switch that is turned on and off in accordance with the scanning signal supplied to the scanning line. The output of the unit circuit of a certain stage is composed of a plurality of stages of the unit circuit for transferring the pulse signal, and the output of the unit circuit of the certain stage is connected to the shift register connected to the input of the unit circuit of the next stage. , And the pulse signal output by the next-stage unit circuit,
An arithmetic circuit that outputs a pulse signal having a width corresponding to a period in which the logic levels of both pulse signals overlap, and an enable signal in which the on-level periods do not overlap each other over the period in which the pulse signal is output by the arithmetic circuit A supplied enable signal line; and a division switch that is interposed between the one enable signal line and the one scan line and that is turned on during a period when a pulse signal is output by the arithmetic circuit. And a driving circuit for the electro-optical device. 2. A first logical operation circuit that executes a prime operation by using a pulse signal output from a unit circuit in a certain stage and a pulse signal output from a unit circuit in the next stage as inputs. 2. The driving circuit for an electro-optical device according to claim 1, further comprising: a second logical operation circuit that performs an elementary operation by using a signal output from the first logical operation circuit as an input. 3. The electric device according to claim 2, wherein the first logical operation circuit and the second logical operation circuit are arranged along a direction substantially perpendicular to the scanning line. Drive circuit for optical device. 4. The first logical operation circuit is a NAND circuit for obtaining a NAND of two input signals, and the second logical operation circuit is a N circuit for obtaining a negative of an input signal.
3. The driving circuit according to claim 2, wherein the driving circuit is an OT circuit. 5. The transistor according to claim 1, wherein the division switch is a transistor of one of an N-channel type and a P-channel type, and a pulse signal output by the arithmetic circuit is used as a gate input. The driving circuit for an electro-optical device according to claim 1. 6. The split switch is a transmission gate in which N-channel and P-channel transistors are combined, and a pulse signal output by the arithmetic circuit is used as a gate input. 2. The driving circuit for an electro-optical device according to claim 1. 7. A pixel electrode provided corresponding to the intersection of a scanning line and a data line, and interposed between the pixel electrode and the data line;
A driving circuit for supplying a scanning signal to the scanning line for an electro-optical device including a pixel switch that is turned on and off in accordance with the scanning signal supplied to the scanning line. The output of the unit circuit of a certain stage is composed of a plurality of stages of the unit circuit for transferring the pulse signal, and the output of the unit circuit of the certain stage is connected to the shift register connected to the input of the unit circuit of the next stage. , And the pulse signal output by the next-stage unit circuit,
An arithmetic circuit that outputs a pulse signal having a width corresponding to a period in which the logic levels of both pulse signals overlap each other; and an enable signal in which on-level periods do not overlap each other over a period in which the pulse signal is output by the arithmetic circuit. A supplied enable signal line, a split switch that is interposed between one enable signal line and one scan line, and that is turned on during a period when a pulse signal is output by the arithmetic circuit; A driving circuit for an electro-optical device, comprising: a data line driving circuit for supplying an image signal via a data line to a pixel electrode corresponding to an intersection with a connected scanning line. 8. A pixel electrode provided corresponding to the intersection of a scanning line and a data line, and interposed between the pixel electrode and the data line;
A pixel switch that is turned on and off in accordance with the scanning signal supplied to the scanning line; and a unit circuit that transfers an input pulse signal every time the level of the clock signal changes. A shift register connected to the input of the next-stage unit circuit, a pulse signal output by a certain-stage unit circuit, and a pulse signal output by the next-stage unit circuit,
An arithmetic circuit that outputs a pulse signal having a width corresponding to a period in which the logic levels of both pulse signals overlap each other; and an enable signal in which on-level periods do not overlap each other over a period in which the pulse signal is output by the arithmetic circuit. A supplied enable signal line, a split switch inserted between one enable signal line and one scan line, and turned on during a period when a pulse signal is output by the arithmetic circuit; An electro-optical device, comprising: a data line driving circuit for supplying an image signal via a data line to a pixel electrode corresponding to an intersection with a connected scanning line. 9. An electronic apparatus comprising the electro-optical device according to claim 8 as a display unit.