JP4583123B2 - 高周波モジュール - Google Patents
高周波モジュール Download PDFInfo
- Publication number
- JP4583123B2 JP4583123B2 JP2004281662A JP2004281662A JP4583123B2 JP 4583123 B2 JP4583123 B2 JP 4583123B2 JP 2004281662 A JP2004281662 A JP 2004281662A JP 2004281662 A JP2004281662 A JP 2004281662A JP 4583123 B2 JP4583123 B2 JP 4583123B2
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- Prior art keywords
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
接地用導体パターン62や、入出力裏面電極63と電気的に接続される。
2 絶縁基板
2a〜2f 絶縁層
3 平面導体層
4、4a1,4a2,4a3 ビア導体
5 弾性表面波素子
10 圧電基板
11a、11b 入出力用端子
12 櫛歯電極
13 リング状接地用端子
14a、14b 入出力用電極
15 リング状接地用電極
16 導電性接着材
Claims (7)
- 複数の絶縁層を積層してなる絶縁基板と、該絶縁基板の表面および内部に形成された平面導体層と、前記絶縁層を貫通するように形成されたビア導体とを具備するモジュール基板の表面に、弾性表面波素子が実装されており、該弾性表面波素子は、誘電体基板の裏面に、櫛歯電極と、一対の入出力用端子と、該一対の入出力用端子および前記櫛歯電極の周囲に配置されたリング状接地用端子とが被着形成されており、前記モジュール基板の表面には、一対の入出力用電極と、リング状接地用電極とが被着形成されており、前記一対の入出力用端子と前記一対の入出力用電極とを、前記リング状接地用端子と前記リング状接地用電極とを、それぞれ導電性接着材によって接着して、前記弾性表面波素子を前記モジュール基板へ実装してなる高周波モジュールにおいて、
前記一対の入出力用電極のうちの第1の入出力用電極が、該第1の入出力用電極と直接接続されたビア導体を含む複数の前記ビア導体を経由して前記モジュール基板裏面に形成された入力用または出力用導体パターンと電気的に接続されており、前記一対の入出力用電極のうちの第2の入出力用電極が、該第2の入出力用電極と直接接続されたビア導体を含む複数の前記ビア導体および前記モジュール基板の内部に形成された前記平面導体層を介して、前記モジュール基板の表面に形成されて電子部品または半導体部品が接続された前記平面導体層に電気的に接続されており、前記複数のビア導体は、平面的にみて、互いに異なる位置に設けられており、かつ前記第1の入出力用電極と直接接続されたビア導体および前記第2の入出力用電極と直接接続されたビア導体の長さが前記モジュール基板の厚さの20%以下であることを特徴とする高周波モジュール。 - 前記リング状接地用電極が、該リング状接地用電極と直接接続されたビア導体を含む複数の前記ビア導体を経由して前記モジュール基板裏面に形成された接地用導体パターンと電気的に接続されていることを特徴とする請求項1記載の高周波モジュール。
- 前記複数のビア導体のうち、前記第1および第2の入出力用電極ならびに前記リング状接地用電極と直接接続されたビア導体以外のビア導体の長さが、前記モジュール基板の厚さの60%以下であることを特徴とする請求項1または請求項2のいずれか記載の高周波モジュール。
- 前記複数のビア導体のうち、隣接するビア導体の中心同士が、該ビア導体の直径以上離間していることを特徴とする請求項1乃至請求項3のいずれか記載の高周波モジュール。
- 前記絶縁層の厚みが150μm以下であることを特徴とする請求項1乃至請求項4のい
ずれか記載の高周波モジュール。 - 前記ビア導体の直径が50〜200μmの大きさであることを特徴とする請求項5に記載の高周波モジュール。
- 前記モジュール基板が、X−Y方向の焼成収縮量がZ方向の焼成収縮量よりも小さくなるように焼成されたものであることを特徴とする請求項1乃至請求項6のいずれか記載の高周波モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004281662A JP4583123B2 (ja) | 2004-09-28 | 2004-09-28 | 高周波モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004281662A JP4583123B2 (ja) | 2004-09-28 | 2004-09-28 | 高周波モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006100361A JP2006100361A (ja) | 2006-04-13 |
JP4583123B2 true JP4583123B2 (ja) | 2010-11-17 |
Family
ID=36239920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004281662A Expired - Fee Related JP4583123B2 (ja) | 2004-09-28 | 2004-09-28 | 高周波モジュール |
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JP (1) | JP4583123B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5135769B2 (ja) * | 2006-11-13 | 2013-02-06 | パナソニック株式会社 | 弾性表面波デバイスの製造方法 |
CN113411069A (zh) * | 2021-06-03 | 2021-09-17 | 成都频岢微电子有限公司 | 一种体声波滤波器装置及提升带外抑制的方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302209A (ja) * | 1991-03-29 | 1992-10-26 | Clarion Co Ltd | 中空素子構造 |
JPH05335747A (ja) * | 1992-05-27 | 1993-12-17 | Matsushita Electric Ind Co Ltd | セラミック多層基板 |
JPH0786743A (ja) * | 1993-09-10 | 1995-03-31 | Matsushita Electric Ind Co Ltd | 多層セラミック基板の製造方法 |
JP2001189550A (ja) * | 1999-12-28 | 2001-07-10 | Kyocera Corp | 回路基板 |
JP2001339166A (ja) * | 2000-05-30 | 2001-12-07 | Kyocera Corp | 多層配線基板及びその製造方法 |
JP2002270989A (ja) * | 2001-03-09 | 2002-09-20 | Matsushita Electric Ind Co Ltd | セラミック電子部品およびその製造方法 |
JP2004214469A (ja) * | 2003-01-07 | 2004-07-29 | Hitachi Ltd | 電子デバイスおよびその製造方法 |
JP2004214582A (ja) * | 2003-01-09 | 2004-07-29 | Mitsubishi Electric Corp | 低温焼成多層セラミック基板の放熱構造 |
-
2004
- 2004-09-28 JP JP2004281662A patent/JP4583123B2/ja not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302209A (ja) * | 1991-03-29 | 1992-10-26 | Clarion Co Ltd | 中空素子構造 |
JPH05335747A (ja) * | 1992-05-27 | 1993-12-17 | Matsushita Electric Ind Co Ltd | セラミック多層基板 |
JPH0786743A (ja) * | 1993-09-10 | 1995-03-31 | Matsushita Electric Ind Co Ltd | 多層セラミック基板の製造方法 |
JP2001189550A (ja) * | 1999-12-28 | 2001-07-10 | Kyocera Corp | 回路基板 |
JP2001339166A (ja) * | 2000-05-30 | 2001-12-07 | Kyocera Corp | 多層配線基板及びその製造方法 |
JP2002270989A (ja) * | 2001-03-09 | 2002-09-20 | Matsushita Electric Ind Co Ltd | セラミック電子部品およびその製造方法 |
JP2004214469A (ja) * | 2003-01-07 | 2004-07-29 | Hitachi Ltd | 電子デバイスおよびその製造方法 |
JP2004214582A (ja) * | 2003-01-09 | 2004-07-29 | Mitsubishi Electric Corp | 低温焼成多層セラミック基板の放熱構造 |
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JP2006100361A (ja) | 2006-04-13 |
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