JP4566266B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP4566266B2
JP4566266B2 JP2009096178A JP2009096178A JP4566266B2 JP 4566266 B2 JP4566266 B2 JP 4566266B2 JP 2009096178 A JP2009096178 A JP 2009096178A JP 2009096178 A JP2009096178 A JP 2009096178A JP 4566266 B2 JP4566266 B2 JP 4566266B2
Authority
JP
Japan
Prior art keywords
sealing body
lead
semiconductor device
manufacturing
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2009096178A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009158978A (ja
JP2009158978A5 (enrdf_load_stackoverflow
Inventor
忠敏 団野
博美 田谷
嘉治 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009096178A priority Critical patent/JP4566266B2/ja
Publication of JP2009158978A publication Critical patent/JP2009158978A/ja
Publication of JP2009158978A5 publication Critical patent/JP2009158978A5/ja
Application granted granted Critical
Publication of JP4566266B2 publication Critical patent/JP4566266B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2009096178A 2009-04-10 2009-04-10 半導体装置の製造方法 Expired - Lifetime JP4566266B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009096178A JP4566266B2 (ja) 2009-04-10 2009-04-10 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009096178A JP4566266B2 (ja) 2009-04-10 2009-04-10 半導体装置の製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2003396996A Division JP2005159103A (ja) 2003-11-27 2003-11-27 半導体装置およびその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009226011A Division JP4535513B2 (ja) 2009-09-30 2009-09-30 半導体装置

Publications (3)

Publication Number Publication Date
JP2009158978A JP2009158978A (ja) 2009-07-16
JP2009158978A5 JP2009158978A5 (enrdf_load_stackoverflow) 2009-11-19
JP4566266B2 true JP4566266B2 (ja) 2010-10-20

Family

ID=40962578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009096178A Expired - Lifetime JP4566266B2 (ja) 2009-04-10 2009-04-10 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP4566266B2 (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5947107B2 (ja) * 2012-05-23 2016-07-06 ルネサスエレクトロニクス株式会社 半導体装置
JP6986539B2 (ja) * 2019-11-25 2021-12-22 Ｔｏｗａ株式会社 樹脂成形済リードフレームの製造方法、樹脂成形品の製造方法、及びリードフレーム

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220361A (ja) * 1985-03-26 1986-09-30 Matsushita Electric Ind Co Ltd 電子部品の捺印及びフレ−ム切断機
JPH06232195A (ja) * 1993-01-28 1994-08-19 Rohm Co Ltd 半導体装置の製造方法およびリードフレーム
JP3547704B2 (ja) * 2000-06-22 2004-07-28 株式会社三井ハイテック リードフレーム及び半導体装置
JP3660861B2 (ja) * 2000-08-18 2005-06-15 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003031753A (ja) * 2001-07-19 2003-01-31 Sony Corp 半導体装置及びその製造方法
JP2003158234A (ja) * 2001-11-21 2003-05-30 Hitachi Ltd 半導体装置及びその製造方法
JP3638136B2 (ja) * 2001-12-27 2005-04-13 株式会社三井ハイテック リードフレームおよびこれを用いた半導体装置

Also Published As

Publication number Publication date
JP2009158978A (ja) 2009-07-16

Similar Documents

Publication Publication Date Title
US10998288B2 (en) Method of manufacturing a semiconductor device
JP4566266B2 (ja) 半導体装置の製造方法
JP5184558B2 (ja) 半導体装置
JP5512784B2 (ja) 半導体装置の製造方法
JP4535513B2 (ja) 半導体装置
JP2014112714A (ja) 半導体装置
JP2009231322A (ja) 半導体装置の製造方法
JP2006216993A (ja) 樹脂封止型半導体装置
JP2005236127A (ja) 半導体装置およびその製造方法
JP2009176987A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090410

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090930

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20090930

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091027

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20091021

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091228

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100223

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100421

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100518

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100528

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100701

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100720

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100803

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4566266

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130813

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term