JP4544902B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP4544902B2
JP4544902B2 JP2004129256A JP2004129256A JP4544902B2 JP 4544902 B2 JP4544902 B2 JP 4544902B2 JP 2004129256 A JP2004129256 A JP 2004129256A JP 2004129256 A JP2004129256 A JP 2004129256A JP 4544902 B2 JP4544902 B2 JP 4544902B2
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JP
Japan
Prior art keywords
main surface
via hole
wiring layer
semiconductor chip
semiconductor substrate
Prior art date
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Expired - Fee Related
Application number
JP2004129256A
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English (en)
Japanese (ja)
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JP2005311215A (ja
JP2005311215A5 (https=
Inventor
工次郎 亀山
彰 鈴木
芳央 岡山
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication date
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Priority to JP2004129256A priority Critical patent/JP4544902B2/ja
Publication of JP2005311215A publication Critical patent/JP2005311215A/ja
Publication of JP2005311215A5 publication Critical patent/JP2005311215A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2004129256A 2004-04-26 2004-04-26 半導体装置及びその製造方法 Expired - Fee Related JP4544902B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004129256A JP4544902B2 (ja) 2004-04-26 2004-04-26 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004129256A JP4544902B2 (ja) 2004-04-26 2004-04-26 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2005311215A JP2005311215A (ja) 2005-11-04
JP2005311215A5 JP2005311215A5 (https=) 2007-06-07
JP4544902B2 true JP4544902B2 (ja) 2010-09-15

Family

ID=35439596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004129256A Expired - Fee Related JP4544902B2 (ja) 2004-04-26 2004-04-26 半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JP4544902B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5194537B2 (ja) * 2007-04-23 2013-05-08 株式会社デンソー 半導体装置およびその製造方法
TWI394260B (zh) * 2007-10-31 2013-04-21 群成科技股份有限公司 具有多晶粒之半導體元件封裝結構及其方法
JP2009295676A (ja) * 2008-06-03 2009-12-17 Oki Semiconductor Co Ltd 半導体装置及びその製造方法
JP2010245292A (ja) * 2009-04-06 2010-10-28 Panasonic Corp 光学デバイス、電子機器、及びその製造方法
US8853072B2 (en) * 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
JP6012998B2 (ja) * 2012-03-29 2016-10-25 芝浦メカトロニクス株式会社 プラズマ処理方法
KR102673730B1 (ko) * 2019-11-07 2024-06-10 삼성전자주식회사 반도체 소자 및 이를 구비한 반도체 패키지
US11676872B2 (en) * 2020-06-10 2023-06-13 Menlo Microsystems, Inc. Materials and methods for passivation of metal-plated through glass vias
CN118830080A (zh) * 2022-12-16 2024-10-22 京东方科技集团股份有限公司 功能基板及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3494100B2 (ja) * 2000-01-11 2004-02-03 富士通株式会社 半導体装置及びその実装方法
JP3530149B2 (ja) * 2001-05-21 2004-05-24 新光電気工業株式会社 配線基板の製造方法及び半導体装置
JP4212293B2 (ja) * 2002-04-15 2009-01-21 三洋電機株式会社 半導体装置の製造方法
JP2003347471A (ja) * 2002-05-24 2003-12-05 Fujikura Ltd 半導体装置及びその製造方法

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Publication number Publication date
JP2005311215A (ja) 2005-11-04

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