JP4538436B2 - Game machine and control method thereof - Google Patents

Description

  The present invention relates to a gaming machine that controls processing of an image to be displayed during a game and a control method thereof, and more particularly to a gaming machine that performs update processing together with image display processing and a control method thereof.

  Some gaming machines such as pachinko machines are provided with an effect control unit separately from the control unit of the main body, and the effect control unit executes the effect control in response to an instruction from the control unit of the main body. In this effect control unit, the CPU performs the entire process, and includes a VDP that is a processor that executes a write / read process to the VRAM, thereby executing the effect control by dividing the processing load.

  In this VDP, an image can be displayed by reading a character image from a CGROM which is a nonvolatile memory and writing it on the VRAM. Here, since the access speed to the VRAM is faster, the necessary image is written on the VRAM and moved to the frame buffer on the VRAM to increase the display speed (for example, see Patent Document 1 below). .

Japanese Patent Laid-Open No. 2005-177088

  However, when image data is transferred to the VRAM in advance, the image data written on the VRAM may be damaged due to static electricity or impact. In the case of a frame buffer or work memory that is always used for image display, writing is constantly repeated, so even if it is damaged, it returns to its original state. However, when it is held in advance for display on the VRAM, it is not normally updated as it is.

  At this time, when display processing is performed using image data stored in advance in the VRAM, the use of the damaged image is repeated. Therefore, the initial setting must be repeated every time the image is damaged. Further, until the setting is reset, the game must be repeated in a damaged state, which may cause discomfort to the user.

  Therefore, it is conceivable to update the image data on the VRAM regardless of the presence or absence of breakage, but executing the update process while maintaining the gaming state is difficult to balance, and the display image does not appear unnatural. If you choose to update when there is no timing, the update does not progress easily. As a result, if the image to be restored is not restored indefinitely, for example, if the image that appears frequently is damaged, it will be displayed on the screen many times before restoration, giving the player a sense of discomfort and stress I have to play games with feeling.

  In addition, what is originally necessary for playing a game is display processing, and it is not preferable to proceed only with update processing while suppressing this display processing. In a normal case, if the update process is allowed to proceed without giving priority to the display process in the demonstration, the player will continue to feel uncomfortable. On the other hand, even if an update is necessary, if you proceed with the update process while considering the display process, you will feel that something is wrong while you are waiting, even though it will be updated soon. You must continue playing.

  In order to eliminate the above-described problems caused by the conventional technology, the present invention further reduces the player's uncomfortable feeling by further proceeding with the update process at the required image or timing while performing the image display process and the update process in parallel. An object of the present invention is to provide a game machine that can be used and a control method thereof.

The gaming machine according to the present invention controls the display processing processor to transfer the image data stored in the nonvolatile memory to the resident data area of the VRAM used for image display, and the transfer means transfers the image data. Determination means for determining whether or not the image data in the resident data area is preferentially updated, and at a timing when the determination means determines that the image data is not preferentially updated. After the start of a certain frame period, the display control means for causing the display processor to display the image data stored in the resident data area of the VRAM , and the timing determined to be preferentially updated by the determination means the image data transferred to the resident data area of the VRAM by the transfer means, the non-volatile memory In the stored image data, and a update control means for updating the display processing processor, the determining unit, from the circling the update of image data transferred to the resident data area of said VRAM, the next image A timer for measuring a time until the data update is completed, and after the update of the image data is completed, it is determined that the timing is not preferentially updated until the timer counts a predetermined time. And

The front Symbol judging means, for each cycle number of times counted by certain of said frame, and judging the timing for updating the image data transferred preferentially by said transfer means.

The front Symbol judging means may be periodically and a timing that does not preferentially update the timing of updating preferentially alternately.

The front Symbol judging means may be periodic timing of updating preferentially after multiple preferentially not update timing.

The front Symbol judging means, when the moving image data of symbols of said image data to be displayed, and judging the preferentially not update timing.

The front Symbol judging means, when the moving image data of symbols of said image data to be displayed, and judging the preferentially not update timing.

In addition, the determination unit counts the number of frames until the update of the image data completes a cycle from the start of the movement of the design image data among the displayed image data. It is determined that the image data transferred by the transfer means is preferentially updated.

The gaming machine according to the present invention controls a display processing processor to transfer image data stored in a nonvolatile memory to a resident data area of a VRAM used for image display, and a section on the image display. Counting means for counting a certain number of frames, and measuring means for preferentially updating the image data in the resident data area transferred by the transferring means for every fixed period, and after the start of the frame period, Display control means for causing the display processing processor to display the image data stored in the resident data area of the VRAM , and display processing by the display control means when the timing for preferential update is measured by the measurement means. from after until period end of said frame, resident data area of the VRAM by the transfer means The transferred image data, the image data stored in the nonvolatile memory includes an update control means for updating the display processing processor, said measuring means, resident data area of VRAM used in the image display A timer that counts the time from one update of the image data transferred to the next update of the next image data, and after the update of the image data completes, the timer sets a predetermined time. Until the time is counted, it is determined that the timing is not preferentially updated.

In addition, the measurement unit alternately cycles the timing for preferential updating and the timing for not preferentially updating.

The measuring means may cycle the timing of preferential updating after a plurality of times of non-preferential updating.

The measuring means may determine that the timing is not preferentially updated when the symbol image data is moving among the displayed image data.

In addition, the measurement unit counts the number of frames until the update of the image data completes from the start of the movement of the design image data among the displayed image data, and at regular intervals. It is determined that the image data transferred by the transfer means is preferentially updated.

The gaming machine control method according to the present invention includes a transfer step of controlling the display processing processor to transfer the image data stored in the nonvolatile memory to a resident data area of a VRAM used for image display; An image display is performed at a determination step for determining whether or not the image data transferred to the resident data area by the transfer step is preferentially updated, and at a timing at which the determination step determines that the image data is not preferentially updated. After the start of the frame period, which is the upper section, it is determined that the image data stored in the resident data area of the VRAM is preferentially updated by the display control step for causing the display processing processor to perform display processing and the determination step when in the timing, the image data transferred to the resident data area of the VRAM by the transfer process, the non-volatile components From the image data stored in the sexual memory includes an update control step of updating the display processing processor, wherein the determination step is to round the update of image data transferred to the resident data area of said VRAM, The time until the next update of the image data is counted by a timer, and after the update of the image data is completed, it is determined that the timing is not preferentially updated until the timer times a predetermined time. It is characterized by.

The gaming machine control method according to the present invention also includes a transfer step of controlling the display processor to transfer the image data stored in the nonvolatile memory to a resident data area of a VRAM used for image display, and an image A measurement step of counting the number of frames that are display intervals and preferentially updating the image data in the resident data area transferred by the transfer means for every fixed number of cycles; After the start of the period, when the display control process for causing the display processor to display the image data stored in the resident data area of the VRAM and the timing for preferential update by the measurement process are measured, the display between after displaying processed by the control step, until the period ends of the frame, the VRAM by the transfer process The image data transferred to the resident data area, the image data stored in the nonvolatile memory includes an update control step of updating the display processing processor, wherein the measuring step is used for the image display VRAM After the update of the image data transferred to the resident data area is cycled, the timer measures the time from the cycle of the update of the next image data until the cycle of the update of the image data. Until the time is counted, it is determined that the timing is not preferentially updated.

  According to the above configuration, since the priority update data is updated more frequently than the non-priority update data, even when image data is damaged, the time for waiting for the recovery of the priority update data is shortened. Or it can be made to have already recovered by the time the image is displayed next time. As a result, for example, frequently used image data can be restored early and damage images can be prevented from being displayed many times. For example, important image data can be restored early and the player can play an important role. Can reduce the chances of lowering morale.

  In addition, according to the above configuration, not only combining display processing and update processing, but also providing a frame that prioritizes update processing as necessary by prioritizing update processing by frame or prioritizing display processing. The damaged image can be quickly restored, and if necessary, a frame that prioritizes display processing can be provided to give priority to a game without a sense of incongruity.

  According to the gaming machine and the control method thereof according to the present invention, the image display process and the update process are performed in parallel to advance the update process while maintaining the game process. In some cases, priority is given to the display processing, thereby producing an effect of reducing the player's uncomfortable feeling.

(Embodiment)
Exemplary embodiments of a gaming machine and a control method thereof according to the present invention will be explained below in detail with reference to the accompanying drawings. In the following description, a pachinko gaming machine will be described as an example of the gaming machine.

(Basic configuration of pachinko machine)
FIG. 1 is a front view showing an example of a game board of a pachinko gaming machine as a gaming machine of the present invention. A game ball launched by driving a launching unit (see FIG. 2) arranged at a lower position of the game board 101 ascends between the rails 102a and 102b and reaches an upper position of the game board 101, and then the game area 103 Fall inside. A plurality of nails (not shown) are provided in the game area 103, and a game ball is dropped in various directions, and a windmill or a prize opening that changes the fall direction of the game ball is placed in the middle of the fall. Is arranged.

  A symbol display unit 104 is arranged at the center of the game area 103 of the game board 101. For example, a liquid crystal display (LCD) is used as the symbol display unit 104. Below the symbol display unit 104, a start winning port 105 for starting winning is arranged. Winning gates 106 are arranged on the left and right of the symbol display unit 104, respectively. The winning gate 106 is provided to detect the passing of a game ball and perform a lottery to open the start winning opening 105 for a predetermined time. A normal winning opening 107 is disposed on the side of the symbol display unit 104 or below. When a game ball wins the normal winning opening 107, the number of winning balls (for example, 10) at the time of the normal winning is paid out. At the bottom of the game area 103, there is provided a collection port 108 for collecting game balls that have not won any winning ports.

  The symbol display unit 104 described above starts a variation in the display of a plurality of symbols when a game ball is won at a specific winning opening (at the time of starting winning), and the symbol stops after a predetermined time. When the specific symbols (for example, “777”) are aligned at the time of the stop, a big hit state is obtained. In the big hit state, the large winning opening 109 located below repeats a predetermined period (for example, 15 rounds) of opening for a certain period, and pays out the number of winning balls corresponding to the winning game balls.

  FIG. 2 is a block diagram showing the internal configuration of the control unit of the pachinko gaming machine. The control unit 200 includes a plurality of control units. In the illustrated example, a main control unit 201, an effect control unit 202, a CGROM 203, a VRAM 204, and a prize ball control unit 205 are included. The main control unit 201 controls basic operations related to the game of the pachinko gaming machine. The production control unit 202 controls the production operation during the game. The prize ball control unit 205 controls the number of prize balls to be paid out.

  Based on the program data stored in the ROM 212, the main control unit 201 includes a CPU 211 that executes basic processing as the game content progresses, a RAM 213 that functions as a data work area when the CPU 211 performs arithmetic processing, and the like. The The main control unit 201 realizes its function by, for example, a main board.

  On the input side of the main control unit 201, a start winning port detection unit 221 that detects a winning ball that has won a winning winning port 105, a gate detection unit 222 that detects a game ball that has passed through the winning gate 106, and a normal win An ordinary winning opening detection unit 223 that detects a game ball won in the mouth 107 and a large winning opening detection unit 224 that detects a winning ball won in the big winning opening 109 are connected. These detection units can be configured using proximity switches or the like.

  A prize winning opening / closing part 231 is connected to the output side of the main control part 201, and the opening / closing of the prize winning opening / closing part 231 is controlled. The special prize opening / closing unit 231 has a function of opening the special prize opening 109 for a certain period of time when a big hit is made, and is configured using a solenoid or the like. This jackpot is pre-programmed to occur with a predetermined probability based on the generated random number.

  The effect control unit 202 controls the change display of the symbol and the effect on the symbol display unit 104 during the game based on the program data stored in the ROM 242. The effect control unit 202 includes a VDP 240, a CPU 241 that executes the effect process, a RAM 243 that functions as a data work area when the CPU 241 performs an arithmetic process, and the like. Further, it is connected to the CGROM 203 and the VRAM 204. The effect control unit 202 realizes its function by, for example, an effect board. The VDP 240 has a display device control function and a high-speed drawing function for displaying an image, operates in accordance with an instruction from the CPU 241, performs a drawing process, and displays the drawn image on the symbol display unit 104.

  The effect control unit 202 receives various data during the game from the main control unit 201 and performs display control during the game. On the output side of the effect control unit 202, the above-described symbol display unit (LCD) 104, the VRAM 204, and the lamp control unit 251 are connected. The effect control unit 202 displays, for the symbol display unit (LCD) 104, the contents of the effect during the game, such as movement display of symbols, reach (a state where two of the three symbols are aligned), and a big hit Generate and output various display information. In addition, the effect control unit 202 outputs data for performing lighting control and the like for various lamps 262 provided on the game board 101, the base frame, and the like to the lamp control unit 251.

  The CGROM 203 is a so-called character generator, and stores different display target images (display element images) in advance. The CGROM 203 is composed of a mask ROM, an EEPROM, and the like, and is a memory element that operates relatively slowly. The CGROM 203 stores special symbol image data and character image data.

  The VRAM 204 is composed of SRAM, DRAM, etc., and is a memory for storing a display target image. The VRAM 204 has a higher operation speed than the CGROM 203. Functionally, the VRAM 204 includes a frame buffer 501 for storing a display target image, a work area 502, and an image data resident area 510, as shown in FIG.

  The prize ball control unit 205 performs prize ball control based on the program data stored in the ROM 282. The prize ball control unit 205 includes a CPU 281 that executes prize ball control processing, a RAM 283 that functions as a data work area when the CPU 281 performs arithmetic processing, and the like. The prize ball control unit 205 realizes its function by a prize ball board, for example.

  The winning ball control unit 205 performs control for paying out the number of winning balls at the time of winning a prize to the connected paying unit 291. In addition, an operation of launching a game ball with respect to the launch unit 292 is detected, and the launch of the game ball is controlled. The payout unit 291 includes a motor for paying out a predetermined number from the game ball storage unit. The winning ball control unit 205 controls the paying unit 291 to pay out the number of winning balls corresponding to the game balls won in each winning port (start winning port 105, normal winning port 107, large winning port 109). Do. The launcher 292 launches a game ball for a game, and includes a sensor that detects a game operation by the player, a solenoid that launches the game ball, and the like. When the prize ball control unit 205 detects a gaming operation by the sensor of the launching unit 292, the game ball 103 is intermittently fired by driving a solenoid or the like in response to the detected gaming operation, and the gaming area 103 of the gaming board 101 is played. A game ball is sent out.

  The main control unit 201, the effect control unit 202, and the prize ball control unit 205 configured as described above are provided on different printed circuit boards (main board, effect board, and prize ball board). For example, the prize ball control unit 205 can be provided on the same printed circuit board as the main control unit 201.

(Basic operation of pachinko machines)
An example of the basic operation of the pachinko gaming machine having the above configuration will be described. Control during the game is performed by the CPU 211 of the main control unit 201, and the winning status of the game balls for each winning opening is output to the winning ball control unit 205. The winning ball control unit 205 has the number of winning balls corresponding to the winning status. Make a withdrawal.

  Each time a game ball wins at the start winning opening 105, a corresponding control signal is output to the effect control unit 202, and the effect control unit 202 repeatedly displays and stops the symbols on the symbol display unit 104. . When the occurrence of the jackpot is determined, a corresponding control signal is output to the effect control unit 202, and the effect control unit 202 is stopped in alignment with a predetermined symbol. At the same time, control for opening the special winning opening 109 is performed. The effect control unit 202 performs various effect displays on the symbol display unit 104 in addition to the symbol variation display during the jackpot occurrence period and during the reach until the jackpot occurrence, at the time of reach notice, or the like. . In addition, effects such as specific driving for various types of accessories and changing the display state of the lamp 262 are performed.

  When a big hit occurs, the big winning opening 109 is opened a plurality of times. For example, 15 rounds are repeatedly executed as one open is one round. The period of one round is set when, for example, 10 game balls are won or a predetermined period (for example, 30 seconds). At this time, the prize ball control unit 205 pays out with the number of 15 prize balls per prize for one ball game ball to the big prize opening 109. After the jackpot is over, the jackpot state is canceled and the normal gaming state is restored.

(Functional configuration of production control unit)
FIG. 3 is a block diagram showing a functional configuration of the effect control unit. The effect control unit 202 shown in FIG. 2 includes a VDP 240, a CPU 241, a ROM 242, and a RAM 243, and is connected to the symbol display unit 104, the CGROM 203, the VRAM 204, and the like.

  The VDP 240 includes a CPU I / F 301, an attribute RAM 302, a CG bus I / F 303, a drawing control unit 304, a VRAM I / F 305, a data transfer control unit 306, and a display driving unit 307, which are connected by an internal bus.

  The CPU 241 executes an operation program stored in the ROM 242 according to an instruction from the main control unit 201 and controls the display operation. Specifically, the CPU 241 has a transfer function that causes the VDP 240 to transfer the image data stored in the CGROM 203 to the VRAM 204. This transfer function operates as an update control function for updating image data by transferring it to the VRAM 204 when image data is stored.

  Further, the CPU 241 has a sorting function for sorting into priority update data and non-priority update data. Further, the CPU 241 has a display control function for controlling the VDP 240 to form a display target image using image data on the VRAM 204. Further, the CPU 241 has a determination function for determining whether or not it is time to preferentially update. In addition, a measurement function is provided that counts the number of frames that are sections on the image display and sets the timing to preferentially update every certain period.

  A CPU I / F 301 is a communication I / F with the CPU 241. An attribute RAM 302 is a RAM that can be accessed by the CPU 241 via the CPU I / F 301. The attribute RAM 302 is an attribute that is a parameter for drawing a character, data that specifies image data to be transferred from the CGROM 203 to the VRAM 204, and the CPU 241. This is a memory for storing instructions (commands) from.

  The CG bus I / F 303 is a bus I / F for performing communication with the CGROM 203. The drawing control unit 304 is for generating a display target image by performing various effect processing on the character read from the CGROM 203 and developing (drawing) it at an arbitrary position, and is set in the attribute RAM 302. A function for analyzing attributes, an image processing function for performing translucent processing, luminance processing, enlargement / reduction processing, a function for generating an address of a development position, a function for writing display target data to the VRAM 204 via the VRAM I / F 305, etc. .

  The VRAM I / F 305 is an I / F for performing communication with the VRAM 204. The data transfer control unit 306 controls data transfer between the VDP 240 and an external circuit and between internal circuits of the VDP 240. In particular, in this embodiment, transfer / decompression / development of image data from the CGROM 203 to the VRAM 204 is executed.

  The display driving unit 307 accesses the VRAM 204 (the frame buffer area in which the image data of the display target image is stored) via the VRAM I / F 305 to read display data (RGB luminance signal), and uses the RGB luminance signal. A driving signal for displaying an image to be defined is supplied to drive the symbol display unit 104 composed of an LCD. The display driving unit 307 generates and supplies a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and the like in order to synchronize the operation timings of the CPU 241, the VDP 240, and the symbol display unit 104 with respect to image display.

(Processing with priority update data and non-priority update data)
FIG. 4 is a timing chart showing operations of display processing and update processing by VDP. First, at time 400, the power is turned on. After the power is turned on, the initial setting process is executed, and the initial setting ends at time 410. In this initial setting, first, image data such as symbols stored in the non-volatile memory CGROM 203 is transferred. The transfer destination is the VRAM 204 which is a memory used for image display. Then, the image data transferred to the VRAM 204 is divided into priority update data and non-priority update data.

  Although the priority update data and the non-priority update data will be described later, after classification by the initial setting, the classification of both can be changed in accordance with the corresponding scene of the game process. It is also possible to store data indicating the frequency of use of each image data, and set image data with high use frequency as priority update data and image data with low use frequency as non-priority update data. Thereafter, the display section is repeated, and this display section is executed by combining display processing and update processing.

  Since the display section starts at time 410, display processing is first executed. That is, after the frame period starts, the image data stored in the VRAM 204 is displayed on the VDP 240. At the time when the display process is completed at time 415, an image generation end interrupt signal is issued to start the update process. This update process is executed until the display section ends at time 420. That is, after the display process is performed by the VDP 240, the update process is performed by the VDP 240 until the frame period ends. The target of the update process is the image data transferred to the VRAM 204. The image data is updated by the VDP 240 so that the priority update data has a higher frequency than the non-priority update data.

  Since this display section is constant and the time required for the display process varies depending on the image to be displayed, the processing amount of the update process executed during the remaining time varies depending on the time. Similarly, the display section starts at time 420 and the display process is executed, the update process is executed from time 425, and the display section ends at time 430. This series of processing is repeated.

  As described above, the display process and the update process are repeated after completion of the initial setting. However, when the update process is executed, the priority update data is processed with priority. Although the update frequency of the priority update data is increased by processing with priority, the update processing with the update frequency changed will be described with reference to FIGS.

  FIG. 5 is a block diagram illustrating the configuration of each area of the VRAM. The VRAM 204 shown in FIG. 3 is used for the frame buffer 501, the work area 502, and the image data resident area 510, respectively. The frame buffer 501 is an area for actually displaying image data. A work area 502 is an area in which image data to be displayed next is prepared in advance.

  The image data resident area 510 is an area where image data read from the CGROM 203 is stored and resident for transfer to the frame buffer 501 or the work area 502. In this embodiment, the image data stored in the image data resident area 510 is divided into priority update data and non-priority update data, and is updated at different update frequencies. The image data resident area 510 is divided into a special symbol storage area 511 and a character storage area 512.

  The special symbol storage area 511 stores a special symbol image displayed during the game. Here, in order to form a display image, image data of a special symbol is transferred and developed in advance. The character storage area 512 stores a character image. Here, image data of various character images (images other than special symbols) used for forming a display image is transferred and developed.

  FIG. 6 is an explanatory diagram for explaining the processing order of the priority update data and the non-priority update data. Prior to the processing described in FIG. 6 and thereafter, first, image data such as symbols stored in the CGROM 203, which is a non-volatile memory, is transferred as an initial setting. The transfer destination is the VRAM 204 which is a memory used for image display. Then, the image data transferred to the VRAM 204 is divided into priority update data and non-priority update data. The image data resident area 510 shown in FIG. 5 can be divided into priority update data 610, non-priority update data 620, and non-priority update data 630.

  Although the display process and the update process are executed alternately, the update process will be described here. The priority update data 610 is updated preferentially and updated frequently. On the other hand, the update of the non-priority update data 620 and the non-priority update data 630 is not prioritized and is updated at a low frequency. Here, the order in which the priority update data 610, the non-priority update data 620, and the non-priority update data 630 are updated will be described.

  Specifically, the processing is as follows. First, the priority update data 610 is updated along the arrow 601. Next, the non-priority update data 620 is updated along the arrow 602. Next, the priority update data 610 is updated again along the arrow 603. Then, the non-priority update data 630 is updated along the arrow 604. Thus, the priority update data 610 is updated twice while the non-priority update data 620 and the non-priority update data 630 are updated once.

  In this way, the priority update data 610 is updated at twice the speed of the non-priority update data 620 and the non-priority update data 630. Depending on the frame, the priority update data 610 and the non-priority update data 620 or the non-priority update data are updated. Since the timing for updating both 630 occurs, this situation will be described.

  FIG. 7 is an explanatory diagram for explaining processing for updating the priority update data after the update of the first half of the non-priority update data is completed. As described with reference to FIG. 6, update processing is performed in the order of the arrow 601 and the arrow 602, but after processing the non-priority update data 620, more time remains, so the priority update data is further increased with the remaining time. A part of 610 is updated.

  That is, when the update processing is performed from the position 710 of the non-priority update data 620 along the arrow 701, the end position 720 of the non-priority update data 620 is reached, so the head returns to the top of the priority update data 610, and the arrow 702 is followed. The priority update data 610 is updated. Thereby, in this frame, in addition to the non-priority update data 620 indicated by the arrow 602 in FIG. 6, the priority update data 610 indicated by the arrow 603 is updated.

  FIG. 8 is an explanatory diagram for explaining the process of updating the second half of the non-priority update data after the update of the priority update data. After updating the non-priority update data 620 in FIG. 7 and shifting to the update of the priority update data 610, update processing is performed in the order of the arrow 603 and the arrow 604, as described in FIG. As in the case of FIG. 7, after the priority update data 610 is processed, a part of the non-priority update data 630 is further updated in the remaining time.

  That is, when the update process is performed along the arrow 801 from the position 810 of the priority update data 610, the end position 820 of the priority update data 610 is reached, so the process proceeds to the top of the non-priority update data 630 and along the arrow 802. The non-priority update data 630 is updated. Thereby, in this frame, in addition to the non-priority update data 610 indicated by the arrow 603 in FIG. 6, the priority update data 630 indicated by the arrow 604 is updated.

  FIG. 9 is an explanatory diagram for explaining a process for updating the priority update data after the latter half of the non-priority update data is updated. After updating the priority update data 610 in FIG. 8 and shifting to the update of the non-priority update data 630, the process returns to the arrow 601 from the arrow 604 described in FIG. Similarly to FIGS. 7 and 8, after processing the non-priority update data 630, a part of the priority update data 610 is further updated in the remaining time.

  That is, when the update process is performed along the arrow 901 from the position 910 of the non-priority update data 630, the end position of the non-priority update data 630 is reached, so the head returns to the top of the priority update data 610 and along the arrow 902. Update processing of the priority update data 610 is performed. As a result, in this frame, in addition to the non-priority update data 630 indicated by the arrow 604 in FIG. 6, the priority update data 610 indicated by the arrow 601 is returned and updated. Thereafter, the update process is repeated by repeating the same process.

  FIG. 10 is an explanatory diagram for explaining the processing order when the non-priority update data is divided into three or more. In FIG. 6, the non-priority update data is divided into the non-priority update data 620 and the non-priority update data 630. However, there are cases where it is desired to update the priority update data 610 earlier. In this case, by dividing the non-priority update data into three or more instead of two and returning to the update of the priority update data 610 each time one update is completed, the update can be performed three times faster than the other. Can proceed.

  Therefore, as an example when dividing into three, the image data resident area 510 shown in FIG. 5 is divided into priority update data 1010, non-priority update data 1020, non-priority update data 1030, and non-priority update data 1040. To do. Similar to FIG. 6, the priority update data 1010 is preferentially updated and updated frequently. On the other hand, the update of the non-priority update data 1020, the non-priority update data 1030, and the non-priority update data 1040 is not prioritized and is updated at a low frequency.

  Specifically, the processing is as follows. First, the priority update data 1010 is updated along the arrow 1001. Next, the non-priority update data 1020 is updated along the arrow 1002. Next, the priority update data 1010 is updated again along the arrow 1003. Then, the non-priority update data 1030 is updated along the arrow 1004. Next, the priority update data 1010 is updated again along the arrow 1005. Then, the non-priority update data 1040 is updated along the arrow 1006. In this manner, while the non-priority update data 1020, the non-priority update data 1030, and the non-priority update data 1040 are updated once, the priority update data 1010 is updated three times and updated at a speed three times that of the other. Will be.

  FIG. 11 is a flowchart for explaining a VRAM update control process. First, before starting this process, the power is turned on to perform an initial setting process. In this initial setting, first, image data such as symbols stored in the non-volatile memory CGROM 203 is transferred. The transfer destination is the VRAM 204 which is a memory used for image display. Then, the image data transferred to the VRAM 204 is divided into priority update data and non-priority update data. After completion of the initial setting process, as shown in FIG. 4, the display process and the update process are executed in units of frames.

  First, the timer is reset (step S1101). This timer is used for frame time measurement, and measures a frame period as a frame period until a fixed time is reached. This timer can also be reset upon receiving a vertical synchronization signal from the VDP 240.

  Next, display processing is executed (step S1102). That is, since the frame period is started by resetting the timer, the image data stored in the VRAM 204 is displayed on the VDP 240. Specifically, an image to be used, an image display position, a size, and an effect are specified, and the specified information is transmitted to the VDP 240 together with an image generation instruction. On the other hand, the VDP 240 receives this instruction and information, forms an image, and actually displays it. After the display, an image generation end interrupt signal is transmitted to the CPU 241.

  After the display process is completed as described above, the update process is executed by the VDP 240 by the end of the frame time. In this update process, the image data transferred to the VRAM 204 by the initial setting or the subsequent update process is updated with the image data stored in the CGROM 203. This update process will be described in steps S1103 to S1108.

  Next, the last update end point is confirmed (step S1103). Since the update point of the VRAM 204 is rewritten every time it is updated, the previous update end point written in advance is read out. Then, the transferable data amount is calculated from the remaining time (step S1104). Specifically, first, the remaining time of the display frame period is obtained by subtracting the measurement time of the internal timer from one display frame time. Then, this remaining time is compared with the total transfer time of each image scheduled to be updated next. Then, the data amount of the image that falls within the remaining time is calculated. For example, if the next image can be updated within the remaining time, the next image can be updated, the next image can be updated, but the next image cannot be updated, the three images that can be updated are transferred. It becomes possible data.

  Next, the transfer scheduled part determination process is performed (step S1105). That is, in the above-described case, the next three images can be updated, and therefore, these three image data are determined as the image data to be transferred that are to be updated. Here, the processing is divided into priority update data and non-priority update data, but the details will be described, and will be specifically described with reference to FIG. Here, a large amount of priority update data is updated by preferentially selecting priority update data as non-priority update data as a transfer scheduled portion.

  Next, a transfer instruction is given (step S1106). Then, the update end point is stored (step S1107). Since the VDP 240 updates the image in accordance with the transfer instruction described above, the update end point is advanced by the amount of the update. That is, the last image data instructed to transfer in step S1106 becomes a new update end point.

  Then, an update end signal is received (step S1108). Since the update end signal is issued when the update process is completed in the VDP 240, the update end signal is received. Then, a series of processing ends. Since one cycle of the display section ends at the end of the process, the above display process and update process are repeated while the power is on. When the power is turned off, the process is completely completed.

  FIG. 12 is a flowchart of the transfer scheduled part determination process when the process is divided into priority update data and non-priority update data. In step S1105 of the VRAM update control process shown in FIG. 11, when the process proceeds to the transfer scheduled part determination process, the next process is started. In this process, a transfer scheduled part to be updated in a form in which priority update data and non-priority update data are distinguished is determined.

  First, it is determined whether or not the last update end point was the priority data portion (step S1201). Here, if it is a priority data part (step S1201: Yes), confirmation of the transfer scheduled part is advanced, and it is determined whether or not the end of the priority data part has been reached (step S1202). If it does not reach the end (step S1202: No), it falls within the priority data portion, so a transfer scheduled portion is determined in the priority data portion (step S1203), and the series of processing ends. If it reaches the end (step S1202: Yes), it does not fit in the priority data part, so it is determined as the transfer scheduled part until the end of the priority data part and the remaining range from the beginning of the next segment of the non-priority data part (step S1204). A series of processing ends.

  On the other hand, when the last update end point is not the priority data part (step S1201: No), confirmation of the transfer scheduled part is advanced, and it is determined whether the segment end of the non-priority data part has been reached (step S1205). . When it does not reach the end (step S1205: No), it falls within the segment, so a transfer scheduled part is determined within the segment (step S1206), and a series of processing ends. If it reaches the end (step S1205: Yes), it does not fit within the segment, so the segment until the end of the segment and the remaining range from the head of the priority data portion are determined as the transfer scheduled portion (step S1207), and the series of processing ends.

  FIG. 13 is a flowchart of update processing when processing is divided into priority update data and non-priority update data. That is, the update process is started in accordance with the transfer instruction shown in step S1106 in FIG. 11, and the update end signal shown in step S1108 is returned at the end. Here, the next processing is started by this transfer instruction.

  First, it is determined whether the transfer scheduled part is a priority data part (step S1301). If it is a priority data part (step S1301: Yes), the data of the priority data part is transferred from the CGRAM 203 to the VRAM 204 (step S1302). Then, it is determined whether or not all data has been processed (step S1303). If all data has not been processed (step S1303: No), the process proceeds to step S1304. If all data has been processed (step S1303: Yes), the process proceeds to step S1306. move on.

  On the other hand, if it is not the priority data part (step S1301: No), the data of the non-priority data part is transferred from the CGRAM 203 to the VRAM 204 (step S1304). Then, it is determined whether or not all data has been processed (step S1305). If all data has not been processed (step S1305: No), the process proceeds to step S1302, and if all data has been processed (step S1305: Yes), the process proceeds to step S1306. move on. Then, a transfer end signal is received (step S1306), and a series of processing ends.

  As described above, the image to be prioritized among the image data can be updated before other images. Since the image to be prioritized is frequently updated, even if the image is damaged, it is quickly restored and the time for which it is left is reduced. Therefore, it is possible to reduce the influence of damage preferentially. For example, if the image to be prioritized is a frequently used image, it is updated early to prevent the image from being repeatedly displayed before it is restored in a damaged state, and given to the player Discomfort can be reduced.

  In addition, by making the image to be prioritized an important image such as a special symbol at the time of probability change, the morale of damaging the image in an important situation for a player who displays this important image. It is possible to prevent the player from making the player uncomfortable by displaying a screen for scraping.

(Process when priority is given to update processing)
In the above description, the case where image data is efficiently updated by dividing the image data into priority update data and non-priority update data has been described. Here, however, by allocating frame distribution to update processing with priority. The case where the update processing time is increased and the image data is updated at high speed will be described. In other words, only the update process is executed at a certain timing instead of the process of executing the update process after performing the display process in the frame.

  FIG. 14 is a timing chart showing operations of display processing and update processing when priority is given to update processing. First, at time 1400, the power is turned on. After the power is turned on, the initial setting process is executed, and the initial setting ends at time 1410. In this initial setting, first, image data such as symbols stored in the non-volatile memory CGROM 203 is transferred. The transfer destination is the VRAM 204 which is a memory used for image display.

  Thereafter, the display section is repeated, and this display section is executed by combining display processing and update processing. This display process and update process are executed by instructing display and update to the VDP 240. Upon receiving this instruction, the VDP 240 reads and executes the image data from the VRAM 204 or displays the image data stored in the VRAM 204 on the symbol display unit 104.

  The display section starts at time 1410, and at this time, it is determined whether or not it is a timing for preferential update. FIG. 14 illustrates an example in which update processing priority, display processing priority, and display processing priority are repeatedly executed. Since this is the first time, it is determined that the timing is to preferentially update. Therefore, since the update process has priority, only the update process is executed. This update process is executed until the display section ends at time 1420.

  Next, since the display section starts at time 1420, it is similarly determined whether or not it is a timing to preferentially update. Here, since the next timing prioritizes the update process, it is determined that the timing is not preferentially updated. Therefore, since the display process has priority, the display process is first executed. If an image generation end interrupt signal is issued at the time when the display process is completed at time 1425, the update process is executed after the display process even when it is not preferentially updated, so the update process is started. This update process is executed until the display section ends at time 1430.

  Similarly, the display section starts at time 1430 and the display process is executed, the update process is executed from time 1435, and the display section ends at time 1440. From time 1440, as with time 1410, the update process is prioritized and only the update process is executed. Thereafter, this series of processing is repeated in the same manner as at time 1420 and at time 1430.

  As to whether or not it is the timing for preferential updating, here, as the timing for preferential updating first, the timing for preferentially updating after that and the timing for preferentially updating once are alternated. However, the first timing may not be preferentially updated. Also, the timing for preferential update at the first time can be changed within a range of repetitions that are not preferentially updated several times thereafter. For example, the number of times of not updating may be one time or three times or more instead of two times.

  Further, it may be a timing to preferentially update after a plurality of times that are not preferentially updated including the first. In this way, it is possible to determine whether or not it is a timing to preferentially update based on the number of frames. For this purpose, the number of frames is counted every certain period, in the case of the above description, once every time, or at the timing when one frame is preferentially updated after a plurality of frames. it can. If the frequency of the preferential update timing is increased, the image data can be recovered early even when the image data is damaged. On the other hand, when updating is not performed preferentially, that is, when display is prioritized, it is possible to reduce a sense of discomfort on the screen display being updated.

  In addition, determination of timing that is not based on the number of frames is also conceivable. For example, when a game process to be operated by a player is being executed, for example, when a symbol is moving, the timing is not preferentially updated. Can do. In addition, it is possible to set the timing during which the probability fluctuation operation is not preferentially updated.

  In addition, the timer can count the time when the update of the image data transferred to the VRAM 204 is completed. Until the timer counts a predetermined time, any timing is not determined to be preferentially updated. Then, when the timer measures a predetermined time, the timing is determined along the above-described interval, and the update process according to the timing is executed. It is also possible to repeat the process of counting again by the timer when the update process has made a round and not determining the preferential update timing during the time measurement. In this case, since time to concentrate on the update occurs every fixed time, the normal update time is not given priority in the normal time zone counted by the timer, and all the updates can be executed periodically.

  FIG. 15 is a flowchart for explaining processing for performing VRAM update control by switching between update priority processing and display priority processing. This process is a process in which steps S1101 to S1103 shown in FIG. 11 are replaced. Similarly to FIG. 11, the power is turned on to perform initial setting processing, and after the initial setting processing is completed, display processing and update processing are executed in units of frames. In this initial setting, first, image data such as symbols stored in the non-volatile memory CGROM 203 is transferred. The transfer destination is the VRAM 204 which is a memory used for image display. Unlike the case of FIG. 11, it is not necessary to distinguish priority update data and non-priority update data.

  First, the timer is reset (step S1501). Next, it is determined whether or not update priority is given (step S1502). If it is not the update priority (step S1502: No), display processing is executed (step S1503), and the process proceeds to step S1505. In the case of updating priority (step S1502: Yes), it is determined whether or not a predetermined count value has been reached (step S1504).

  If not reached (step S1504: NO), display processing is executed (step S1503), and the process proceeds to step S1505. If it has been reached (step S1504: YES), a count process is executed (step S1505). Next, the last update end point is confirmed (step S1506), and the series of processing ends. Since this series of processes replaces step S1101 to step S1103 shown in FIG. 11, the process then proceeds to step S1104 in FIG. 11 to continue the process. By replacing the process as described above, the update priority process and the display priority process can be switched depending on the count value.

  As described above, since the display process and the update process are combined and the update process is preferentially executed at a certain timing, the time allocated to the update process increases as a whole. Therefore, since the update process can be rushed, the influence of image damage can be reduced at an early stage. On the other hand, the display process and the update process can be performed in parallel while giving priority to the update process. That is, as compared with the case where only the display process and the update process are combined, the image data can be updated more quickly. On the other hand, the display process is not stopped completely, but the display process and the update process are performed at regular intervals. Since the process combining the above is also executed, the uncomfortable feeling on the screen display can be minimized.

(Processing when priority is given to display processing)
In the above description, the process of preferentially assigning the distribution of frames to the update process has been described, but here, the time of the update process is reduced by preferentially assigning the distribution of frames to the display process, and the update process continues. A case will be described in which display processing is executed preferentially while being executed. That is, only the display process is executed at a certain timing instead of the process of executing the update process after the display process in the frame.

  FIG. 16 is a timing chart showing operations of display processing and update processing in the case of priority on display processing. First, at time 1600, the power is turned on. After the power is turned on, the initial setting process is executed, and the initial setting ends at time 1610. Thereafter, the display process is repeated, and this display section is executed by combining the display process and the update process. In this initial setting, first, image data such as symbols stored in the non-volatile memory CGROM 203 is transferred. The transfer destination is the VRAM 204 which is a memory used for image display.

  Thereafter, the display section is repeated, and this display section is executed by combining display processing and update processing. This display process and update process are executed by instructing display and update to the VDP 240. Upon receiving this instruction, the VDP 240 reads and executes the image data from the VRAM 204 or displays the image data stored in the VRAM 204 on the symbol display unit 104.

  The display section starts at time 1610. At this time, it is determined whether or not it is a timing for preferential update. FIG. 16 illustrates an example in which display processing priority, update processing priority, and update processing priority are repeatedly executed. Since this is the first time, it is determined that the timing is not preferentially updated. Accordingly, priority is given to display processing, so only display processing is executed. Then, when this display process is completed, an image generation end interrupt signal is issued, and the system waits until the display section ends at time 1620.

  Next, since the display section starts at time 1620, it is similarly determined whether or not it is a preferential update timing. Here, since it is next to the timing when the update process is not prioritized, it is determined that the timing is to preferentially update. Therefore, display processing is first executed. At the time when this display process is completed at time 1625, an image generation end interrupt signal is issued to start the update process. This update process is executed until the display section ends at time 1630.

  Similarly, the display section starts at time 1630 and the display process is executed, the update process is executed from time 1635, and the display section ends at time 1640. From time 1640, display processing is prioritized as in time 1610, and only display processing is executed. Thereafter, this series of processing is repeated in the same manner as at time 1620 and at time 1630.

  As to whether or not it is the timing for preferential updating, here, as the timing for not preferentially updating first, the timing for preferential updating including this one time and the timing for preferentially updating two times alternately Although the example which performs is demonstrated, it is good also as the timing which updates preferentially first. In addition, the timing can be changed within a range of repetition of preferential update timing after a plurality of preferential update timings including the first. For example, the number of times of not updating may be one time or three times or more instead of two times. In addition, the timing for updating with priority first may be set to the timing for not updating with priority a plurality of times thereafter.

  In this way, it is possible to determine whether or not it is a timing to preferentially update based on the number of frames. For this purpose, the number of frames is counted every certain period, in the case of the above description, once every time, or at the timing when one frame is preferentially updated after a plurality of frames. it can. If the frequency of the preferential update timing is increased, the image data can be recovered early even when the image data is damaged. On the other hand, when updating is not performed preferentially, that is, when display is prioritized, it is possible to reduce a sense of discomfort on the screen display being updated.

  In addition, determination of timing that is not based on the number of frames is also conceivable. For example, when a game process to be operated by a player is being executed, for example, when a symbol is moving, the timing is not preferentially updated. Can do. In addition, it is possible to set the timing during which the probability fluctuation operation is not preferentially updated.

  In addition, the timer can count the time when the update of the image data transferred to the VRAM 204 is completed. Until the timer counts a predetermined time, any timing is not determined to be preferentially updated. Then, when the timer measures a predetermined time, the timing is determined along the above-described interval, and the update process according to the timing is executed. It is also possible to repeat the process of counting again by the timer when the update process has made a round and not determining the preferential update timing during the time measurement. In this case, since time to concentrate on the update occurs every fixed time, the normal update time is not given priority in the normal time zone counted by the timer, and all the updates can be executed periodically.

  As described above, the display process and the update process can be executed in parallel at a certain cycle and the display process can be executed independently, so the update process is performed little by little while giving priority to the display process. Can proceed. At the timing when the update process is not executed, a frame is reserved exclusively for the display process. Therefore, the screen display is executed more reliably than when the display and the update are executed at each timing. Can proceed.

(Process to switch between display priority processing and update priority processing)
As described above, in addition to the case where the display process and the update process are combined, the case where the update process is mainly increased and the case where the display process is mainly increased has been described. However, if you want to concentrate on the display process depending on the situation, if you want to focus on the update process, you may want to be in the middle. Therefore, a case will be described in which these display priority processing and update priority processing are dynamically switched in order to achieve appropriate processing according to the situation. The display priority process and the update priority process are both processes that combine the display process and the update process. Among these processes, the display priority process gives priority to display, and the update priority process executes to give priority to update.

  The update priority process is the process described with reference to FIG. 14 and is a process form in which the update is preferentially executed as a whole by executing only the update process in a specific frame. In contrast to this update priority process, the process shown in FIG. 16 can be a display priority process. This processing is a processing form in which display is preferentially executed as a whole by executing only display processing in a specific frame.

  Further, when the update priority process is the process shown in FIG. 14, the processing mode for executing the display process and the update process for each frame shown in FIG. 4 may be the display priority process. By switching this processing to update priority processing, display processing can be relatively prioritized. On the other hand, when the display priority process is the process shown in FIG. 16, the processing mode for executing the display process and the update process for each frame shown in FIG. 4 may be the update priority process. By switching this process to the display priority process, the update process can be relatively prioritized.

  FIG. 17 is a timing chart when the display priority process and the update priority process are periodically switched. First, at time 1700, the power is turned on. After the power is turned on, the initial setting process is executed, and the initial setting ends at time 1710. After that, both are executed alternately by measuring with a timer. The display priority process is executed for most of the time, and the update priority process is executed when a certain time has elapsed. When the update is completed, the process returns to the display priority process and the same process is repeated.

  Specifically, display priority processing is started at time 1710. Then, with the start, the timer measures the time and waits for a certain period of time. The display priority process is repeated until a certain time has elapsed. Assuming that a certain time elapses at time 1720, the display priority processing ends here. Next, update priority processing is started at time 1720.

  Here, the period until the update of all the image data in the image data resident area 510 is set as the update priority process period, and the display priority process is switched when all the image data is updated. Note that the update priority process may be switched to the display priority process after the elapse of a certain time as in the display priority process. Similarly, display priority processing is started at time 1730, and update priority processing is started from time 1740 after a predetermined time has elapsed. Thereafter, the same processing is repeated.

  FIG. 18 is a timing chart in the case of switching to the update priority process at a specific timing on the premise of the display priority process. First, as in the case of FIG. 17, at time 1800, the power is turned on. After the power is turned on, the initial setting process is executed, and the initial setting ends at time 1810. After that, both are executed alternately by measuring with a timer. However, unlike the case of FIG. 17, here, the display priority process is executed for most of the time, the update priority process is executed at a specific timing, and the process returns to the display process when the update is completed.

  Specifically, the display priority process starts at time 1810. Since there are no players yet after the power is turned on, a demo screen is displayed. During this time, display priority processing is continued. Then, the update priority process is started at the time when the player appears and the game is started, that is, at time 1820. The start of the game may be, for example, the time when the sensor is detected by touching the knob of the game table, or the time when a ball is hit and reacts at some point.

  Here, the period until the update of all the image data in the image data resident area 510 is set as the update priority process period, and the display priority process is switched when all the image data is updated. Then, from time 1830, the process returns to the display priority process.

  As described above, it is also conceivable to combine the process of giving priority to the update process and the process of giving priority to the display process while performing the display process and the update process in parallel. In this case, it is possible to prioritize the update process or prioritize the display process as necessary while paralleling the update process and the display process. That is, it is possible to perform processing so as to increase the specific gravity as needed, without stopping display and updating in any time zone.

  Note that the gaming machine control method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

  As described above, the gaming machine and the control method thereof according to the present invention can further advance the update process at a necessary image or timing while reducing the player's uncomfortable feeling while performing the image display process and the update process in parallel. It is suitable for pachinko machines, slot machines, and other various game machines.

It is a front view which shows an example of the game board of the pachinko game machine as a game machine of this invention. It is a block diagram which shows the internal structure of the control part of a pachinko gaming machine. It is a block diagram showing a functional configuration of an effect control unit. It is a timing chart showing operation of display processing and update processing by VDP. It is a block diagram explaining the structure of each area | region of VRAM. It is explanatory drawing explaining the processing order of priority update data and non-priority update data. It is explanatory drawing explaining the process which updates priority update data after completion | finish of the update of the first half of non-priority update data. It is explanatory drawing explaining the process which updates the non-priority update data second half after completion | finish of the update of priority update data. It is explanatory drawing explaining the process which updates priority update data after the update end of non-priority update data latter half. It is explanatory drawing explaining the processing order when non-priority update data is divided into three or more. It is a flowchart explaining the control process of VRAM update. It is a flowchart of a transfer plan part determination process at the time of dividing a process with priority update data and non-priority update data. It is a flowchart of an update process when a process is divided into priority update data and non-priority update data. It is the timing chart which showed the operation | movement of the display process and update process in case of update process priority. It is a flowchart explaining the process which switches an update priority process and a display priority process, and performs VRAM update control. It is the timing chart which showed the operation | movement of the display process and update process in case of display process priority. It is a timing chart in the case of switching display priority processing and update priority processing periodically. It is a timing chart in the case of switching to update priority processing at a specific timing in a state premised on display priority processing.

Explanation of symbols

104 Symbol Display Unit 201 Main Control Unit 202 Production Control Unit 203 CGROM
204 VRAM
240 VDP
241 CPU
242 ROM
243 RAM
304 Drawing control unit

Claims (13)

Transfer means for controlling the display processing processor to transfer the image data stored in the non-volatile memory to a resident data area of a VRAM used for image display;
Determining means for determining whether or not it is time to preferentially update the image data in the resident data area transferred by the transfer means;
At the timing when the determination means determines that the update is not performed preferentially, the image data stored in the resident data area of the VRAM is transferred to the display processing processor after the start of the frame period which is a section on image display. Display control means for display processing;
The image data transferred to the resident data area of the VRAM by the transfer means at the timing determined to be preferentially updated by the determination means is the image data stored in the nonvolatile memory for the display processing. Update control means for updating the processor,
The determination means includes a timer that counts the time from when the update of the image data transferred to the resident data area of the VRAM goes around until the next update of the image data goes around,
The gaming machine is characterized in that it is determined that the timing is not updated preferentially until the timer times a predetermined time after the image data has been updated.   The said determination means counts the frequency | count of the said frame, and determines with the timing which preferentially updates the said image data transferred by the said transfer means for every fixed period. Gaming machine.   The gaming machine according to claim 2, wherein the determination unit alternately cycles a preferential update timing and a non-preferential update timing.   The gaming machine according to claim 2, wherein the determination unit cycles the timing of preferential update after a plurality of times of non-preferential update.   5. The determination unit according to claim 1, wherein when the image data of a symbol is moving among the displayed image data, the determination unit determines that the timing is not preferentially updated. Game machines.   The determination means counts the number of frames until the update of the image data completes a cycle from the start of the movement of the symbol image data of the displayed image data, and transfers the transfer at regular intervals. The game machine according to any one of claims 1 to 4, wherein the timing is determined to preferentially update the image data transferred by the means. Transfer means for controlling the display processing processor to transfer the image data stored in the non-volatile memory to a resident data area of a VRAM used for image display;
A measuring unit that counts the number of frames that are sections on the image display and sets the image data of the resident data area transferred by the transfer unit as a priority for each predetermined number of cycles, and
Display control means for causing the display processor to display the image data stored in the resident data area of the VRAM after the start of the frame period;
When the timing to preferentially update is measured by the measuring means, it is transferred to the resident data area of the VRAM by the transfer means after the display processing by the display control means and until the end of the frame period. Update control means for updating the display processing processor with the image data stored in the nonvolatile memory.
The measuring means includes a timer that measures the time from the update of the image data transferred to the resident data area of the VRAM used for the image display until the update of the next image data is completed,
The gaming machine is characterized in that it is determined that the timing is not updated preferentially until the timer times a predetermined time after the image data has been updated.   The gaming machine according to claim 7, wherein the measurement unit alternately cycles the timing for preferential updating and the timing for not preferentially updating.   The gaming machine according to claim 7, wherein the measuring unit cycles the timing of preferential updating after a plurality of times of non-preferential updating.   10. The measurement unit according to claim 7, wherein when the design image data is moving among the displayed image data, the measurement unit determines that the timing is not preferentially updated. Game machines.   The measuring means counts the number of frames until the update of the image data completes a cycle from the start of the movement of the design image data in the displayed image data, and transfers the transfer at regular intervals. The game machine according to claim 7, wherein the timing is determined to preferentially update the image data transferred by the means. A transfer step of controlling the display processor to transfer the image data stored in the non-volatile memory to a resident data area of a VRAM used for image display;
A determination step of determining whether or not it is time to preferentially update the image data transferred to the resident data area by the transfer step;
At the timing when it is determined not to be preferentially updated by the determination step, the image data stored in the resident data area of the VRAM is transferred to the display processing processor after the start of the frame period, which is a section on image display. A display control process for display processing;
The image data transferred to the resident data area of the VRAM by the transfer step is the image data stored in the non-volatile memory at the timing determined to be preferentially updated by the determination step. An update control step for causing the processor to update,
The determination step uses a timer to count the time from the completion of the update of the image data transferred to the resident data area of the VRAM to the completion of the update of the next image data.
A control method of a gaming machine, characterized in that it is determined that the timing is not preferentially updated until the timer times a predetermined time after the image data has been updated. A transfer step of controlling the display processor to transfer the image data stored in the non-volatile memory to a resident data area of a VRAM used for image display;
A measurement step that counts the number of frames that are sections on the image display and sets the image data in the resident data area transferred by the transfer unit as a priority for every predetermined number of cycles, and
A display control step of causing the display processing processor to display the image data stored in the resident data area of the VRAM after the start of the frame period;
When the timing to preferentially update is measured by the measurement process, it is transferred to the resident data area of the VRAM by the transfer process after the display process by the display control process until the end of the frame period. An update control step of causing the display processor to update the image data with the image data stored in the nonvolatile memory,
In the measuring step, the timer measures the time from the update of the image data transferred to the resident data area of the VRAM used for the image display until the update of the next image data is completed,
A control method of a gaming machine, characterized in that it is determined that the timing is not preferentially updated until the timer times a predetermined time after the image data has been updated.

Images