JPH04175798A - Refreshing system for frame memory - Google Patents

Abstract

PURPOSE:To avoid the concentration of the consumed current at the time of refreshing and miniaturize the power feed section of a system by refreshing frame memories in blocks of a proper number of memories in time division. CONSTITUTION:Memory blocks 7-1 through 7-n of a frame memory are units of dynamic RAMs refreshed concurrently and constitute the frame memory of a high-precision image output device. A refresh controller 2 outputs special refresh request signals ERR during the horizontal flyback line period and outputs the refresh request signals MRR of the dynamic RAMs corresponding to the memory blocks 7-1 through 7-n to the memory blacks 7-1 through 7-n of the frame memory in sequence during the image signal output period. The refresh timing is divided, and the capacity of the power feed section of a system can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an effective refresh method when a dynamic RAM is used as a frame memory in a high-definition image output device.

(Prior art) Conventional refresh methods for computers using dynamic RAM provide refresh timing separately from or during the bus cycle, and arbitrate between the refresh timing and bus access, and Running high refresh timings without interruption.

(Problem to be solved by the invention) It is easy to design a low-definition image output device using static RAM for the frame memory, but a high-definition image output device has a large number of images, so it is costly. In terms of implementation, it is advantageous to use dynamic RAM.

If such a system has multiple frame memories and a large number of dynamic RAMs are used, the memory is selected continuously during the video output period, and it is impossible to interrupt this process, so it is difficult to know when to refresh the memory. It concentrates on a short period of time during the horizontal retrace period, and the power consumption of the system momentarily decreases.

In addition, the priority level of "Refreshi" is the highest < L,! l:
In case of horizontal synchronization medium dazorbano/memo 1. Alternatively, it is necessary to hold the FIFO memory in front of the D/A converter to perform speed conversion, which has the drawback of increasing the burden on the hardware.

(Means for Solving the Problems) Refreshing of one frame memory according to the present invention", 't)
The formula divides the frame stream into multiple memory blocks, sequentially uses refresh timings equal to the number of memory blocks during the video output period, and performs special refresh timing during the horizontal retrace period. 1 request timing, and at the given refresh request timing for each memory block, refresh is performed at the timing of memory blocks that are not outputting video,
The video output (one memory memory drive) gives priority to video use, does not perform T refresh, maintains this timing, and renovates while observing the special refresh call request timing set during the water 1Tj-return period. It is characterized by performing the following.

(Function) In the above-mentioned reel reset 1 method, since the frame memories are refreshed in a time-sharing manner for each appropriate number of frames, it is possible to avoid concentration of current consumption during reload reset 1.
This can be done by reducing the size of the system's power supply.

(Example) Fig. 1 is a functional block diagram of a high-definition video output device according to this method, and Fig. 2 shows the timing for refreshing dynamic R and AM of the high-definition video output device. There is.

In FIG. 1, 1 is a display bus, 2 is a refresh 1 control section, 3 is a readout control section, 4 is a video synchronization section, and 5 is a D/A
A converting section, 6 a display section, and 7-1 to 7-n indicate the ivy of the divided frames 1i.

Each memory block 7-1-7-n of frame t is
The units of guinomics RΔ~1 that are refreshed at the same time constitute a room of the high-definition video output device.

The video synchronization unit 4 has a reference oscillator therein, and generates synchronization (i and pixel signals) for outputting the video signal to the display 6.

The readout control unit 3 receives and receives a signal indicating a video output period and a pixel signal from the video synchronization unit 4, and reads the signal from the memory block 7-1.
The video data is read from 7-n, and the read data is sent to the D/A converter 5.

The 0/A converter 5 converts the digital data of the video into analog data at the middle pixel level, and outputs the analog data to the display 6.

The refresh 1 control unit 2 outputs the special refresh request signal ERR shown in FIG. Each memory block 7-1 to 7-n of the room memory during the signal output period
f, JU order ratio output.

The refresh Tokyo for the memory block 7-1 is 1 in the meth1 refresh-1 request MRf in FIG.
At this time, if the memory block 7-1 has not been read out from the read control 3, it is refreshed at the timing of the request MRR1.
). The refresh request MRR2 is a refresh request to the memory block 7-2, and at this time, in FIG. Therefore, the memory block 7=-2 is refreshed at the timing of the memory 2 refresh request MRR2, the memory 2 refresh hold signal MRH2 is enabled, and the refresh is performed until the next special refresh request signal ERR ( MRF2>
.

Memory block 7-n is refreshed at the timing of memory 2 refresh request compensation QMRRn (MRFn) in the same way as memory 1 is refreshed 7-1.

<Effects of the Invention> As explained above, the present invention does not require a double buffer memory or FIFO memory for each horizontal synchronization unit, can be realized with a simple device, and can reduce the power consumption of the system by dividing the refresh timing. This has the effect of reducing the capacity of the supply section.

Furthermore, the read timing and refresh timing only need to satisfy the horizontal synchronization relationship, and it is not difficult to provide refresh requests from other buses.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a high-definition image output device embodying the present invention, and FIG. 2 is a timing chart showing refresh timing according to the present invention. 1... Display lotus, 2... Refresh control section, 3...
...Reading control section, 4...Video synchronization section, 5...D
/A conversion section, 6... display section, 7-1 to 7-n... memory block. Applicant Mitsubishi Precision Co., Ltd.

Claims (1)

[Claims] The frame memory is divided into a plurality of memory blocks, and refresh request timings corresponding to the number of the plurality of memory blocks are sequentially output during the video output period, and special refresh request timings are output during the horizontal retrace period. At the given refresh request timing for each memory block, memory blocks that are not outputting video are refreshed at this timing, and memory blocks that are outputting video are refreshed with priority given to video output. A frame memory refresh method characterized in that the refresh is performed by holding this timing and waiting for a special refresh request timing provided during a horizontal retrace period.