JPH0614718B2 - Video data transfer method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a large-screen display device configured by arranging a plurality of display units each having a memory and a control circuit, and particularly relates to an image in a memory in each display unit. The present invention relates to a method of transferring data.

[Prior Art] As a conventional large screen display device, there is one having a structure shown in FIG. In the figure, (1) is a display unit in which display elements are arranged in a matrix, (2) is a memory, (3) is a control unit for converting display data into ON / OFF signals of display unit pixels, (4)
Is an AD converter that performs AD conversion of the video signal, (5) and (6) are memory write / read control units, (7) is a CPU, and the display unit (1) is a display element such as a light bulb or a CRT. Are arranged in a matrix to form a display panel.

In the above configuration, the display data written in the memory (2) is converted into the pixel on / off signal in the control unit (3), and the on / off of each pixel is controlled.・ Since only two states of OFF can be displayed, when displaying halftone like a video signal is necessary,
By reading the video signal of each pixel from the memory (2) for the required number of times at the required time interval and controlling the on / off of the corresponding pixel, the cumulative time when each pixel is turned on is the amplitude of the video signal corresponding to the pixel. I am trying to display halftones in proportion to. Here, the video signal is AD converter (4)
At AD, the data is AD converted and sequentially written into the memory (2), but the writing and read control sections (5) and (6) are adjusted so as not to interfere with the timing of reading data for display.

Here, details of the write control unit (5) and the read control unit (6) will be described with reference to FIGS. 7 and 8. FIG. 7 is a configuration diagram of the write control unit (5). First, as an address signal given to the memory,
The horizontal sync signal and the vertical sync signal separated and output from the sync separation circuit are input to the horizontal and vertical address counters, and the output of each counter is input to the memory as horizontal and vertical addresses. Then, the memory writes the data at the address in synchronization with the timing signal output from the timing generator.

Further, FIG. 8 shows a read control unit, which reads data from the read address of the memory output from the address counter in synchronization with the timing signal output from the timing generation unit. Here, in the read control unit (6), the reading of the memory is performed a plurality of times for one writing.

In order for the write control unit (5) and the read control unit (6) to write to or read from the memory, it is necessary to arbitrate the timing at which they access the memory. Here, as a method of arbitration, a method of allocating the read period and the write period in a time division manner is used.

By the way, in such a display device, when the number of pixels of the display unit (1) is increased to increase the screen size or to improve the display quality, or when the amount of data held by each pixel is increased,
The number of times of memory reading within the required time increases, and there arises a problem that the access time of the memory (2) cannot be kept in time. In order to solve such a problem, it is effective to divide the memory (2) into a plurality of pieces and read them in parallel.

FIG. 5 shows an example in which the display unit (1) is divided into a plurality of display units (8) together with the memory (2), and FIG. 6 shows the internal structure of the display unit (8). Memory (2) in each unit (8)
And the memory (2) is read out periodically for display. Since the number of readings of the memory (2) is proportional to the number of pixels of the display unit (1), if the memory (2) is provided for each display unit (8), the reading timing of the memo (2) becomes easier.

On the other hand, the AD-converted video signal is transferred to each display unit (8) via a cable. This transfer rate depends on the sampling rate of the video signal, but is generally high. Therefore, it becomes difficult to write data without disturbing the read timing of the memory (2) in each display unit (8).

As a method of adjusting the reading and writing of the memory (2),
A method is known in which the memory (2) is provided for two fields, while the data is being written for one field, the other one field is read and the memory (2) is switched for each field. Has been.

However, in the method of dividing the memory (2) into each display unit (8) and providing the memory (2) for each two fields in this way, the number of parts mounted on the display unit (8) increases and the cost is increased. Unfavorable.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a transfer method capable of favorably transferring video data to divided memories in a display unit. And

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below by assigning the same reference numerals to the same portions as those of a conventional device. In FIG. 1, the display section
(1) is vertically divided into, for example, three, and is composed of three display blocks (9), and each display block (9) is composed of three display units (8) and a power supply device (14). To be done. here,
Each display unit (8) has a display unit as shown in FIG.
(1), memory (2), memory read control circuit (6),
And a pixel on / off control circuit (3), the video signal is AD converted, passes through the same number of buffer memories BM1 to BM3 (10) as the display block via the bus, and the corresponding display block It is designed to be transferred to (9).

Then, in each display unit (8), the memory (2) is periodically read in order to display the data written in the memory (2). On the other hand, if the AD-converted display data is directly written to each display unit (8), the reading of the memory is hindered.Therefore, the same number of buffer memories BM1 to BM3 (10) are provided as the display block (9). Transfer from the buffer memories BM1 to BM3 (10) to the corresponding display blocks (9) in parallel via the bus (11). By doing this, it is possible to slow down the speed of data transfer to each display unit (8),
Data can be written without disturbing the reading of the memory (2) in each display unit.

Each display unit by slowing the data transfer rate
It will be described with reference to FIG. 2 that data can be written in (8) without hindering reading from the memory. In Figure 2, (a)
Shows the case where the buffer memories BM1 to BM3 (10) are not provided, and (b) shows the case where the buffer memories BM1 to BM3 (10) are provided to reduce the data transfer speed. Each display unit (8) periodically reads the memory (2) to display the data. On the other hand, data is written to the memory (2) to further advance the display. Therefore, as shown by the R / W timing in FIG. 2, reading and writing of the memory (2) are switched in a time division manner. It is assumed that the memory (2) is read during the period indicated by R, and the memory (2) is written during the period indicated by W.
If there is no buffer memory (10) as shown in Fig. 5,
The display data depends on the sampling rate of the data,
While being transferred to the display unit (8) at _{t 1, t 2, T 3} ... timing as shown in FIG. (A), this speed is generally fast, the period indicated by W in Figure 2, That is, it becomes difficult to stably hold the data and write it to the memory (2) during the period allotted for writing the data in the display unit. Therefore, as shown in FIG. 1, three buffer memories BM1 to B
M3 (10) is provided, and data is transferred in parallel from each display block (9) from these, and as shown by t ₁ ′, t ₂ ′, t ₃ ′ in FIG. Can be slowed down. By doing so, the data to be transferred can be sufficiently held for the period allocated for writing in the display unit (8), and thus writing to the memory (2) can be easily performed.

Next, the timing of writing / reading data to / from the buffer memories BM1 to BM3 (10) will be described.
Correspondence of division of (1) and division of horizontal scanning period, writing of data to each buffer memory BM1 to BM3 (10) and timing of data transfer from buffer memory BM1 to BM3 (10) to each display block (9) Show the relationship. (a) is a division of the display corresponding to the division of the display unit (1) shown in FIG. 1, (b) is a division of the horizontal scanning period H of the video signal corresponding to the division of the display, and (c) is a division of the data. The timings of writing to the buffer memories BM1 to BM3 (10) and data transfer from the buffer memories to the corresponding display blocks are shown. In the third view (c), for example, a signal of a period of an H ₁ of the video signal to AD conversion period W _1, by writing into the buffer memory BM1 through a bus, the W ₁ is the period P1 The data written in the period is sequentially read, and the data is transferred from the buffer memory BM1 to the corresponding display block via the bus (11). Buffer memory BM2,
Write signal H _2, the period of H ₃ similarly each video signal in a period of W _2, W ₃ will BM3, transfers P _2, respectively corresponding display block period P ₃ to (9). The data thus AD-converted can be slowed down by passing through the buffer memories BM1 to BM3 (10), so that the data read and write of the memory (2) divided in each display unit (8) can be performed. Timing adjustment becomes easy.

The signals output from the buffer memories BM1 to BM3 (10) are transferred to the display blocks (9) via the bus (11). In each display block (9), the signal is received by the buffer (12), the waveform is shaped, and the signal is transferred to each display unit (8) via the bus. Here, (13) is a terminating device for preventing dripping of the signal waveform.

[Effect of the Invention] As described above, according to the present invention, the display unit is divided into each display block, a buffer memory is provided corresponding to each display block, and one horizontal scanning period is time-divided so that a data writing period is obtained. The data is written in the buffer memory based on the timing based on the video signal, and the data is read in parallel from the buffer memory to each display block during the period from the end of the data writing until the writing starts again. Since it is decided to transfer the data, the data transfer speed can be reduced, so that the data can be written in the memory without hindering the reading of the data, the reliability of the data transmission to each display block is improved, and each display unit is improved. Inside, it becomes easy to adjust the reading and writing of the memory. Furthermore, since each display block receives data via the buffer memory, if the data transfer from the buffer memory to each display block is sent by a differential signal, the power supply of each display block can be electrically separated, and noise from the power supply can be eliminated. Can be reduced. Further, by decreasing the data transfer rate, it is possible to obtain the effect that the signal line can be lengthened.

[Brief description of drawings]

FIG. 1 is a block diagram according to an embodiment of the present invention, FIGS. 2 and 3 are time charts for explaining the present invention, FIG. 4 and the following are conventional examples, and FIG. 4 is a block diagram of a conventional display device. 5, FIG. 5 is a block diagram of a display device in which a plurality of display units are arranged side by side, FIG. 6 is a block diagram of a display unit including a memory for one field and its control circuit, and a display section, and FIG. 7 is a memory write control. FIG. 8 is a block diagram of the memory read control unit. (1) …… Display section, (2) …… Memory, (3) …… On / off control section, (4) …… AD conversion section, (5) …… Memory write control section, (6) …… Memory read controller, (8) …… Display unit, (9) …… Display block, (10) …… Buffer memory. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a large-screen display device comprising a plurality of display units each having a memory and a control circuit arranged side by side, the display section is vertically divided into a plurality of display blocks, and horizontal scanning of a video signal is performed corresponding to the division. The period is divided into a plurality of data writing periods, and the AD-converted video data is sequentially written to the buffer memory provided for each display block via the first bus for each data writing period, and then to each buffer memory. After the data writing is completed, the written data is transferred from each buffer memory to the memory in the corresponding display block via the second bus during the data reading period until the data writing is started again. The control circuit reads the data written in the memory at required time intervals to control ON / OFF of the corresponding pixel. Image data transfer method.