JP4514597B2 - 電子部品実装用基板 - Google Patents
電子部品実装用基板 Download PDFInfo
- Publication number
- JP4514597B2 JP4514597B2 JP2004375058A JP2004375058A JP4514597B2 JP 4514597 B2 JP4514597 B2 JP 4514597B2 JP 2004375058 A JP2004375058 A JP 2004375058A JP 2004375058 A JP2004375058 A JP 2004375058A JP 4514597 B2 JP4514597 B2 JP 4514597B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- electronic component
- metallized layer
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Description
1a:凹部
1b:実装部
1c:溝部
2:メタライズ層
3:メタライズ層の一部
6:蓋体
7:電子部品
8:電気的接続手段
Claims (1)
- 絶縁層を積層して成るとともに、上面に電子部品が実装される実装部を有した基体と、該基体の下面から側面にかけて形成されたメタライズ層とを具備し、前記メタライズ層の一部が内部に収容された複数の溝部を前記基体の側面に前記基体の上下面間にわたって形成するとともに、前記複数の溝部の各々の開口幅を前記積層された絶縁層の下層に比し上層で大となし、前記複数の溝部の全てにおいて、上端部に絶縁層が露出されており、かつ、前記メタライズ層の上端が同じ高さに位置することを特徴とする電子部品実装用基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004375058A JP4514597B2 (ja) | 2004-12-24 | 2004-12-24 | 電子部品実装用基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004375058A JP4514597B2 (ja) | 2004-12-24 | 2004-12-24 | 電子部品実装用基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006185971A JP2006185971A (ja) | 2006-07-13 |
JP4514597B2 true JP4514597B2 (ja) | 2010-07-28 |
Family
ID=36738882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004375058A Expired - Fee Related JP4514597B2 (ja) | 2004-12-24 | 2004-12-24 | 電子部品実装用基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4514597B2 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6316644A (ja) * | 1986-07-08 | 1988-01-23 | Kyocera Corp | 半導体素子収納用パツケ−ジの製造法 |
JP2003243556A (ja) * | 2002-02-19 | 2003-08-29 | Murata Mfg Co Ltd | 積層型基板装置 |
-
2004
- 2004-12-24 JP JP2004375058A patent/JP4514597B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6316644A (ja) * | 1986-07-08 | 1988-01-23 | Kyocera Corp | 半導体素子収納用パツケ−ジの製造法 |
JP2003243556A (ja) * | 2002-02-19 | 2003-08-29 | Murata Mfg Co Ltd | 積層型基板装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2006185971A (ja) | 2006-07-13 |
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