JP4512158B2 - 可変遅延回路網 - Google Patents

可変遅延回路網 Download PDF

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Publication number
JP4512158B2
JP4512158B2 JP2008501964A JP2008501964A JP4512158B2 JP 4512158 B2 JP4512158 B2 JP 4512158B2 JP 2008501964 A JP2008501964 A JP 2008501964A JP 2008501964 A JP2008501964 A JP 2008501964A JP 4512158 B2 JP4512158 B2 JP 4512158B2
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JP
Japan
Prior art keywords
signal
network
delay
circuitry
registration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008501964A
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English (en)
Japanese (ja)
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JP2008533916A5 (enExample
JP2008533916A (ja
Inventor
アンディー エル． リー，
ゲイリー レイ，
チャンソン チャン，
ボーン ベッツ，
ライアン ファン，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
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Altera Corp
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Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of JP2008533916A publication Critical patent/JP2008533916A/ja
Publication of JP2008533916A5 publication Critical patent/JP2008533916A5/ja
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Publication of JP4512158B2 publication Critical patent/JP4512158B2/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
JP2008501964A 2005-03-18 2006-03-13 可変遅延回路網 Expired - Fee Related JP4512158B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/083,482 US7138844B2 (en) 2005-03-18 2005-03-18 Variable delay circuitry
PCT/US2006/009132 WO2006101840A1 (en) 2005-03-18 2006-03-13 Variable delay circuitry

Publications (3)

Publication Number Publication Date
JP2008533916A JP2008533916A (ja) 2008-08-21
JP2008533916A5 JP2008533916A5 (enExample) 2009-08-20
JP4512158B2 true JP4512158B2 (ja) 2010-07-28

Family

ID=36593739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008501964A Expired - Fee Related JP4512158B2 (ja) 2005-03-18 2006-03-13 可変遅延回路網

Country Status (3)

Country Link
US (1) US7138844B2 (enExample)
JP (1) JP4512158B2 (enExample)
WO (1) WO2006101840A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7752475B2 (en) * 2006-06-27 2010-07-06 International Business Machines Corporation Late data launch for a double data rate elastic interface
US7734944B2 (en) * 2006-06-27 2010-06-08 International Business Machines Corporation Mechanism for windaging of a double rate driver
US7739538B2 (en) * 2006-06-27 2010-06-15 International Business Machines Corporation Double data rate chaining for synchronous DDR interfaces
US7783911B2 (en) * 2006-06-27 2010-08-24 International Business Machines Corporation Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements
US7882322B2 (en) * 2006-06-27 2011-02-01 International Business Machines Corporation Early directory access of a double data rate elastic interface
US7782990B1 (en) * 2006-09-27 2010-08-24 Xilinx, Inc. Method of and circuit for oversampling a signal in an integrated circuit
JP2010079520A (ja) * 2008-09-25 2010-04-08 Ricoh Co Ltd メモリモジュールのコントローラ及びメモリモジュールのコントローラの制御方法
US7948792B1 (en) 2009-04-15 2011-05-24 Altera Corporation Memory and techniques for using same
KR20120096028A (ko) 2009-12-25 2012-08-29 후지쯔 가부시끼가이샤 신호 수신 회로, 메모리 컨트롤러, 프로세서, 컴퓨터 및 위상 제어 방법
US8232826B1 (en) * 2010-01-25 2012-07-31 Altera Corporation Techniques for multiplexing delayed signals
US9235460B2 (en) 2012-02-27 2016-01-12 Altera Corporation Methods and apparatus for automatic fault detection
US10950542B2 (en) 2019-03-20 2021-03-16 Analog Devices, Inc. High-performance variable gain amplifier employing laminate transmission line structures

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4805195A (en) * 1984-06-08 1989-02-14 Amdahl Corporation Selectable timing delay circuit
US4714924A (en) * 1985-12-30 1987-12-22 Eta Systems, Inc. Electronic clock tuning system
JPS63211919A (ja) * 1987-02-27 1988-09-05 Nec Corp クロツク発生回路
US5376849A (en) * 1992-12-04 1994-12-27 International Business Machines Corporation High resolution programmable pulse generator employing controllable delay
JP3378667B2 (ja) * 1994-08-10 2003-02-17 株式会社アドバンテスト 周期クロックの可変遅延回路
JP2771464B2 (ja) * 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路
JPH0974351A (ja) * 1995-09-05 1997-03-18 Nippon Telegr & Teleph Corp <Ntt> プログラマブル回路装置
JPH10256883A (ja) * 1997-03-06 1998-09-25 Nec Ic Microcomput Syst Ltd デジタル逓倍回路
US6327318B1 (en) * 1998-06-30 2001-12-04 Mosaid Technologies Incorporated Process, voltage, temperature independent switched delay compensation scheme
US6453402B1 (en) * 1999-07-13 2002-09-17 Micron Technology, Inc. Method for synchronizing strobe and data signals from a RAM
US20020079937A1 (en) * 2000-09-05 2002-06-27 Thucydides Xanthopoulos Digital delay locked loop with wide dynamic range and fine precision
US7805628B2 (en) * 2001-04-02 2010-09-28 Credence Systems Corporation High resolution clock signal generator
CN1393992A (zh) * 2001-07-02 2003-01-29 朗迅科技公司 包含反馈回路的延迟补偿电路
JP4871462B2 (ja) * 2001-09-19 2012-02-08 エルピーダメモリ株式会社 補間回路とｄｌｌ回路及び半導体集積回路
US7034596B2 (en) * 2003-02-11 2006-04-25 Lattice Semiconductor Corporation Adaptive input logic for phase adjustments
US7009433B2 (en) * 2003-05-28 2006-03-07 Lattice Semiconductor Corporation Digitally controlled delay cells
US20050046458A1 (en) 2003-08-28 2005-03-03 Schroeder Charles G. Digital delay elements constructed in a programmable logic device

Also Published As

Publication number Publication date
US7138844B2 (en) 2006-11-21
WO2006101840A1 (en) 2006-09-28
US20060208785A1 (en) 2006-09-21
JP2008533916A (ja) 2008-08-21

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