JP4379878B2 - エアーギャップを選択的に形成する方法及び当該方法により作製された装置 - Google Patents

エアーギャップを選択的に形成する方法及び当該方法により作製された装置 Download PDF

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JP4379878B2
JP4379878B2 JP2004287734A JP2004287734A JP4379878B2 JP 4379878 B2 JP4379878 B2 JP 4379878B2 JP 2004287734 A JP2004287734 A JP 2004287734A JP 2004287734 A JP2004287734 A JP 2004287734A JP 4379878 B2 JP4379878 B2 JP 4379878B2
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layer
etching
liner
air gap
laminate
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Expired - Fee Related
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JP2004287734A
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Japanese (ja)
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JP2005175435A5 (enExample
JP2005175435A (ja
Inventor
ジャン・ポール・ゲノー・ドゥ・ミュシー
ゲラルト・バイヤー
カレン・メックス
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Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
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Priority claimed from EP03447239A external-priority patent/EP1521301A1/en
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2004287734A 2003-09-30 2004-09-30 エアーギャップを選択的に形成する方法及び当該方法により作製された装置 Expired - Fee Related JP4379878B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50758403P 2003-09-30 2003-09-30
EP03447239A EP1521301A1 (en) 2003-09-30 2003-09-30 Method of formation of airgaps around interconnecting line

Publications (3)

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JP2005175435A JP2005175435A (ja) 2005-06-30
JP2005175435A5 JP2005175435A5 (enExample) 2005-11-04
JP4379878B2 true JP4379878B2 (ja) 2009-12-09

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JP2004287734A Expired - Fee Related JP4379878B2 (ja) 2003-09-30 2004-09-30 エアーギャップを選択的に形成する方法及び当該方法により作製された装置

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100712517B1 (ko) * 2005-07-14 2007-04-30 삼성전자주식회사 에어 갭 구조를 갖는 반도체 소자의 인터포저
JP4735314B2 (ja) * 2006-02-14 2011-07-27 ソニー株式会社 半導体装置およびその製造方法
FR2916303B1 (fr) * 2007-05-15 2009-07-31 Commissariat Energie Atomique Procede de fabrication de cavites d'air utilisant des nanotubes
JP2010258215A (ja) 2009-04-24 2010-11-11 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
KR102190654B1 (ko) * 2014-04-07 2020-12-15 삼성전자주식회사 반도체 장치 및 이의 제조 방법

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