JP4346626B2 - 半導体集積回路およびその検査方法 - Google Patents
半導体集積回路およびその検査方法 Download PDFInfo
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- JP4346626B2 JP4346626B2 JP2006137753A JP2006137753A JP4346626B2 JP 4346626 B2 JP4346626 B2 JP 4346626B2 JP 2006137753 A JP2006137753 A JP 2006137753A JP 2006137753 A JP2006137753 A JP 2006137753A JP 4346626 B2 JP4346626 B2 JP 4346626B2
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- input
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- control signal
- data signal
- signal processing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
14,15,16 入力端子としての信号入力端子
21 制御バス部としてのバスインターフェース
22 データ信号処理部
23 切換部
R1 第1経路
R2 第2経路
SB 制御信号
SE 制御信号
Claims (2)
- 入力された画像信号を、入力された制御信号に基づき処理するデータ信号処理部と、
このデータ信号処理部よりも動作クロックが遅く、外部からの入力信号を処理して制御信号を生成し、この制御信号を前記データ信号処理部へと出力可能な制御バス部と、
外部からの制御信号を前記データ信号処理部へ直接入力する第1経路と、
前記制御バス部により生成された制御信号を前記データ信号処理部へ入力する第2経路と、
前記第1経路と前記第2経路とを選択的に切り換え可能な切換部とを具備し、
前記第1経路は、前記データ信号処理部に電気的に接続され、前記切換部により前記第2経路が選択されている状態では、画像信号の少なくとも一部を入力可能であるとともに、前記切換部により前記第1経路が選択されている状態では、外部からの制御信号を入力可能な入力端子を備えている
ことを特徴とした半導体集積回路。 - 入力された画像信号を、入力された制御信号に基づき処理するデータ信号処理部と、このデータ信号処理部よりも動作クロックが遅く、外部からの入力信号を処理して制御信号を生成し、この制御信号を前記データ信号処理部へと出力可能な制御バス部と、前記データ信号処理部に電気的に接続され、画像信号の少なくとも一部を入力可能な入力端子とを具備した半導体集積回路の検査方法であって、
外部からの所定の制御信号を、前記制御バス部を経由せずに前記入力端子を介して前記データ信号処理部へと直接入力する
ことを特徴とした半導体集積回路の検査方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006137753A JP4346626B2 (ja) | 2006-05-17 | 2006-05-17 | 半導体集積回路およびその検査方法 |
US11/797,527 US7770082B2 (en) | 2006-05-17 | 2007-05-04 | Semiconductor integrated circuit and test method therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006137753A JP4346626B2 (ja) | 2006-05-17 | 2006-05-17 | 半導体集積回路およびその検査方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007309745A JP2007309745A (ja) | 2007-11-29 |
JP4346626B2 true JP4346626B2 (ja) | 2009-10-21 |
Family
ID=38713298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006137753A Active JP4346626B2 (ja) | 2006-05-17 | 2006-05-17 | 半導体集積回路およびその検査方法 |
Country Status (2)
Country | Link |
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US (1) | US7770082B2 (ja) |
JP (1) | JP4346626B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8855029B2 (en) * | 2007-03-21 | 2014-10-07 | Skyworks Solutions, Inc. | LMS adaptive filter for digital cancellation of second order inter-modulation due to transmitter leakage |
TW201220269A (en) * | 2010-11-11 | 2012-05-16 | Novatek Microelectronics Corp | Display controller driver and testing method therewith |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0587890A (ja) | 1991-09-30 | 1993-04-06 | Nec Corp | 半導体集積回路 |
JP3310174B2 (ja) | 1996-08-19 | 2002-07-29 | 東芝マイクロエレクトロニクス株式会社 | 半導体集積回路 |
JP2003139818A (ja) | 2001-10-30 | 2003-05-14 | Hitachi Ltd | 半導体集積回路及び半導体集積回路のテスト方法 |
US7280620B2 (en) * | 2002-10-18 | 2007-10-09 | Canon Kabushiki Kaisha | Electronic device including image forming apparatus |
KR20060031476A (ko) | 2004-10-08 | 2006-04-12 | 삼성전자주식회사 | 커넥터/디지털 직렬 버스 인터페이스 장치 및 이를구비하는 표시 장치의 제어 장치 및 집적 회로 칩 |
-
2006
- 2006-05-17 JP JP2006137753A patent/JP4346626B2/ja active Active
-
2007
- 2007-05-04 US US11/797,527 patent/US7770082B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7770082B2 (en) | 2010-08-03 |
JP2007309745A (ja) | 2007-11-29 |
US20070271488A1 (en) | 2007-11-22 |
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