JP4334066B2 - パターン発生器及び電気部品試験装置 - Google Patents

パターン発生器及び電気部品試験装置 Download PDF

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Publication number
JP4334066B2
JP4334066B2 JP18447099A JP18447099A JP4334066B2 JP 4334066 B2 JP4334066 B2 JP 4334066B2 JP 18447099 A JP18447099 A JP 18447099A JP 18447099 A JP18447099 A JP 18447099A JP 4334066 B2 JP4334066 B2 JP 4334066B2
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JP
Japan
Prior art keywords
address
interrupt
pattern
test pattern
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18447099A
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English (en)
Japanese (ja)
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JP2001014893A (ja
Inventor
勝 津藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
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Advantest Corp
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Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP18447099A priority Critical patent/JP4334066B2/ja
Priority to TW089112545A priority patent/TW457535B/zh
Priority to DE10031528A priority patent/DE10031528A1/de
Priority to US09/606,082 priority patent/US6499126B1/en
Publication of JP2001014893A publication Critical patent/JP2001014893A/ja
Application granted granted Critical
Publication of JP4334066B2 publication Critical patent/JP4334066B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919Storing and outputting test patterns
    • G01R31/31921Storing and outputting test patterns using compression techniques, e.g. patterns sequencer

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP18447099A 1999-06-29 1999-06-29 パターン発生器及び電気部品試験装置 Expired - Fee Related JP4334066B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP18447099A JP4334066B2 (ja) 1999-06-29 1999-06-29 パターン発生器及び電気部品試験装置
TW089112545A TW457535B (en) 1999-06-29 2000-06-26 Pattern generator and electric parts testing device
DE10031528A DE10031528A1 (de) 1999-06-29 2000-06-28 Mustergenerator und Prüfvorrichtung für elektrische Teile
US09/606,082 US6499126B1 (en) 1999-06-29 2000-06-29 Pattern generator and electric part testing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18447099A JP4334066B2 (ja) 1999-06-29 1999-06-29 パターン発生器及び電気部品試験装置

Publications (2)

Publication Number Publication Date
JP2001014893A JP2001014893A (ja) 2001-01-19
JP4334066B2 true JP4334066B2 (ja) 2009-09-16

Family

ID=16153733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18447099A Expired - Fee Related JP4334066B2 (ja) 1999-06-29 1999-06-29 パターン発生器及び電気部品試験装置

Country Status (4)

Country Link
US (1) US6499126B1 (de)
JP (1) JP4334066B2 (de)
DE (1) DE10031528A1 (de)
TW (1) TW457535B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10110050A1 (de) * 2001-03-02 2002-09-05 Bosch Gmbh Robert Verfahren zur Absicherung sicherheitskritischer Programmteile vor versehentlicher Ausführung und eine Speichereinrichtung zur Durchführung dieses Verfahrens
US6789160B2 (en) * 2001-04-03 2004-09-07 Sun Microsystems, Inc. Multi-threaded random access storage device qualification tool
JP2005524852A (ja) 2002-05-08 2005-08-18 エヌピーテスト, インコーポレイテッド 多目的メモリを有するテスタシステム
US7434124B2 (en) * 2006-03-28 2008-10-07 National Instruments Corporation Reduced pattern memory in digital test equipment
US7725782B2 (en) * 2007-01-04 2010-05-25 Gm Global Technology Operations, Inc. Linked random access memory (RAM) interleaved pattern persistence strategy
CN101359966A (zh) * 2007-08-03 2009-02-04 深圳富泰宏精密工业有限公司 Gsm模块测试系统及方法
WO2015081980A1 (en) * 2013-12-02 2015-06-11 Advantest Corporation Instruction provider and method for providing a sequence of instructions, test processor and method for providing a device under test

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032281A (en) * 1996-01-12 2000-02-29 Advantest Corp. Test pattern generator for memories having a block write function
US6067651A (en) * 1998-02-20 2000-05-23 Hewlett-Packard Company Test pattern generator having improved test sequence compaction
US6161206A (en) * 1998-04-30 2000-12-12 Credence Systems Corporation Pattern generator for a semiconductor integrated circuit tester
US6092225A (en) * 1999-01-29 2000-07-18 Credence Systems Corporation Algorithmic pattern generator for integrated circuit tester

Also Published As

Publication number Publication date
DE10031528A1 (de) 2001-02-08
JP2001014893A (ja) 2001-01-19
TW457535B (en) 2001-10-01
US6499126B1 (en) 2002-12-24

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