JP4314096B2 - 半導体集積回路検査装置および半導体集積回路検査方法 - Google Patents

半導体集積回路検査装置および半導体集積回路検査方法 Download PDF

Info

Publication number
JP4314096B2
JP4314096B2 JP2003374912A JP2003374912A JP4314096B2 JP 4314096 B2 JP4314096 B2 JP 4314096B2 JP 2003374912 A JP2003374912 A JP 2003374912A JP 2003374912 A JP2003374912 A JP 2003374912A JP 4314096 B2 JP4314096 B2 JP 4314096B2
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
output
input
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003374912A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005140555A5 (enExample
JP2005140555A (ja
Inventor
宏 渡辺
達治 池田
一也 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2003374912A priority Critical patent/JP4314096B2/ja
Priority to US10/979,245 priority patent/US7317324B2/en
Publication of JP2005140555A publication Critical patent/JP2005140555A/ja
Publication of JP2005140555A5 publication Critical patent/JP2005140555A5/ja
Application granted granted Critical
Publication of JP4314096B2 publication Critical patent/JP4314096B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Tests Of Electronic Circuits (AREA)
JP2003374912A 2003-11-04 2003-11-04 半導体集積回路検査装置および半導体集積回路検査方法 Expired - Fee Related JP4314096B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003374912A JP4314096B2 (ja) 2003-11-04 2003-11-04 半導体集積回路検査装置および半導体集積回路検査方法
US10/979,245 US7317324B2 (en) 2003-11-04 2004-11-03 Semiconductor integrated circuit testing device and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003374912A JP4314096B2 (ja) 2003-11-04 2003-11-04 半導体集積回路検査装置および半導体集積回路検査方法

Publications (3)

Publication Number Publication Date
JP2005140555A JP2005140555A (ja) 2005-06-02
JP2005140555A5 JP2005140555A5 (enExample) 2006-12-21
JP4314096B2 true JP4314096B2 (ja) 2009-08-12

Family

ID=34686471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003374912A Expired - Fee Related JP4314096B2 (ja) 2003-11-04 2003-11-04 半導体集積回路検査装置および半導体集積回路検査方法

Country Status (1)

Country Link
JP (1) JP4314096B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006105738A (ja) * 2004-10-04 2006-04-20 Canon Inc 半導体集積回路検査装置、半導体集積回路検査方法、及びプログラム
US7557592B2 (en) * 2006-06-06 2009-07-07 Formfactor, Inc. Method of expanding tester drive and measurement capability
US7977959B2 (en) 2007-09-27 2011-07-12 Formfactor, Inc. Method and apparatus for testing devices using serially controlled intelligent switches
JP4727641B2 (ja) * 2007-10-01 2011-07-20 日本エンジニアリング株式会社 テスター装置
JP7095491B2 (ja) * 2018-08-27 2022-07-05 株式会社デンソー パルス信号異常検出装置

Also Published As

Publication number Publication date
JP2005140555A (ja) 2005-06-02

Similar Documents

Publication Publication Date Title
US20050093561A1 (en) Semiconductor integrated circuit testing device and method
EP2064562A2 (en) Testable integrated circuit and ic test method
KR20020025841A (ko) 반도체 집적회로의 검사방법 및 그 검사장치
US6031386A (en) Apparatus and method for defect testing of integrated circuits
JP2000503124A (ja) 集積回路を検査する方法
JP4314096B2 (ja) 半導体集積回路検査装置および半導体集積回路検査方法
US20100182033A1 (en) Testable integrated circuit and test method
KR20040101660A (ko) 테스트용 신호 패스를 가지는 출력 버퍼 회로 및 이에대한 테스트 방법
JP2962283B2 (ja) 集積回路の故障検出方法及び故障検出装置
US6815969B2 (en) Semiconductor inspection device capable of performing various inspections on a semiconductor device
JP3398755B2 (ja) Ｉｃテスタの電流測定装置
JPS645461B2 (enExample)
KR20090115615A (ko) 고장 여부 판단장치를 포함한 메모리 테스트 시스템 및메모리 테스트 시스템에서 디바이스의 고장 여부 판단방법
JPH10170585A (ja) 回路基板検査方法
JP3372488B2 (ja) 半導体ｃｍｏｓ集積回路の試験装置
US6674299B2 (en) Semiconductor tester, semiconductor integrated circuit and semiconductor testing method
JP4061533B2 (ja) Ｉｃテスタ
KR100355716B1 (ko) 인서키트테스터에서의 저저항 측정방법
JPH11190761A (ja) 半導体試験装置
JP2001147254A (ja) 半導体集積回路のテスト装置とそのテスト方法
JP2006105738A (ja) 半導体集積回路検査装置、半導体集積回路検査方法、及びプログラム
JP4227815B2 (ja) 半導体集積回路装置およびその検査方法
JPH04190175A (ja) Ｉｃ試験装置
JP2001091920A (ja) 試験回路
WO2009022305A1 (en) An integrated circuit having an analog circuit portion and a method for testing such an integrated circuit

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20060418

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061106

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061106

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20070626

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080515

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080520

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080718

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090106

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090306

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090512

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090518

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120522

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120522

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130522

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140522

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees