WO2009022305A1

WO2009022305A1 - An integrated circuit having an analog circuit portion and a method for testing such an integrated circuit

Info

Publication number: WO2009022305A1
Application number: PCT/IB2008/053255
Authority: WO
Inventors: Leon Van De Logt; Alexander Guido Gronthoud
Original assignee: Nxp B.V.
Priority date: 2007-08-16
Filing date: 2008-08-13
Publication date: 2009-02-19

Abstract

An IC (100) comprises an analog circuit portion (115) comprising a plurality of transistors (M1, M2, Q1, Q2) anda plurality of nodes (TP1-TPn), each connected to a terminal of a transistor from the plurality of transistors. The IC (100) also comprises a digital portion (110) including a processor (120) and a test arrangement comprising a digital to analog signal conversion stage (130) having a plurality of channels, each channel being arranged to couple the processor (120) to one of the respective nodes (TP1-TPn) and an analog to digital signal conversion stage (140) having a plurality of channels, each channel being arranged to couple one of the respective nodes (TP1-TPn) to the processor (120). In a test mode of the IC (100), the processor (120) is arranged to determine a structural parameter of a transistor (M1, M2, Q1, Q2) from the plurality of transistors in a test mode of the integrated circuit (100) by selecting the transistor by providing a test signal to the channel of the digital to analog signal conversion stage (130) coupled to a first node to which the transistor is connected and byreceiving a response to the test signal from the channel of the analog to digital signal conversion stage (140) associated with a second node to which the transistor is connected. The processor (120) compares the response with a reference value of the structural parameter. Thisway, localized process variations in the analog portion of the IC (100) can be detected in an efficient manner.

Description

DESCRIPTION

AN INTEGRATED CIRCUIT HAVING AN ANALOG CIRCUIT PORTION AND A METHOD FOR TESTING SUCH AN INTEGRATED CIRCUIT.

The present invention relates to an integrated circuit (IC) comprising an analog circuit portion comprising a plurality of transistors and a plurality of nodes that are each connected to a terminal of a transistor from the plurality of transistors; and a digital portion including a processor. The present invention further relates to a method for testing such an IC.

Nowadays, complex digital ICs can be tested in a satisfactory manner; high test coverage can be achieved relatively quickly, which means that the additional cost of the test process can be limited. Moreover, many solutions exist to add so-called design for testability (DfT) hardware to digital ICs that require only a modest area overhead. Unfortunately, the testing of analog portions of ICs still cannot be tested in the same satisfactory manner. For instance, analog test busses are part of a state-of-the-art DfT approach that is commonly used within an analog design. The test bus is used to provide probing signals to and from the analog circuit. A drawback is that such busses are typically configured to directly output the probed signals to the primary pins. This requires multiplexing to output pins, which can lead to a performance penalty on such pins. Alternatively, dedicated test bus pins may be added at the expense of the primary pin count, which adds to the cost of the IC and is often an undesirable solution because of the limited number of pins available to the designer.

In modern mixed signal processing ICs, i.e. ICs that have a digital and an analog signal processing part, both the digital processor and the analog circuit are usually included in the total design. This creates the possibility to use the processing power of the processor for analysis of test data. US patent application US 2006/0090113 A1 discloses an IC having a digital condition checker for comparing a digitized version of a signal value on an analog node of the IC with a reference value. The analog portion of the IC is brought into a prepared state using analog test signals that are supplied via analog test busses. The DfT arrangement of US 2006/0090113 A1 is used to functionally test the analog portion of the IC.

Other applications of using embedded processors for system testing on functionally operational analog circuit portions to improve the quality of the tests and at the same time being less dependent on expensive test systems include the application of loopback structures on a chip. The advantage of using the processors in such setup is, that the analog path is much shorter compared to traditional loopback. Therefore signal integrity is fully maintained and the test is close to real performance of the chip in an application.

However, these state of the art arrangements still have several drawbacks. For instance, these arrangements focus on testing the analog circuitry in a functional mode. Potential faults that arise from structural variations, e.g. variations in process parameters, may not be detected in such tests.

The present invention seeks to provide an IC in which the analog circuitry can be structurally tested.

The present invention further seeks to provide a method for testing such an IC.

According to a first aspect of the present invention, there is provided an IC comprising an analog circuit portion comprising a plurality of transistors and a plurality of nodes, each connected to a terminal of a transistor from the plurality of transistors; a digital portion including a processor; and a test arrangement comprising a digital to analog (DA) conversion stage having a plurality of channels, each channel being arranged to couple the processor to one of the respective nodes; and an analog to digital (AD) conversion stage having a plurality of channels, each channel being arranged to couple one of the respective nodes to the processor; and wherein the processor is arranged to determine a structural parameter of a transistor from the plurality of transistors in a test mode of the integrated circuit by selecting the transistor by providing a test signal to the channel of the digital to analog signal conversion stage coupled to a first node to which the transistor is connected; receiving a response to the test signal from the channel of the analog to digital signal conversion stage coupled to a second node to which the transistor is connected; and comparing the response with a reference value of the structural parameter.

The inclusion of such a test arrangement facilitates the testing of structural parameters of the transistors of the analog portion of the IC. The processor of the digital portion is used to measure individual parameters of individual transistors, thus effectively executing an in-circuit structural test. In particular, if the analog portion is kept in a powered down mode, the injection of a test signal generated by the digital processor and converted into an analog signal by the DA conversion stage into a node at one end of the transistor channel leads to a directly observable response signal on a node of the other end of the transistor channel. A biasing current generator may be included in the analog portion of the IC in case a current has to be sourced through the transistor for the determination of a current-related structural parameter.

In a preferred embodiment, the IC further comprises a memory device for storing a list of the transistors to be tested, respective digital signal values to be provided to the respective transistors in said list and the respective reference values for the transistors in said list; and wherein the processor is arranged to select respective transistors with their respective digital signal values their respective reference values from said list. This has the advantage that the complete test script is embedded in the IC, which makes it possible to perform the test of the transistors of the analog portion in an efficient manner.

The IC may further comprise a further memory device, with the processor being arranged to store the comparison results for the selected transistors in the further memory device. This make it possible to retrieve the test results in batch from the further memory device upon completion of the test rather than having to rely on the more complicated way of making each individual test result separately available on the outside of the IC during the test.

The IC may comprise a test access port (TAP) including an instruction register and instruction decoding logic coupled to the instruction register, the processor being arranged to enter the test mode in response to a dedicated instruction received by the instruction register such that the IC can be efficiently brought into the analog circuit test mode by the use of a dedicated instruction. Preferably, the TAP is a boundary scan (IEEE 1149.1 ) compliant TAP. The test data output pin of the TAP may be used by making the test results available on the outside of the IC, for instance by shifting out the test results stored in the further memory device.

According to a further aspect of the invention, there is provided a method of testing an integrated circuit comprising an analog portion comprising a plurality of transistors that are interconnected via respective nodes and a digital portion including a processor, the method comprising providing the integrated circuit with a test arrangement comprising: a digital to analog signal conversion stage having a plurality of channels, each channel being arranged to couple the processor to one of the respective nodes; and an analog to digital signal conversion stage having a plurality of channels, each channel being arranged to couple one of the respective nodes to the processor; the method further comprising determining a structural parameter of a transistor from the plurality of transistors by selecting the transistor by providing a test signal from the processor to the channel of the digital to analog signal conversion stage coupled to a first node to which the transistor is connected; receiving, at the processor, a response to the test signal from the channel of the analog to digital signal conversion stage coupled to a second node to which the transistor is connected; and operating the processor to compare the response with a reference value of the structural parameter. The method of the present invention facilitates the on-chip determination of structural parameters of the transistors of an analog portion of an IC. The reference values of the transistors under test may be determined using a golden device, i.e. a version of the IC that is known to be fault-free. The selected transistor may be diagnosed to comprise a certain structural defect if a difference between the response and the reference value is larger than a predefined threshold. Advantageously, the method may further comprise the steps of compiling a list of observable defects in respective transistors from the plurality of transistors by providing a fault-free version of the integrated circuit; emulating a defect in a transistor of said fault-free integrated circuit by providing the nodes from the plurality of nodes that are located at the interconnections of the selected transistor with respective predetermined voltage values; observing a node from the plurality of nodes, said node being located between a transistor terminal and a primary pin of the fault-free version of the integrated circuit; and adding the defect to the list if the emulated defect has caused a measurable response to the emulated defect on the observed node.

This has the substantial advantage that the list of test data from which the processor selects the transistors, the predefined signals and reference response signals for testing the IC of the present invention can be compiled using hardware, i.e. the golden device, rather than having to simulate the observability of these faults using analog circuit simulators. Since this simulation process is quite cumbersome and time-consuming, the emulation of the faults on a golden device can save a substantial amount of time and effort.

At this point, it is emphasized that although this method of compiling a set of test data for structurally testing the transistors of an analog circuit portion is disclosed in conjunction with the test arrangement of the IC of the present invention, this method may be used independently thereof, and may be considered as a feasible alternative to analog simulators.

The invention is described in more detail and by way of non-limiting examples with reference to the accompanying drawings, wherein:

Fig. 1 depicts an embodiment of an IC of the present invention; Fig. 2 depicts the IC of Fig. 1 in a first test mode; Fig. 3 depicts a golden device in a defect emulation mode; and Fig. 4 depicts a flowchart of an advantageous aspect of the method of the present invention.

It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.

Fig. 1 depicts an embodiment of an IC 100 of the present invention. The IC 100 has a digital portion 110 including an embedded processor 120, and an analog portion 115 including several transistors interconnected via nodes. In Fig. 1 , the analog portion 115 comprises a differential to single ended buffer having CMOS transistors M1 , M2, bipolar transistors Q1 , Q2 and nodes TP1 - TPn, with each of the nodes being connected to a terminal of one of the transistors. In the context of the present invention, a terminal of a transistor is either a connection to control the transistor or a connection to the channel of the transistor, such as the source and drain terminals of a CMOS transistor. The analog portion further comprises primary pins Vdd, Vss, inN and Out and some resistors and capacitors. The analog portion further comprises a current source l-bias, which is used in the normal operating mode of the analog portion 115, but can also be controlled in the test mode of the IC 100 to force currents through selected transistors. It will be appreciated that this implementation of analog portion 115 is chosen by way of non-limiting example only, and that the present invention can be used with any analog circuit portion.

The embedded processor 120 can be configured to derive structural parameters from the transistors of the analog circuit portion 115 in a test mode of the IC 100. In this mode, the processor 120 is used to drive test signals to selected nodes, capture response signals from selected nodes and to evaluate the captured signals by comparing them with available reference values for these signals. In order to facilitate communications between the digital processor 120 and the analog portion 115, the IC 100 further comprises a multi-channel DA conversion stage 130 and a multi-channel AD conversion stage 140. The number of channel in stage 130 may be different to the number of channels in stage 140. Each channel links the processor 120 to a specific node in the analog portion 115. Since the signals to be captured are typically low frequency signals, the sample rate of the DA and AD conversion stages can be kept low. The resolution of stages 130 and 140 can also be kept relatively low, e.g. 8bit, depending on what signals are to be measured. Consequently, the DA and AD conversion stages can be kept small, which makes them cheap to implement. Preferably, the DA conversion stage 130 and the AD conversion stage 140 are implemented as test-only conversion stages. This has the advantage that the wiring for the multi-channel AD/DA conversion stages can be dedicated to testing DC signals without having a negative loading effect on functionally used AD/DA converters.

The IC 100 further comprises an arrangement for bringing the IC in the test mode. This may be done in any known way, for example through the use of existing serial busses. However, in Fig. 1 , a TAP controller 170 including an instruction register 172 is used for this purpose by way of non-limiting example. The test mode is selected by shifted a dedicated instruction into the instruction register 172. The TAP controller 170 preferably is a JTAG controller, i.e. a TAP controller that is compliant with the IEEE 1149.1 boundary scan test standard.

The processor 120 typically has to be loaded with program code for executing the structural test of the transistors of the analog portion 115. This program code may be made available to the processor 120 from an external source, such as another processor or an external memory, for instance by shifting in the program code via the TAP 170. Alternatively, the IC 100 may comprise a memory device 150, such as a read-only memory (ROM), a look- up table (LUT) or another suitable memory device that stores the aforementioned program code in a first section 152. In addition, the processor 120 must have access to test configuration data, such as a list of transistors to be tested. Such a list typically includes, for each transistor, a reference value of the structural parameter to be determined and the values for the signals to be provided to the associated nodes of the transistor to be tested. Each transistor may be tested for more than one structural parameter. The test configuration data may be provided by an external source, although preferably the test configuration data is also stored in a second section 154 of the memory device 150, because the processor 120 can access the data more quickly if it is available in this memory device. The test mode of the IC 100 of Fig. 1 is typically initiated by loading the dedicated instruction into the instructor register 172 of the TAP controller 170, and decoding this instruction. This puts the processor 120 in the analog test mode (ATEST-STRUCTURAL). When ATEST-STRUCTURAL is invoked during production testing of the IC 100, the processor 120 will test individual transistors of the analog portion 115. Preferably, the analog portion 115 is left un-powered during this test mode. An un-powered analog portion 115 makes it easier to individually measure transistors in the portion. In case a current- related structural parameter is to be determined, a biasing circuit l-bias can be used in the test mode to source current through a transistor. The processor 120 accesses the memory device 150 to retrieve the necessary information for testing a transistor of the analog circuit portion 115. The transistor under test (TUT) is made in a specific technology, such as CMOS, and has specific, technology-dependent characteristics. These characteristics are also referred to as structural parameters in this application. These characteristics may be determined by process measurements or simulation, as will be explained in more detail later, and the determined characteristics are stored in the memory device 150 as reference. This can be either a complete I-V (current-voltage) characteristic or, more practically, transistor parameters such as beta, threshold voltage and so on. The stored references may include upper and lower limits for these values to cover process variations, in which case the reference comprises two reference values. The word size of the reference values is typically chosen based on the required accuracy of the determination of the structural parameter.

In fact, by measuring these characteristics every transistor of the analog portion 115 acts as an embedded process control monitor (PCM). It will be appreciated that state of the art PCMs only provide global process information, whereas the use of the transistors of the analog portion 115 as PCMs makes it possible to observe extremely localized process shifts, mismatch, systematic defects and other relevant structural parameters of the analog portion 115.

In Fig. 1 , the transistors to be tested are also listed in the second section 154 of the memory device 150. Practically, the transistors may be listed implicitly by storing the nodes to be probed for testing the transistor. It is pointed out that the transistor selection data does not require much memory; assume 1000 nodes to be probed, then each probe identifier is 10 bits in size which makes the required memory space 10 kBit only. The processor 120 will sequentially select transistors for testing from this list and will compare the measured test responses against the appropriate references. To this end, the processor 120 may have a dedicated comparison stage 122, if so required. One by one, the analog signals needed to measure the transistor characteristics of the selected transistor are driven through the DA conversion stage 130 to the TUT. While the DA conversion stage 130 is driving voltages to this transistor, the AD conversion stage 140 is used to retrieve the transistor specific values for evaluation by the processor 120 against the reference stored in memory device 150. The transistor instance will be flagged when it is failing against the reference. The comparison results may be made directly available off-chip, or may be stored in a further memory device (not shown) such as a result register, which may be part of TAP controller 170, or a random access memory (RAM). The data stored in the register or RAM can be serially shifted out to an external tester, for instance through the TDO pin of the TAP controller 170 or through any other suitable pin, to indicate the pass/fail status of the individually tested transistors of the analog portion 115. Hence, when a failure occurs, these flags indicate which transistor is failing. This facilitates a high level of test coverage detail, which greatly improves the diagnosis compared to state of the art techniques.

Fig. 2 gives an example of the ATEST-STRUCTURAL test mode that illustrates the detailed operation of the present invention. Some of the details of Fig. 1 have been left out for reasons of clarity only. In Fig. 2, the circle 200 indicates that the bipolar transistor Q1 has been selected for a parametric test. The processor 120 provides the DA conversion stage 130 with appropriate digital words, which are converted by the DA conversion stage 130 to analog values that are used to drive the nodes TP2 and TP3. Since direct current (DC) parameters are measured, the DA conversion stage 130 does not need to be a fast sampling DA conversion stage. For example a 1 OkSpS, 8-10 bit DA conversion stage 130 will suffice in most cases. While the DA conversion stage 130 is driving the nodes TP2 and TP3, the AD conversion stage 140 will start to sample the response of the transistor Q1 to the test signals on nodes TP1 and TP3.

The processor 120 will calculate the specific parametric values from the responses sampled on nodes TP1 and TP3. The resulting parameter value is compared against the reference parameter value that has been retrieved from the memory device 150. A flag bit is set when transistor Q1 does not meet its specification. This procedure will continue until all transistors in the list are tested, after which the flag bits are made available externally, e.g. by shifting them out via the TDO pin or any other IO pin, for further external processing.

A particularly advantageous aspect of the invention concerns the compilation of a list of observable parametric defects of the analog portion 115. To this end, a golden device 300 is provided in a first step 410 of method 400 shown in Fig. 4 to determine whether or not a parametric fault can be detected in a TUT of the IC 100. Fig.3 shows this golden device. The golden device 300 is a known good version of the IC 100. The TAP controller 170 of the golden device 300 is configured to trigger the processor 120 to enter the ATEST_DEFECT test mode in step 420 of the method 400. This is a different instruction to the ATEST_STRUCTURAL instruction, and involves the loading of a different test program onto the processor 120. This program may be stored in memory device 150. The memory device 150 typically comprises a list of defects for which it must be determined if the defects are observable on the nodes of an IC 100. This list typically includes information about the nodes involved, such as the values of the signals that need to be driven to these nodes to emulate the defect. These values may be taken from an initial simulation run.

In a next step 430 of method 400, the processor 120 selects a defect from the list, and generates the digital words that are translated by the DA conversion stage 130 into analog signals with which the nodes of the selected known good transistor of the analog portion 115 are driven in order to emulate the selected defect in the selected individual transistor. The analog portion 115 will be in its DC operating point, i.e. at nominal Vdd.

The golden device 300 comprises test points, i.e. nodes, which are connected to the primary pins of the golden device 300. These nodes are connected to the AD conversion stage 140, with the processor 120 being arranged to monitor whether a change in the voltage on the nodes associated with these primary pins can be detected upon emulation of a defect in a selected transistor in a next step 440 of the method 400. If the emulated defect causes a response difference on one or more of the primary pins, the defect will be flagged as observable in step 450 of the method 400, and it is assumed that this particular test condition is capable of detecting the targeted defect if it would occur in a production chip. The behavior of the primary pins may be monitored by the processor 120 via AD conversion stage 140. To this end, the processor 120 will compare the observed behavior of the sampled primary pins against a reference parameter value, which may be retrieved from the memory device 150. A flag bit is set when the observed behavior provides a measurable difference from one or more of the reference values.

Alternatively, the response to the emulated defect on the primary pins may be monitored off-chip by directly measuring the behavior of the primary pins with external measuring equipment. In step 460 of the method 400, it is checked if all defects to be emulated have been emulated. If not, the method 400 reverts back to step 430, otherwise the method 400 terminates in step 470.

For instance, the bipolar transistor Q1 may be selected, as indicated by circle 310 and the nodes TP1 and TP3 may be driven with equal voltages to emulate a short 315 in the transistor Q1 , since the characteristic behavior of a short in this transistor would be the lack of a voltage drop over its channel, thus resulting in equal voltages on the nodes on either side of this transistor. In this particular example, nodes to Vdd and Vss, as indicated by circles 320 and 330 respectively, are selected for observation. It will be appreciated that different types of defects can be inserted. For instance, for transistor Q1 , a resistive short can be emulated as a small voltage difference between drain- source determined by the resistive value of the short. Alternatively, a stuck-at fault can be emulated as a short to Vdd or Vss. Other examples will be apparent to the person skilled in the art.

The flags for all defects may be stored in a memory device such as a result register or a RAM. This memory device may be located on the golden device 300 in case processor 120 is used to monitor the selected primary pins, or may be located external to the golden device 300 if the primary pins are monitored externally. In case of an on-chip memory device, the observability data may be serially shifted out to the tester, for instance through TDO or another suitable IO pin. The current or voltage values observed on the primary pins may also be stored in this (or another) memory device, because these values are measurable in a production test (i.e. the test of an IC 100), and can therefore serve as reference values in this production test.

The method 400 can be part of evaluating a test plan during production ramp up to investigate if the test plan is capable of covering the process specific defects. In addition, the method 400 may be used for failure analysis and diagnosis, in which case the flags indicate which defects can be found. It is reiterated that although the method 400 described in Figs. 3 and 4 has been explained in conjunction with the test arrangements shown in Figs 1 and 2, it should be appreciated that the use of the method 400 may be used to develop a list of observable parametric faults to be used in any method for determining parametric faults in an analog portion of an IC. The use of the method 400 obviates the need to use cumbersome and time-consuming simulations to compile such a list. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. An integrated circuit (100) comprising: an analog circuit portion (115) comprising a plurality of transistors (M1 , M2, Q1 , Q2) and a plurality of nodes (TPI-TPn), each connected to a terminal of a transistor from the plurality of transistors; and a digital portion (110) including a processor (120); and a test arrangement comprising: a digital to analog signal conversion stage (130) having a plurality of channels, each channel being arranged to couple the processor (120) to one of the respective nodes (TPI -TPn); and an analog to digital signal conversion stage (140) having a plurality of channels, each channel being arranged to couple one of the respective nodes (TPI -TPn) to the processor (120); and wherein the processor (120) is arranged to determine a structural parameter of a transistor (M1 , M2, Q1 , Q2) from the plurality of transistors in a test mode of the integrated circuit (100) by: selecting the transistor by providing a test signal to the channel of the digital to analog signal conversion stage (130) coupled to a first node to which the transistor is connected; receiving a response to the test signal from the channel of the analog to digital signal conversion stage (140) coupled to a second node to which the transistor is connected; and comparing the response with a reference value of the structural parameter.

2. The integrated circuit (100) of claim 1 , wherein the analog portion (115) comprises a biasing current generator (l-bias) for sourcing a current through the transistor in the test mode.

3. The integrated circuit (100) of claim 1 or 2, further comprising a memory device (150) for: storing a list of the transistors to be tested; respective digital signal values to be provided to the nodes associated with respective transistors in said list; and the respective reference values for the transistors in said list; and wherein the processor (120) is arranged to select the transistors, the respective digital signal values and the respective reference values from said list.

4. The integrated circuit (100) of claim 1 , 2 or 3, wherein further comprising a further memory device, and wherein the processor (120) is arranged to store the comparison results for the selected transistors in the further memory device.

5. The integrated circuit (100) of any of the preceding claims, further comprising a test access port controller (170) including an instruction register

(172), the processor (120) being arranged to enter the test mode in response to a dedicated instruction received by the instruction register (172).

6. The integrated circuit (100) of claim 5, wherein the test access port (170) is further arranged to make the comparison results available on a test data output pin (TDO).

7. A method of testing an integrated circuit (100) comprising an analog portion (115) comprising a plurality of transistors (M1 , M2, Q1 , Q2) and a plurality of nodes (TPI -TPn), each connected to a terminal of a transistor from the plurality of transistors; and a digital portion (110) including a processor (120), the method comprising: providing the integrated circuit with a test arrangement comprising: a digital to analog signal conversion stage (130) having a plurality of channels, each channel being arranged to couple the processor (120) to one of the respective nodes (TPI -TPn); and an analog to digital signal conversion stage (140) having a plurality of channels, each channel being arranged to couple one of the respective nodes (TPI -TPn) to the processor (120); the method further comprising: bringing the integrated circuit (100) in a test mode; determining a structural parameter of a transistor (M1 , M2, Q1 , Q2) from the plurality of transistors by: selecting the transistor (M1 , M2, Q1 , Q2) by providing a test signal from the processor (120) to the channel of the digital to analog signal conversion stage (130) coupled to a first node to which the transistor is connected; receiving, at the processor (120), a response to the test signal from the channel of the analog to digital signal conversion stage (140) coupled to a second node to which the transistor is connected; and operating the processor (120) to compare the response with a reference value of the structural parameter.

8. The method of claim 7, further comprising diagnosing the selected transistor as comprising a structural defect if a difference between the response and the reference value is larger than a predefined threshold.

9. The method of claim 7 or 8, further comprising providing a bias current for sourcing a current through the transistor (M1 , M2, Q1 , Q2) in the test mode.

10. The method of claim 7, 8 or 9, further comprising determining the reference value in a fault-free version (300) of the integrated circuit.

11. The method of claim 7 or 8, further comprising: compiling (400) a list of observable defects in respective transistors from the plurality of transistors by: providing (410) a fault-free version (300) of the integrated circuit; bringing (420) the fault-free version (300) of the integrated circuit in a test mode; emulating (430) a defect in a selected transistor of said fault-free integrated circuit by providing the nodes from the plurality of nodes that are located at the interconnections of the selected transistor with respective predetermined voltage values; observing (440) a node from the plurality of nodes, said node being located between a transistor terminal and a primary pin of the fault-free version of the integrated circuit; and adding (450) the defect to the list if the emulated defect has caused a measurable response to the emulated defect on the observed node.

12. The method of claim 11 , wherein the steps of observing (440) the node and adding (450) the defect to the list are performed external to the fault-free version (300) of the integrated circuit.

13. The method of claim 11 or 12, wherein the step of selecting a transistor for determining a value of a structural parameter comprises selecting the transistor from the compiled (400) list.